JP5447631B2 - Data transfer circuit, solid-state imaging device, and camera system - Google Patents

Description

  The present invention relates to a data transfer circuit, a solid-state imaging device represented by a CMOS image sensor, and a camera system.

In recent years, CMOS image sensors have attracted attention as solid-state imaging devices (image sensors) that replace CCDs.
This requires a dedicated process for manufacturing the CCD pixel, requires a plurality of power supply voltages for its operation, and further requires a combination of a plurality of peripheral ICs to operate, resulting in a very complicated system. This is because the CMOS image sensor overcomes various problems such as.

  The CMOS image sensor can be manufactured by using a manufacturing process similar to that of a general CMOS integrated circuit, can be driven by a single power source, and further, an analog circuit or a logic circuit using the CMOS process. Can be mixed in the same chip, so it has several great advantages such as reducing the number of peripheral ICs.

The output circuit of a CCD is mainly a 1-channel (ch) output using an FD amplifier having a floating diffusion layer (FD).
In contrast, a CMOS image sensor has an FD amplifier for each pixel, and its output is a column parallel output type in which one row in the pixel array is selected and read out in the column direction at the same time. Mainstream.
This is because it is difficult to obtain a sufficient driving capability with an FD amplifier arranged in a pixel, and therefore it is necessary to lower the data rate, and parallel processing is advantageous.

  Various signal output circuits of this column parallel output type CMOS image sensor have been proposed, and one of the most advanced forms is an analog-to-digital converter (hereinafter referred to as ADC (Analog digital converter)) for each column. And a pixel signal is extracted as a digital signal.

  A CMOS image sensor equipped with such a column parallel ADC is disclosed in Non-Patent Document 1 and Patent Document 1, for example.

  FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device (CMOS image sensor) equipped with a column parallel ADC.

  The solid-state imaging device 1 includes a pixel array unit 2 as an imaging unit, a row scanning circuit 3, a column scanning circuit 4, a timing control circuit 5, an ADC group 6, a digital-analog converter (hereinafter referred to as a DAC (Digital-Analog converter)). And a data output circuit 9 including a counter 8 and a sense amplifier circuit (S / A).

The pixel array unit 2 is configured by unit pixels 2-1 including photodiodes and in-pixel amplifiers arranged in a matrix (matrix).
In the solid-state imaging device 1, as a control circuit for sequentially reading out signals from the pixel array unit 2, a timing control circuit 5 that generates an internal clock, a row scanning circuit 3 that controls row address and row scanning, and a column address And a column scanning circuit 4 for controlling the column scanning.

The ADC group 6 includes a ramp waveform RAMP in which the reference voltage generated by the DAC 7 is changed stepwise, and an analog obtained from the unit pixel 2-1 via the column lines V0, V1,... For each row line H0, H1,. A plurality of ADCs including a comparator 6-1 that compares signals and a memory device 6-2 that holds the count result of the counter 8 that counts the comparison time are arranged.
The ADC group 6 has an n-bit digital signal conversion function and is arranged for each column line V0, V1,... To constitute a column parallel ADC block 6-3.
The output of each memory device 62 is connected to a horizontal transfer line 6-4 having a 2n-bit width.
Then, 2n sense circuits, data output circuits 9 and output circuits corresponding to the respective horizontal transfer lines 6-4 are arranged.

  Here, the operation of the solid-state imaging device (CMOS image sensor) 1 will be described with reference to the timing chart of FIG. 2 and the block diagram of FIG.

After the first reading from the unit pixel 2-1 in the arbitrary row Hx to the column lines V0, V1,... Is stabilized, the DAC 7 causes the comparator 6-1 to change the reference voltage over time. A waveform PAMP is input, and comparison with the voltage of an arbitrary column line Vx is performed by the comparator 6-1.
In parallel with the staircase wave input of the ramp waveform RAMP, the counter 8 performs a first count.
Here, when the voltages of RAMP and Vx become equal, the output of the comparator 6-1 is inverted, and at the same time, a count corresponding to the comparison period is held in the memory device 6-2. At the time of the first reading, the reset component ΔV of the unit pixel 2-1 is read, and noise that varies for each unit pixel 2-1 is included as an offset in the reset component ΔV.
However, since the variation of the reset component ΔV is generally small and the reset level is common to all pixels, the output of an arbitrary column line Vx is approximately known.
Therefore, at the time of reading the reset component ΔV for the first time, the comparison period can be shortened by adjusting the ramp waveform (RAMP) voltage. In this example, ΔV is compared in a count period (128 clocks) of 7 bits.

In the second reading, in addition to the reset component ΔV, a signal component corresponding to the amount of incident light for each unit pixel 2-1 is read, and the same operation as the first reading is performed.
That is, after the second reading from the unit pixel 2-1 in any row Hx to the column lines V0, V1,... Is stabilized, the DAC 7 causes the comparator 6-1 to change the reference voltage over time. The ramp waveform RAMP is input and a comparison with the voltage of an arbitrary column line Vx is performed by the comparator 6-1.
In parallel with the staircase wave input of the ramp waveform RAMP, the counter 8 performs a second count.
Here, when the voltages of RAMP and Vx become equal, the output of the comparator 6-1 is inverted, and at the same time, a count corresponding to the comparison period is held in the memory device 6-2.
At this time, the first count and the second count are held at different locations in the memory device 6-2.
After the end of the AD conversion period, the column scanning circuit 4 outputs the first and second n-bit digital signals held in the memory device 6-2 through 2n horizontal transfer lines 6-4 and outputs data. The signal is detected by the circuit 9 and (subsequent signal)-(first signal) is output by the subtraction circuit, and then output to the outside. Thereafter, the same operation is repeated for each row, and the two-dimensional image is output. Is generated.

W. Yang et al. (W. Yang et. Al., “An Integrated 800x600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, Feb., 1999)

JP 2005-323331 A

  Since the solid-state imaging device (CMOS image sensor) as described above employs a column parallel reading method, scanning in the row direction (vertical scanning) is very slow, but scanning in the column direction (horizontal scanning) is 1H. (Horizontal scanning) Since all the data for one line must be read in time, the processing becomes very fast.

  However, in the solid-state imaging device (CMOS image sensor) as described above, the horizontal transfer line is very long, for example, about 7 mm in length, and is far from the side closer to the sense circuit due to parasitic capacitance, parasitic resistance, and the like. Variation in detection time occurs on the side.

In general, when the data of the counter latches of each column arranged over a wide range is serially read out using the data transfer line, all the locations with respect to the data latch timing of the data output circuit 9 including the sense amplifier circuit Data reading from is simultaneously performed.
In this case, it is necessary for the data output circuit to always latch the data from the near place and the data from the far place at the same timing.
However, when the points are very wide, latching at the same timing becomes difficult if the wiring delay is too large. As the transfer rate (clock frequency) increases, the influence of this wiring delay is greater.

  In recent years, image sensors have not only increased the number of pixels and the speed, but also with the expansion of the single-lens reflex camera market, the size of image sensors has increased considerably. The influence of this wiring delay is the image sensor row (horizontal) scanning. This hinders speeding up.

  The present invention can reduce the influence of the wiring delay on the transfer line to the data output circuit, can accurately take in the data in the data output circuit, and thus can increase the scanning speed. The object is to provide a data transfer circuit, a solid-state imaging device, and a camera system.

Multiple first aspect data transfer circuit of the present invention, to detect a plurality of transfer lines for transferring data, the data transferred to the transfer line, and outputs Captures the detection data in synchronization with the sampling clock A data output unit, a plurality of holding units arranged in parallel to hold data corresponding to an input level and transfer the data to the corresponding transfer line in response to a selection signal, and the capture clock A capture clock supply unit that supplies data to a plurality of data output units, a clock supply unit that supplies at least a master clock, and a scan that generates the selection signal in synchronization with a drive clock based on the master clock and outputs the selection signal to the holding unit a Department, the pseudo transfer lines arranged in the same direction as the transfer line, arranged corresponding to the parallel arrangement of the holding portion, which is generated in synchronism with the drive clock In response to the serial selection signal has the same frequency as the data, and has 1 and a plurality of pseudo data storage unit to be transferred to the pseudo-transfer line pseudo data corresponding a repeating pattern of 0, a, the transfer The line is wired in the parallel arrangement direction of the holding units and connected to the corresponding data output unit arranged in the direction, and the scanning unit is arranged and supplied corresponding to the parallel arrangement of the holding units. A plurality of selection signal generation units that output the selection signal to a corresponding holding unit in synchronization with the drive clock, a clock supply line that propagates a master clock and supplies the selection clock generation unit as a drive clock, wherein the said capture clock supply unit, the pseudo data, and supplies to the plurality of data output section as the receiving clock, the data output unit, and the capture clock A capture unit that captures data in a complementary manner in synchronization with both the falling edge and the rising edge at the time of the pseudo data level transition, and the data captured by the capture unit is a clock based on the master clock. And a data synchronization circuit which takes in again .

A data transfer circuit according to a second aspect of the present invention includes an imaging unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, a plurality of transfer lines that transfer data, and data transferred through the transfer lines. detection transferred, a plurality of data output section for write-output takes the detected data in synchronization with the receiving clock, and holds the data corresponding to the input level, in the transfer line corresponding to the data in response to a selection signal A plurality of holding units arranged in parallel, a capture clock supply unit that supplies the capture clock to the plurality of data output units, a clock supply unit that supplies at least a master clock, and a drive clock based on the master clock synchronously generates said selection signal to a scanning unit that outputs to the holding portion, and a pseudo transfer lines arranged in the same direction as the transfer line, a parallel arrangement of the holding portion In response to the selection signal generated in synchronization with the drive clock, pseudo data having the same frequency as the data and a repetitive pattern of 1 and 0 is applied to the corresponding pseudo transfer line. A plurality of pseudo data storage units to be transferred , wherein the transfer line is wired in the parallel arrangement direction of the holding units, connected to the corresponding data output unit arranged in the direction, and the scanning unit is A plurality of selection signal generators arranged corresponding to the parallel arrangement of the holding units and outputting the selection signals to the corresponding holding units in synchronization with the supplied driving clock; anda clock supply line supplied to the plurality of selection signal generator as, the capture clock supply unit includes a phase adjusting function of the supply clock, the pseudo data, the uptake Is supplied to the plurality of data output section as a lock, the data output unit takes to capture the falling edge, and the rising edge complementary data synchronously both of the time of the pseudo data level transition the above sampling clock And a data synchronization circuit that takes in the data fetched by the fetching unit again with a clock based on the master clock .

A data transfer circuit according to a second aspect of the present invention includes a solid- state image sensor, an optical system that forms a subject image on the solid-state image sensor, and a signal processing circuit that processes an output image signal of the solid-state image sensor. The solid-state imaging device detects and captures an imaging unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, a plurality of transfer lines that transfer data, and data that is transferred through the transfer lines. a plurality of data output section for write-output takes the detected data in synchronism with a clock, and holds the data corresponding to the input level, and transfers the data in response to a selection signal to a corresponding the transfer line, in parallel a plurality of holding portions arranged above the sampling clock and capture clock supply section for supplying to the plurality of data output unit, and a clock supply unit for supplying at least a master clock, based on the master clock Ku in synchronization with the drive clock to generate the selection signal, a scanning unit that outputs to the holding portion, and a pseudo transfer lines arranged in the same direction as the transfer line, arranged corresponding to the parallel arrangement of the holding portion In response to the selection signal generated in synchronization with the drive clock, a plurality of pseudo data having the same frequency as the data and having a repetition pattern of 1 and 0 are transferred to the corresponding pseudo transfer line. A pseudo data storage unit, wherein the transfer line is wired in a parallel arrangement direction of the holding unit, connected to the corresponding data output unit arranged in the direction, and the scanning unit is connected to the holding unit A plurality of selection signal generation units arranged in parallel with each other and outputting the selection signal to a corresponding holding unit in synchronization with a supplied drive clock, and the plurality of selection signal generation units propagating a master clock as a drive clock. Anda clock supply line for supplying a selection signal generation unit, the fetch clock supply unit includes a phase adjusting function of the supply clock, the pseudo data, and supplies to the plurality of data output section as the receiving clock The data output unit has a capturing unit that captures data in a complementary manner in synchronization with both the falling edge and the rising edge at the time of the pseudo data level transition serving as the capturing clock, and the capturing unit captures the data. It has a data synchronization circuit that takes in data again with a clock based on the master clock .

According to the present invention, the influence of wiring delay on the transfer line to the data output unit can be reduced.
Therefore, data can be taken in the data output unit accurately and with high accuracy.

It is a block diagram which shows the structural example of a column parallel ADC mounting solid-state image sensor (CMOS image sensor). 3 is a timing chart for explaining the operation of the solid-state imaging device of FIG. 1. It is a block diagram which shows the structural example of the solid-state image sensor (CMOS image sensor) mounted with column parallel ADC which concerns on one Embodiment of this invention. It is a figure which shows the more concrete structural example of the data transfer system of ADC of FIG. 3, a solid-state image sensor. 4 is a circuit diagram showing a specific example of a drive transistor Tr in the counter latch circuit according to the present embodiment. FIG. It is a figure which shows the 1st structural example of the data transfer type | system | group which concerns on this embodiment. It is a figure which shows the timing chart of the data transfer type | system | group of FIG. It is a figure which shows the 2nd structural example of the data transfer type | system | group which concerns on this embodiment. It is a figure which shows the timing chart of the data transfer type | system | group of FIG. It is a figure which shows the 3rd structural example of the data transfer type | system | group based on this embodiment. It is a figure which shows the circuit of FIG. 10 more concretely. It is a figure which shows the 4th structural example of the data transfer type | system | group which concerns on this embodiment. It is a figure which shows the 5th structural example of the data transfer type | system | group which concerns on this embodiment. It is a figure which shows the timing chart of the data transfer type | system | group of FIG. It is a figure which shows the 6th structural example of the data transfer type | system | group based on this embodiment. It is a figure which shows the 7th structural example of the data transfer type | system | group which concerns on this embodiment. It is a figure which shows the 8th structural example of the data transfer type | system | group which concerns on this embodiment. It is a figure which shows the timing chart of the data transfer type | system | group of FIG. It is a figure which shows the 9th structural example of the data transfer system which concerns on this embodiment. 4 is a timing chart for explaining the operation of the solid-state imaging device of FIG. 3. It is a figure for demonstrating the other example of the clock distribution in the column scanning circuit which concerns on this embodiment. It is a figure which shows an example of a structure of the camera system with which the solid-state image sensor which concerns on embodiment of this invention is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 3 is a block diagram illustrating a configuration example of a solid-state imaging device (CMOS image sensor) equipped with a column parallel ADC including a data transfer circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing a more specific configuration example of the data transfer system of the ADC and the solid-state imaging device of FIG.

  The solid-state imaging device 10 includes a pixel array unit 11 as an imaging unit, a row scanning circuit 12, a column scanning circuit 13, a timing control circuit 14, an ADC group 15, a DAC 16, and a plurality of sense amplifier (S / A) circuits 171. A data output circuit (data detection circuit) 17 is included.

The pixel array unit 11 is configured by arranging unit pixels 111 including photodiodes and in-pixel amplifiers in a matrix of M rows and N columns.
In the solid-state imaging device 10, as a control circuit for sequentially reading out signals from the pixel array unit 11, a timing control circuit 14 that generates an internal clock, a row scanning circuit 12 that controls row address and row scanning, and a column address. Further, a column scanning circuit 13 for controlling column scanning is disposed.

The ADC group 15 includes a ramp waveform RAMP in which the reference voltage generated by the DAC 16 is changed stepwise, an analog signal obtained from the unit pixel 111 via the column lines V0, V1,... For each row line H0, H1,. (N + 1) comparators (REF) 151 provided corresponding to the respective columns of the pixel array to be compared with each other, and an asynchronous up / down counter (hereinafter referred to as a counter) that receives the output of the comparator 151 and performs up / down counting .. Are arranged for each column line V0, V1,... Corresponding to each column of the pixel array, and a column parallel ADC block 153 is configured.
The output of each counter latch 152 is connected to the data transfer line 154. The data transfer line 154 is connected to the input of the sense amplifier circuit of the data output circuit 17.

The counter latch 152 having a function as a holding circuit is in a down-count state at the initial stage, performs a reset count, stops the down-count operation when the output COMPOUTi of the corresponding comparator 151 is inverted, and holds the count value.
At this time, the initial value of the counter latch 152 is an arbitrary value of the AD conversion gradation, for example, 0. During the reset count period, the reset component ΔV of the unit pixel 111 is read.
After that, the counter latch 152 enters the up-count state, performs data counting corresponding to the incident light quantity, and holds the count value corresponding to the comparison period when the output COMPOUTi of the corresponding comparator 151 is inverted.
The counter value held in the counter latch 152 is scanned by the column scanning circuit 13 and input to the sense amplifier circuit 171 through the data transfer line 154 as a digital signal.

  The column scanning circuit 13 is activated by, for example, the supply of the start pulse STR and the master clock MCK, and selects the corresponding selection line SEL in synchronization with the drive clock CLK (based on MCK) corresponding to the master clock MCK. Driven to read the latch data of the counter latch 152 to the data transfer line 154.

  Here, a more specific configuration example of the data transfer system of the ADC and the solid-state imaging device in FIG. 3 will be described with reference to FIG.

For example, as shown in FIG. 4, the counter latches 152-0 to 152 -n are configured by a counter CNT / latch LTC / drive DRV transistor (Tr) arranged for 1 bit (10 bits, 12 bits, etc.). The ADCs 15A are arranged in (n + 1) rows.
At the time of data transfer, a specific column is sequentially selected by the column scanning circuit 13 through the selection lines SEL0 to SELn.
The column scanning circuit 13 is sequentially selected by selecting a start position by a start pulse and comprising a shift register or the like.
Information (1 or 0) of the drive transistor Tr in the selected column is read to the data transfer line 154, detected by the sense amplifier circuit 171 of the data output circuit 17, and output to the output data processing circuit 20.

FIG. 5 is a circuit diagram showing a specific example of the drive transistor in the counter latch according to the present embodiment.
As shown in FIG. 5, the drive transistor DRVTr includes a select transistor NT1 composed of, for example, an n channel MOS (NMOS) connected in series between a predetermined potential (for example, ground potential) and a data transfer line 154, and an NMOS. The data transistor NT2 is formed. The gate of the select transistor NT1 is connected to select lines SEL0 to SELn driven by the column scanning circuit 13, and the gate of the data transistor NT2 is connected to the output of the latch LTC.

The selection line SEL0 to SELn driven by the output of the column scanning circuit 13 is connected to the data transfer line (S / A bus) 154, and the state of the transistor NT2 determined by the latch data is changed by a sense amplifier circuit 171 which is a data detection circuit. read out.
When the latch data is 1, a current path is created and current flows. When the latch data is 0, the current path is cut off and no current flows.

In the data transfer system according to the present embodiment, reading of the latched data of the counter latch 152 to the data transfer line 154 and detection and fetching of the data transferred through the data transfer line 154 are performed in the data input stage of the output data processing circuit 20. This is performed in synchronization with the drive clock CLK based on the master clock MCK by the arranged clock supply circuit 21.
In this embodiment, as viewed from the sense amplifier circuit 171, the delay of the drive clock CLK and the delay of data on the data transfer line (data bus) 154 can be canceled.
Hereinafter, the configuration of the data transfer system capable of canceling the delay of the drive clock CLK and the delay of data will be described with a plurality of examples.

<First configuration example of data transfer system>
FIG. 6 is a diagram illustrating a first configuration example of the data transfer system according to the present embodiment.

  The column scanning circuit 13 in the data transfer system 30 of the present embodiment basically constitutes a shift register 131, and sequentially shifts the start pulse STRT in synchronization with the drive clock CLK based on the master clock MCK to select the selection lines SEL0 to SEL0. Latches 131-0 to 131-n are formed as selection signal generation units made up of flip-flops, for example, which generate and output selection signals HSEL0 to HSELn for driving SELn.

In the column scanning circuit 13 of FIG. 6, the master clock supply line (wiring) LMCK1 of the master clock MCK is transmitted so that the drive clock CLK is evenly transmitted to the latches 131-0 to 131-n arranged in parallel. The latches 131-0 to 131-n arranged in parallel are wired at substantially the center in the arrangement direction.
Further, a drive clock supply line (wiring) LCLK1 of the drive clock CLK is connected to the master clock supply line LMCK1 via the buffer 132, and this drive clock supply line LCLK1 is wired in the arrangement direction of the latches 131-0 to 131-n. ing.
Then, from the vicinity of the clock input end of each of the latches 131-1 to 131-n of the drive clock supply line LCLK1, the drive clock distribution line LCLK2 extends in the wiring direction of the column line (direction orthogonal to the wiring direction of the drive clock supply line). −0 to LCLK2-n are wired.
In parallel with the master clock supply line 1, the start clock supply line LSTRT of the start pulse STRT is a data input terminal of the data output circuits 17-0 to 17-n of the column scanning circuit 13 (input terminal of the sense amplifier circuit 171). Are wired from the nearest end to the farthest end, and are further wired in the column line wiring direction (direction orthogonal to the driving clock supply line wiring direction), and the end thereof is connected to the data input terminal of the latch 131-0. ing.

  The data output circuits 17-0 to 17-n are connected to the ends of the data transfer lines 154-0 to 154-n, and amplify and read (detect) the transferred data. 171-n and the outputs of the sense amplifier circuits 171-0 to 171-n are captured in synchronization with the capture clock SACK and output to the output data processing circuit 20, for example, data synchronization circuits 172-0 to 172- consisting of flip-flops. n.

In the data transfer system 30 of FIG. 6, the master clock MCK supplied from the clock supply circuit 21 receives the data output circuits 17-0 to 17-as the capture clock SACK through the phase adjustment unit 22 that forms the capture clock supply unit. n.
Therefore, the data synchronization circuits 172-0 to 172-n of the data output circuits 17-0 to 17-n in the data transfer system 30 of FIG. 6 synchronize with the capture clock SACK via the phase adjustment unit 22, and the sense amplifier circuit 171. Latch the output from -0 to 171-n.
The phase adjustment unit 22 transmits the master clock MCK in the column scanning circuit 13 and the data transfer lines 154-0 from the counter latches 152-0 to 152-n as the selection lines SEL0 to SELn are driven by the drive clock CLK. In consideration of the read transfer processing to 154-n, the phase of the master clock MCK is adjusted (delay adjustment) so that accurate data capture can be performed.

In the data transfer system 30 of FIG. 6, for example, the start clock supply line LSTRT of the start pulse STRT, the master clock supply line LMCK1, the drive clock supply line LCLK1, and the drive clock distribution line from the output end of the clock supply circuit 21 A shield line LSLD1 is wired between LCLK2-0 and fixed at a predetermined fixed potential, for example, a ground potential, and suppresses the influence of interference between the clock supply lines.
Similarly, a predetermined fixed potential is applied between the master clock supply line LMCK1 and the drive clock supply line LCLK1 wired in parallel with the master clock supply line LMCK1 and to the output side of the phase adjustment unit 22 of the master clock MCK. For example, a shield line LSLD2 that is fixed to the ground potential and suppresses the influence of interference between the clock supply lines is provided.

FIG. 7 is a timing chart of the data transfer system of FIG.
In the data transfer system 30 of FIG. 6, as shown in FIG. 7, first, the shift register 131 that performs column (horizontal) scanning is synchronized with the drive clock CLK corresponding to the master clock MCK supplied by the clock supply circuit 21. The counter latch (data storage unit) 152 is sequentially selected by the selection lines SEL0, SEL1,..., SELn with a slight delay.
When the counter latch 152 is selected, data is transferred onto the data transfer lines 154-0 to 154-n and amplified by the sense amplifier circuits 171-0 to 171-n of the data output circuits 17-0 to 17-n. And read as AMPOUT [n: 0].
This read signal AMPOUT [n: 0] is finally synchronized with the master clock MCK by the acquisition clock SACK whose phase is adjusted (delayed) by the phase adjustment unit 22, and the data synchronization circuits 172-0 to 172-n. And sent to the output data processing circuit 20.

  In the data transfer system 30 of FIG. 6 having such a configuration, basically, the delay of the drive clock CLK and the data are viewed from the sense amplifier circuit 171 by appropriately performing the phase adjustment amount of the phase adjustment unit 22. It is possible to cancel the delay of data on the transfer line (data bus) 154, absorb data transfer variations on the data transfer lines 154-0 to 154-n, and perform accurate data detection and capture. It is.

  Incidentally, in the data transfer system 30 of FIG. 6, there is a possibility that it may be difficult to perform accurate data detection and capture depending on the case for the following reasons.

In particular, the phase adjustment by only the phase adjustment unit 22 is limited due to a clock frequency, a data transfer delay difference, and the like, and the data is synchronized to the data synchronization circuits 172-0 to 172-n by the fetch clock SACK adjusted in phase by the phase adjustment unit 22. As the operation of the column (horizontal) scanning circuit 13 increases in speed, there may be a case where the capture of the image does not succeed.
The reason for this is not only because of high speed, but also because the data has a fairly large skew component.

The skew component of data is roughly divided into four.
The first is a variation component of transfer delay caused by so-called manufacturing variation for each output amplifier or each MOS Tr of each data storage unit.
The second is whether the pattern of data flowing on the horizontal signal line is a dynamic pattern such as 1 · 0 · 1 · 0 · 1 · 0 ... or 0 · 0 · 0 · 1 · 0 · 0 · This is a variation component of transfer delay caused by a data pattern, such as whether it has an isolated pattern.
The third is caused by noise, such as board noise and clock noise. If it is large noise, it will cause a symptom that the data once confirmed will be turned over. When data overlaps with noise, a phenomenon such as chattering occurs near the threshold value of the output amplifier, and it takes time until data is determined, which may be a data skew component.
The fourth reason is that the data comes from the far end (left end in the figure) or near end (right end in the figure) when viewed from the sense amplifier circuit 171 of the data output circuit 17. This is a variation component of transfer delay.

As a result, the data outputs AMPOUT [n: 0] of the sense amplifier circuits 171-0 to 171-n have a considerably large data indefinite period, and when the far end is selected as shown in FIG. Since the data transfer delay after the selection is different from the case where is selected, it may be difficult to set an appropriate capture timing with one clock called the capture clock SACK. In addition, depending on the selected position, either the setup time (setup time) or the hold time (hold time) will become strict, and in some cases, it may not be possible to create a timing that allows stable capture of all data. There is also a risk.
The skew component of the difference in transfer distance is inevitably present in the structure of the image sensor. In recent years, not only with the increase in the number of pixels and the speed, but also with the expansion of the single lens reflex camera market, The increase in size is also progressing considerably, and countermeasures against skew due to the transfer distance are important in speeding up the row (horizontal) scanning of the image sensor.

  Based on the above, a configuration example of a data transfer system that can sufficiently cope with a CMOS image sensor having a large number of pixels and a high speed will be described.

<Second configuration example of data transfer system>
FIG. 8 is a diagram illustrating a second configuration example of the data transfer system according to the present embodiment.

  The data transfer system 30A in FIG. 8 is different from the data transfer system 30 in FIG. 6 in that in the column scanning circuit 13, the master clock supply line LMCK1A is arranged in the arrangement direction of the latches 131-0 to 131-n arranged in parallel. To the position beyond the formation position of the latch 131-0 on the farthest end from the data input end of the data output circuits 17-0 to 17-n (the input end of the sense amplifier circuit 171). Further, it is wired so as to be connected to the end of the drive clock supply line LCLK1 via the buffer 132 in the column line wiring direction (direction orthogonal to the drive clock supply line wiring direction).

8, in the column scanning circuit 13, the drive clock supply line LCLK1 is connected to the master clock supply line LMCK1A by the data input terminals (sense amplifier circuit) of the data output circuits 17-0 to 17-n. 171 is formed so as to be folded back on the farthest end side.
Then, from the vicinity of the clock input end of each of the latches 131-1 to 131-n of the drive clock supply line LCLK1, the drive clock distribution line LCLK2 extends in the wiring direction of the column line (direction orthogonal to the wiring direction of the drive clock supply line). −0 to LCLK2-n are wired.
Therefore, in the data transfer system 30A of FIG. 8, the latch 131-0 located from the data input terminal (the input terminal of the sense amplifier circuit 171) of the data output circuits 17-0 to 17-n to the sense amplifier The drive clock CLK is sequentially supplied from the input ends of the circuits 171-0 to 171-n toward the latch 131-n located on the nearest end side, and selection signals HSEL0 to HSELn for driving the selection line SEL0 are sequentially output. The
In other words, in the data transfer system 30A of FIG. 8, the drive clock CLK and the data read from each counter latch 152 to the sense amplifier circuits 171-0 to 171-n are wired in the same direction, and the sense amplifier circuit As viewed from 171-0 to 171-n, the wiring capacity of the drive clock CLK of the column scanning circuit 13, the delay due to the time constant of the resistance, and the wiring capacity of the data on the data transfer lines (data bus) 154-0 to 154-n The delay due to the time constant of the resistor is cancelled.
Preferably, the sum of the delay component of the drive clock CLK and the delay component from the column counter (counter latch) to the sense amplifier circuit is constant regardless of the column position. As a result, a sufficient timing margin for driving the data output circuit 17 can be obtained, so that high-speed driving and high-speed reading are possible.

  Further, in the data transfer system 30A of FIG. 8, the connection end to the drive clock distribution line LCLK2-n which is the final end of the drive clock supply line LCLK1 is in the direction in which the latches 131-0 to 131-n are provided (the row line Wiring direction) extending to the arrangement side of the clock supply circuit 21, passing through the repeater 23, then wired in the column line wiring direction (direction orthogonal to the driving clock supply line wiring direction), and phase (delayed) ) The capture clock SACK is generated via the adjustment unit 22A.

  In parallel with the master clock supply line LMCK1A, the start clock supply line LSTRT of the start pulse STRT is a data input terminal of the data output circuits 17-0 to 17-n of the column scanning circuit 13 (input terminal of the sense amplifier circuit 171). Are wired from the nearest end to the farthest end, and are further wired in the column line wiring direction (direction orthogonal to the driving clock supply line wiring direction), and the end thereof is connected to the data input terminal of the latch 131-0. ing.

In the data transfer system 30A of FIG. 8, for example, a predetermined interval is provided between the start clock supply line LSTRT of the start pulse STRT, the master clock supply line LMCK1, and the drive clock distribution line LCLK2-0 from the output end of the clock supply circuit 21. A shield line LSLD1A that is fixed at a fixed potential, for example, a ground potential, and suppresses the influence of interference between the clock supply lines is provided.
Similarly, between the master clock supply line LMCK1A and the drive clock supply line LCLK1 wired in parallel with the master clock supply line LMCK1A, the drive clock distribution lines LCLK2-0 to LCLK2-n of the drive clock supply line LCLK1 Shield lines LSLD2A and LSLD3A that are fixed to a predetermined fixed potential, for example, a ground potential and suppress the influence of interference between the clock supply lines, are wired on the wiring side and the output side of the phase adjustment unit 22 of the master clock MCK. Has been.
Further, since the power supply wiring and the like are formed on the opposite side (downward in FIG. 8) opposite to the wiring side of the shield line LSLD1A with respect to the start clock supply line LSTRT in FIG. 8, the power supply wiring and the start clock supply line LSTRT A shield line LSLD4A is routed between them.
When the master clock supply line LMCK1A is wired close to the power supply wiring instead of the start clock supply line LSTRT, the shield line LSLD4A is wired between the master clock supply line LMCK1A and the power supply wiring. .

  FIG. 9 is a timing chart of the data transfer system 30A in FIG.

  9A shows the waveform of the output terminal of the master clock MCK in the clock supply circuit 21 of FIG. 8, and FIG. 9B shows the data input terminal of the data output circuits 17-0 to 17-n of the drive clock supply line LCLK1. The waveform of the clock supply terminal from the (input terminal of the sense amplifier circuit 171) to the latch 131-0 on the farthest end side is shown in (C) of the data output circuits 17-0 to 17-n of the drive clock supply line LCLK1. The waveform at the clock supply terminal from the data input terminal (the input terminal of the sense amplifier circuit 171) to the latch 131-n which is the closest terminal is shown in (D) from the output of the phase adjustment unit 22A to the data output circuit 17- (E) shows the clock of the data synchronization circuit 172-0 of the data output circuit 17-0 of the farthest end from the output of the phase adjustment unit 22A. (F) is a column selection signal (selection pulse) SEL0 output from the latch 131-0 of the column scanning circuit 13, and (G) is a column output from the latch 131-0 of the column scanning circuit 13. A selection signal (selection pulse) SELn (for example, n = 4000), (H) is read data (transfer data) to the data transfer line 154-0 of the uppermost counter latch 152-0, and (I) is data transfer. (J) shows the data at the input terminal to the sense amplifier circuit 171-n of the transfer data of the data transfer line 154-n. (K) shows the output data of the data synchronization circuit 172-0 in the data output circuit 17-0, and (L) shows the data synchronization circuit 172-n in the data output circuit 17-n. The force data, respectively.

As can be seen from FIG. 9, the data transfer system 30A in FIG. 8 indicates the direction of data read from the drive clock CLK and the counter latches 152-0 to 152-n of each column to the sense amplifier circuits 171-0 to 171-n. Since the drive clock supply line LCLK1 and the data transfer lines 154-0 to 154-n are wired so as to be the same, the delay of the drive clock CLK and the data when viewed from the sense amplifier circuits 171-0 to 171-n. Data delay on the transfer line (data bus) is canceled.
That is, according to the data transfer system 30A of FIG. 8, the sum of the delay component of the drive clock CLK and the delay component from the counter latch of each column to the sense amplifier circuits 171-0 to 171-n is constant regardless of the column position. It becomes.
Therefore, a sufficient timing margin for driving the sense amplifier circuits 171-0 to 171-n and the data synchronization circuits 172-0 to 172-n can be secured, so that high-speed driving and high-speed reading are possible. ing.

Consider further the data transfer system 30A of FIG.
For example, when the column N1 adjacent (close) to the data output circuit 17 is selected, the clock and data timing difference Tdiff_n in the data output circuit 17 is as follows.

      Tdiff_n ≒ T1

  On the other hand, when the column F1 away from the data output circuit 17 is selected, the clock and data timing difference Tdiff_f in the data output circuit is as follows.

      Tdiff_f ≒ T2

And from the physical layout
T1 ≒ T2
Therefore, the following relationship is obtained.

      Tdiff_f ≒ Tdiff_n

As described above, the data timing difference is substantially the same depending on the location of the selected column. This means that it is constant regardless of the location of the selected column.
Accordingly, the operating frequency F of the subsequent circuit at this time is as follows.

  F = 2 x 1 / (Tdiff_f − Tdiff_n) = ∞

  This means that the upper limit of the actual operating frequency is limited by the upper limit operating frequency of the subsequent circuit itself, but there is no timing constraint due to the column selection location.

  As described above, according to the data transfer system 30A of FIG. 8, the sum of the delay component of the drive clock CLK and the delay component from the counter latch of each column to the sense amplifier circuits 171-0 to 171-n is related to the column position. Therefore, a sufficient timing margin for driving the sense amplifier circuits 171-0 to 171-n and the data synchronization circuits 172-0 to 172-n can be secured, so that high-speed driving and high-speed reading are possible. There is an advantage that it becomes possible.

<Third configuration example of data transfer system>
FIG. 10 is a diagram illustrating a third configuration example of the data transfer system according to the present embodiment. FIG. 11 is a diagram more specifically showing the circuit of FIG.

  The data transfer system 30B shown in FIGS. 10 and 11 is configured to solve a transfer distance-dependent problem among data skew problems in column (horizontal) scanning.

First, the basic principle of the third configuration example will be described with reference to FIG.
The data transfer system 30B is different from the data transfer system 30 in FIG. 6 in that the pseudo clock storage unit 24-0 to which fixed data has been written is provided separately from the data storage unit corresponding to each bit of the counter latch. .., And the continuous data of 1 · 0 · 1 · 0... Is read to the pseudo clock transfer line 25 together with the imaging data.
In the data transfer system 30B, the data read out to the pseudo clock transfer line 25 passes through the sense amplifier circuit 26 and the phase adjustment unit 27, and has an appropriate phase with respect to the capture timing of AMPOUT [n: 0]. It is set and used as it is as the fetch clock SACKD of the data synchronization circuits 172-0 to 172-n.
By adopting such a configuration, since the data and the clock always have the same transfer distance, the transfer delay due to the transfer distance always has the same value for both the data and the clock.
Therefore, among the four skew components described above, the skew component due to the fourth transfer distance is canceled accurately, the data capture margin is expanded, and the data can be stably captured.

FIG. 11 shows a configuration that further embodies FIG.
In the data transfer system 30B, as shown in FIG. 11, the configuration of the pseudo clock storage units 24-0 to 24-n is the same as that of the drive transistor DRVTr that is the output stage of the counter latches 152-0 to 152-n. Have.
That is, the pseudo clock storage units 24-0 to 24-n are, as shown in FIG. 11, select circuits composed of, for example, NMOSs connected in series between a predetermined potential (for example, ground potential) and the pseudo clock transfer line 25. A transistor PNT1 and a data transistor PNT2 made of NMOS are used.
The gate of the select transistor PNT1 is connected to select lines SEL0 to SELn driven by the column scanning circuit 13.
Then, the gates of the data transistors PNT2 in the pseudo clock storage units 24-0, 24-2,..., 24-n-1 (even numbers in FIG. 11) are grounded via the inverter INV1. Connected to potential.
On the other hand, the gates of the data transistors PNT2 in the pseudo clock storage units 24-1, 24-3,..., 24-n with odd numbers (even columns in FIG. 11) are directly connected to the ground potential. Has been.

  As described above, in this example, the pseudo clock storage units 24-0 to 24-n have the same basic configuration as the counter latches 152-0 to 152-n, but do not have a latch for storing data. Continuous data of 1, 0, 1, 0,... Is created by physically embedding whether 1 is input or 0 is input to the gate of the data transistor PTN2 with or without the inverter INV1.

According to this example, it is possible to remove a position-dependent component caused by the data transfer distance from the skew component of the data that has hindered the speeding up at the time of horizontal transfer of the data of the image pickup unit. This can contribute to further speeding up or upsizing.
In addition, since data and a clock are transferred on the same transfer line, it is possible to relatively easily absorb the influence of process variations between chips and between wafers, and the yield can be improved. In addition, since the capture margin for data synchronization can be expanded, the design is facilitated, and the design period and man-hours can be reduced.

<Fourth Configuration Example of Data Transfer System>
FIG. 12 is a diagram illustrating a fourth configuration example of the data transfer system according to the present embodiment.

The data transfer system 30C in FIG. 12 differs from the data transfer system 30B in FIGS. 10 and 11 in that it is a configuration example in the case of using differential sense amplifier circuits 171C-0 to 171-n.
Although the basic configuration is almost the same, since it is differential, there are two data transfer lines for each channel (ch), and both the counter latches 152C-0 to 152C-n and the pseudo clock storage units 24C-0 to 24C-n Complementary data is supplied to the data transfer lines 154-0P, 154-0M to 154-nP, 154-nM and the pseudo clock transfer lines 25P, 25M, respectively.

As shown in FIG. 12, the counter latches 152C-0 to 152C-n are NMOS select switches connected in series between a predetermined potential (for example, ground potential) and data transfer lines 154-0M to 154-nM. A transistor NT1, a data transistor NT2 made of NMOS, a select transistor NT3 made of NMOS connected in series between a predetermined potential (for example, ground potential) and data transfer lines 154-0P to 154-nP, and an NMOS Data transistor NT4.
The gates of the select transistors NT1 and NT3 are connected to selection lines SEL0 to SELn driven by the column scanning circuit 13, the gate of the data transistor NT2 is connected to the output of the latch LTC, and the gate of the data transistor NT4 is connected to the inverter INV2. To the output of the latch LTC.

As shown in FIG. 12, the pseudo clock storage units 24C-0 to 24C-n are connected in series between a predetermined potential (for example, ground potential) and the pseudo clock transfer line 25P, and are, for example, select transistors PNT1 made of NMOS. A data transistor PNT2 made of NMOS, a select transistor PNT3 made of NMOS, for example, and a data transistor PNT4 made of NMOS, connected in series between a predetermined potential (for example, ground potential) and the pseudo clock transfer line 25M, have.
The gates of the select transistors PNT1 and PNT3 are connected to selection lines SEL0 to SELn driven by the column scanning circuit 13.
Then, the gates of the data transistors PNT2 in the pseudo clock storage units 24C-0, 24C-2,..., 24C-n-1 with even numbered symbols (in the odd number columns in FIG. 11) are grounded via the inverter INV1. The gate of the data transistor PTN4 is directly connected to the ground potential.
On the other hand, the gates of the data transistors PNT2 in the pseudo clock storage units 24C-1, 24C-3,..., 24C-n with odd numbers (even columns in FIG. 11) are directly connected to the ground potential. The gate of the data transistor PTN4 is connected to the ground potential via the inverter INV3.

  According to the data transfer system 30C of FIG. 12, by adopting the differential configuration, in addition to the above-described effect, the noise margin becomes large, and the third noise component among the four skew components described above is caused. The effect that things decrease significantly can be acquired.

<Fifth Configuration Example of Data Transfer System>
FIG. 13 is a diagram illustrating a fifth configuration example of the data transfer system according to the present embodiment.
FIG. 14 is a timing chart of the data transfer system of FIG.

  The data transfer system 30D in FIG. 13 is different from the data transfer system 30C in FIG. 12 in that the data output in the data output circuit is changed to the edge of pseudo clock data level switching, specifically, from the high level “1” to the low level. This is performed using both the falling edge at the transition to the level “0” and the rising edge at the transition from the low level “0” to the high level “1”. The adjusted master clock is re-acquired as the second acquisition clock, and the data is output to the output data processing circuit 20.

Each data output circuit 17D-0 to 17D-n includes a first latch 173-0 between the output of the sense amplifier circuit 171D-0 to 171D-n and the data input of the data synchronization circuit 172D-0 to 172D-n. 173-n, second latches 174-0 to 174-n, first switches 175-0 to 175-n, and capture circuits 177-0 to 177-n including second switches 176-0 to 176-n Is arranged.
Specifically, the first latch 173-0 to 173-n and the second latch 174-0 to 174-n are connected in parallel to the output of the sense amplifier circuits 171D-0 to 171D-n, and the first latch 173- 0-173-n inverts the capture clock SACK by the phase adjustment unit 27 and inputs it to the clock input terminal, and the second latches 174-0 to 174-n directly input the capture clock SACK to the clock input terminal.
The outputs of the first latches 173-0 to 173-n are connected to the data inputs of the data synchronization circuits 172D-0 to 172D-n via the first switches 175-0 to 175-n, and the second latch 174- The outputs of 0 to 174-n are connected to the data inputs of the data synchronization circuits 172D-0 to 172D-n via the second switches 176-0 to 176-n.
The first switches 175-0 to 175-n are turned on when the capture clock SACK is supplied to the negative input and the capture clock SACK is at a low level, and the latch data of the first latches 173-0 to 173-n is data-synchronized. Supply to the data inputs of the circuits 172D-0 to 172D-n.
The second switches 176-0 to 176-n are turned on when the capture clock SACK is supplied and the capture clock SACK is at a high level, and the latch data of the second latches 174-0 to 174-n is transferred to the data synchronization circuit 172D-. Supply 0 to 172D-n data input.
As described above, the first switches 175-0 to 175-n and the second switches 176-0 to 176-n are turned on and off in a complementary manner. As a result, the latch data of the first latches 173-0 to 173-n The latch data of the second latches 174-0 to 174-n are supplied complementarily (alternately) to the data inputs of the data synchronization circuits 172D-0 to 172D-n.
The reason for this configuration is shown below.

In the column scanning circuit 13, the shift register 131 operates in synchronization with the drive clock CLK based on the master clock MCK. For example, when the drive clock CLK is distributed using a clock tree structure, the clock wiring to the shift register 131 is It tends to be longer.
In this case, since the tree structure is also taken into consideration, the clock wiring delay tends to increase, and the output selection signals HSEL0, HSEL1,... Of the latches 131-0 to 131-n of the shift register 131 with respect to the master clock MCK. ..., HSELn may be output with some delay.
The counter latches 152-0 to 152-n selected by the selection signals HSEL0, HSEL1,..., HSELn and the pseudo clock storage units 24-0 to 24-n transfer stored data to the data transfer line 154 in the current mode. 0 to 154-n (154-0P to 154-nP, 154-0M to 154-nM) and the pseudo clock transfer line 25 (25P, 25M), but the input impedance of these transfer lines is not 0. Even if a current mode signal is passed, some voltage fluctuations occur.
For this reason, the charge / discharge time of the time constant due to the parasitic capacitance and resistance of the transfer line is required, but when viewed from the output amplifier, the far-end has a larger parasitic resistance and the near-end has a larger time constant. The constant looks small. Therefore, due to the difference in charge / discharge time, there is a difference in transfer delay between the far end data and the near end data.

For this reason, a configuration is adopted in which the pseudo clock for data capture is transferred on the pseudo clock transfer line 25 (25P, 25M) like the data. However, as shown in the timing chart of FIG. The clock frequency is only half that of the master clock MCK and the same frequency as the data.
Therefore, in order to capture data using this, it is necessary to use both the rising edge and the falling edge. In FIG. 13, an example of the above-described capturing circuits 177-0 to 177-n is introduced.
The capture circuits 177-0 to 177-n capture data at the rising edge of the clock, and have two ordinary latches that hold data and two switches that select the output during the high level H period of the clock.

At the instant when the capture clock SACD supplied to the first and second latches 173-0 to 173-n and 174-0 to 174-n rises, the second latches 174-0 to 173-n of the two latches Latches the data, and is held while the capture clock SAKD is at the high level H. Since the second switches 176-0 to 176-n conduct during the period when the capture clock SACD is at the high level H, the latch data of the second latches 174-0 to 174-n are output as LAOUT0 to n.
Next, at the moment when the capture clock SAKD falls, data is secured and held by the first latches 173-0 to 173-n to which the inverted clock is supplied, and the analog switches behind the first latches 175-0 to 175- n switches to a conductive state, and the second switches 176-0 to 176-n switch to a non-conductive state. Therefore, this time, the latch data of the first latches 173-0 to 173-n is output as LAOUT.

In this way, data can be captured and synchronized using both edges of the capture clock SACD. Since the synchronization capture circuit corresponding to both edges is composed of two switches with two latches, it can be configured with the same area as a normal F / F.
Since the capture clock SACD basically has the same transfer delay as the data regardless of the location of the selected data, it is output in the same phase as the data. If this is the case, data may be captured in an indefinite period in which the edges of the data overlap. Therefore, the phase adjustment unit 27 can obtain an appropriate setup time and hold time (setup / hold time) for the data latch. Thus, the phase is adjusted to an appropriate place.
The setup time and hold time with respect to the capture clock SAKD of the output data AMPOUT [n: 0] of the sense amplifier circuits 171-0 to 171-n thus secured are far from those of the first configuration example shown in FIG. A constant value can always be secured regardless of the end or the near end.

Now, the data LAOUT [n: 0] synchronized by the capture clock SAKD is caused by the first variation, the second pattern, and the third of the four skew components described above by the synchronization. Three components due to the first noise were removed.
However, since synchronization is performed using the capture clock SACD, there is a possibility that only the fourth position-dependent skew component remains when the master clock MCK is used as a reference. Eventually, since it is necessary to pass data to the output data processing circuit 20 operating with the master clock MCK, it is necessary to synchronize the data with the master clock MCK.
Although it is possible to change to the master clock MCK while having a skew component due to position dependency, in FIG. 13, the transfer is again made to the recapture master clock MKD generated from the master clock MCK using the phase adjustment unit 28. As an example, a configuration of finally switching to the master clock MCK after performing the above is given.
As a configuration, the data LATOU [n: 0] is only recaptured by the master clock MCKD with a normal flip-flop F / F, but in accordance with the phase of the capture clock SACD, the most appropriate timing is obtained. The phase of the recapture master clock MCKD is set. Since the recapture master clock MCKD is based on MCK, it does not have a position dependent component.

Although the setup time and the hold time margin differ between the far end and the near end due to the position-dependent component of the capture clock SAKD, three of the four skew components have already been removed, so that it is shown in FIG. As shown in the first configuration example, it can be seen that the four skew components are captured all at once and synchronized with the clock SACK, so that the synchronization can be performed with a sufficient margin.
In the configuration of FIG. 13, among the four skew components, the three components caused by the first variation, the second pattern, the third noise, and the fourth position-dependent component It can be said that the margin of each capture can be expanded because it is divided into two and removed by synchronizing with the capture clock SAKD and the recapture master clock MCKD.

By the way, in each of the above-described embodiments, the phase adjustment unit 22 uses the propagation delay in the column scanning circuit 13 of the drive clock CLK, and the counter latches 152-0 to 152-n accompanying the drive of the selection lines SEL0 to SELn by the drive clock CLK. In consideration of the read transfer processing to the data transfer lines 154-0 to 154-n, the phase of the master clock MCK is adjusted (delay adjustment) so that accurate data capture can be performed.
However, while the propagation delay in the column scanning circuit 13 is mainly caused by the wiring load of the drive clock supply line LCLK1 and the data transfer lines 154-0 to 154-n, the phase adjustment unit 22 (22A, 27, 28) delays the master clock MCK for adjustment and generates the capture clock SACK because of the driving capability of the transistor. That is, a large timing margin is required for the column scanning circuit 13 in order to enable accurate data capture even when these two independent delay factors vary.

  Hereinafter, a configuration example for realizing another method for securing a timing margin will be described.

<Sixth Configuration Example of Data Transfer System>
FIG. 15 is a diagram showing a data transfer system 30E of the sixth configuration example according to the present embodiment.
The data transfer system 30E of the sixth configuration example has a configuration obtained by improving the data transfer system of the first configuration example shown in FIG. 6, and there are the following two differences.

The first difference is that the data output circuit 17E is composed of two stages of F / Fs.
That is, the data output circuit 17E is a data synchronization circuit 172E that captures the output from the sense amplifier circuit 171 in synchronization with the capture clock SACK, and a data output that outputs the data captured by the data synchronization circuit 172E in synchronization with the master clock MCK. Circuit 178.
Thus, the data synchronization circuit 172E reliably captures (latches) the data, and the data output circuit 178 outputs the data in synchronization with the master clock MCK, thereby guaranteeing the phase relationship with the output data processing circuit 20. Yes.

The second difference is that the drive clock supply line LCLK1 that is the wiring of the drive clock CLK and the capture clock supply line LSACK that is the capture clock SACK have the same wiring load.
In FIG. 15, this wiring load is expressed in the form of a resistor and a capacitor, the wiring load of the drive clock supply line LCLK1 is represented as RCLK, and the wiring load of the take-in clock supply line LSACK is represented as RSACK.
That is, the sixth configuration example of the data transfer system illustrated in FIG. 15 is configured so that a wiring load approximately equal to the wiring load RCLK of the drive clock supply line LCLK1 is taken in and is included in the clock supply line LSACK as the wiring load RSACK. Thus, the delay elements of the drive clock CLK and the capture clock SACK are made equal. Thereby, the phase relationship between the data scan synchronized with the drive clock CLK and the data capture (latch) synchronized with the capture clock SACK can be determined.

Incidentally, in the drive clock supply line LCLK1, a gate for the drive clock CLK to drive the shift register 131 exists as a part of the wiring load RCLK. As shown in FIG. 14, in the data transfer system 30E of the sixth configuration example, this gate load is expressed as GCLK.
Here, in the sixth configuration example of the present embodiment, a gate load similar to the gate load GSACK is provided on the side of the take-in clock supply line LSACK as GSACK, so that the drive clock CLK and the take-in clock SACK are included. Make delay elements equal. As a result, the delay elements of the drive clock CLK and the capture clock SACK become more equal, and the phase relationship between the data scan synchronized with the drive clock CLK and the data capture (latch) synchronized with the capture clock SACK can be further determined.

  In the sixth configuration example of the data transfer system according to the present embodiment, the drive clock supply line LCLK1 and the capture clock supply line LSACK are configured to have the same level of wiring loads RCLK and RSACK, respectively, as described above. Thus, since the delay elements of the drive clock CLK and the capture clock SACK are equal, the delay element of the phase adjustment unit can be eliminated without providing the phase adjustment unit, and data reading (scanning) and capture by the drive clock CLK can be performed. The phase relationship with data capture (latching) by the clock SACK can be determined.

<Seventh Configuration Example of Data Transfer System>
Next, a seventh configuration example of the data transfer system according to the present embodiment will be described.
FIG. 16 is a diagram illustrating a seventh configuration example of the data transfer system according to the present embodiment.
In the data transfer system 30F of the seventh configuration example in FIG. 16, the gate load GSACKF of the capture clock supply line LSACK is reduced as compared with the gate load GSACK of the data transfer system 30E of the sixth configuration example described above. This is different from the data transfer system 30E of the sixth configuration example.
This gate load GSACKF is configured to be freely set in the range from 0 to the gate load GCLK.

  Since the wiring load RCLK of the drive clock supply line LCLK1 and the wiring load RSACK of the capture clock supply line LSACK are the same as in the sixth configuration example described above, the timing at which the drive clock CLK is input to the shift register 131, The timing at which the data synchronization circuit 172E latches data in synchronization with the capture clock SACK differs by the delay caused by the gate load GCLK and the gate load GSACK (the drive clock is different from the capture clock in the gate load). Is delayed by an amount corresponding to

  With this configuration, for example, in the data transfer system 30E of the above-described sixth configuration example, the propagation delay caused by the wiring load RCLK and the gate load GCLK of the drive clock CLK and the wiring load RSACK and the gate load GSACK of the fetch clock SACK Even in the case where the propagation delay caused by the error does not match well, the data transfer system 30F of the seventh configuration example can freely set the gate load GSACKF on the side of the take-in clock supply line LSACK as described above. Since the wiring load of the capture clock supply line LSACK is freely variable, the gate load GSACKF of the capture clock supply line LSACK is adjusted so that the delay due to the drive clock CLK and the delay due to the capture clock SACK are well matched. It can be successfully determine the phase relationship between the drive clock CLK synchronized with the data read and capture clock SACK synchronized with data acquisition (latch).

<Eighth configuration example of data transfer system>
Next, an eighth configuration example of the data transfer system according to the present embodiment will be described.
FIG. 17 is a diagram showing a data transfer system 30G of the eighth configuration example according to the present embodiment.
The data transfer system 30G of the eighth configuration example in FIG. 17 is different from the sixth configuration example described above in that the fetch clock supply line LSACK is configured to have no gate load.

  In the case of the data transfer system 30G of the eighth configuration example according to the present embodiment, data reading synchronized with the driving clock CLK is equivalent to the gate load GCLK of the driving clock supply line LCLK1 rather than data capturing synchronized with the capturing clock SACK. There will definitely be a delay. However, since the main causes of the delay of the drive clock CLK and the delay of the capture clock SACK are the wiring loads RCLK and RSACK, when one of the delays increases, the other delay also increases. Therefore, even if the delay state changes due to manufacturing variations of wirings or the like, the phase relationship of these clocks is maintained, thereby making it easy to secure a setup time margin.

An example of a timing chart in the eighth configuration example is shown in FIG.
18A shows the waveform of the output end of the master clock MCK, FIG. 18B shows the waveform of the clock supply end inputted to the farthest end latch 131-0 from the data output circuit 17E, and FIG. The waveform of the clock supply terminal input to the nearest latch 131-n from the output circuit 17E, (D) the waveform of the clock supply terminal input to the data synchronization circuit 172E of the capture clock SACK, and (E) the counter. The latch 152-0 reads the read data transferred by the read data transfer line 154, (F) shows the read data transferred by the counter latch 152-n by the read data transfer line 154, and (G) shows the output data of the data synchronization circuit 172E. (H) shows the output data of the data output circuit 178, respectively.
As shown in FIG. 18, in the data transfer system 30G of the eighth configuration example, the timing control of the data synchronization circuit 172E is ensured, and a sufficient timing margin can be secured.

<Ninth Configuration Example of Data Transfer System>
Next, a ninth configuration example of the data transfer system according to the present embodiment will be described.
FIG. 19 is a diagram showing a data transfer system 30H of the ninth configuration example according to the present embodiment.
In the data transfer system 30H of the ninth configuration example, as shown in FIG. 19, the capture clock supply line LSACKH is wired shorter than the drive clock supply line LCLK1.
As a result, the wiring load RSACKH of the fetch clock supply line LSACKH takes a smaller value than the wiring load RCLK of the drive clock supply line LCLK, and the fetch clock SACKH has a smaller delay than the drive clock CLK. That is, the data scan synchronized with the drive clock CLK is surely delayed from the data capture synchronized with the capture clock SACKH, and the phase relationship between the drive clock CLK and the capture clock SACKH is determined. For this reason, the data transfer system 30H of the ninth configuration example can secure a sufficient timing margin.

  In the data transfer system 30H of the ninth configuration example shown in FIG. 19, the gate load GSACK is configured to be smaller than the gate load GCLK on the drive clock side as in the seventh configuration example of the data transfer system described above. The timing margin may be adjusted so as to be secured.

Further, as a modification of the data transfer system 30H of the ninth configuration example shown in FIG. 19, in contrast to the data transfer system 30H, instead of shortening the capture clock supply line LSACKH, the drive clock supply line LCLK1 is captured. It may be configured to be longer than the supply line LSACK and to provide a delay element for the capture clock SACK on the drive clock CLK side. Similarly, an extra gate load GCLKH may be connected to the drive clock supply line LCLK1, and a delay element for the capture clock SACK may be provided on the drive clock CLK side.
That is, in the ninth configuration example, the wiring load RCLK including the gate load of the drive clock supply line LCLK1 is made variable, or the wiring load RSACK including the gate load of the fetch clock supply line LSACK is made variable, or these Both of these are made variable so that the wiring load of each supply line can be set freely, thereby establishing the phase relationship between the drive clock CLK and the capture clock SACK and reliably performing data scanning and data capture. Will be able to.
As a method of making the wiring load of each supply line variable, in the above-described sixth to ninth configuration examples, the gate load GSACK of the take-in clock supply line LSACK, which adjusts the length of the supply line (running), is used. However, the present invention is not limited to this, and other methods may be used.

  As described above, in the sixth to ninth configuration examples of the data transfer system, the wiring load is increased by adjusting the lengths (routes) of the supply lines of the drive clock CLK and the capture clock SACK, or the gate load. By providing a delay element to each clock and adjusting the phase relationship, a sufficient timing margin can be secured.

  Next, the operation of the solid-state imaging device (CMOS image sensor) 10 according to the present embodiment will be described with reference to the timing chart of FIG. 20 and the block diagram of FIG.

After the first reading from the unit pixel 111 in any row Hx to the column lines V0, V1,... Is stabilized, the ramp waveform RAMP based on the reference voltage is output from the output of the DAC 16. The ramp waveform RAMP based on the reference voltage is input as a stepped waveform as the reference voltage REF of the comparator 151. In each comparator 151, a comparison with the voltage of an arbitrary column line Vx is performed.
At this time, the counter latch 152 is in a down-count state and performs a reset count. When the reference voltage REF becomes equal to the voltage Vx, the output COMPOUTi of the comparator 151 is inverted, the down-count operation is stopped, and the count is held.
At this time, the initial value of the counter latch 152 is an arbitrary value of the AD conversion gradation, for example, 0. During the reset count period, the reset component ΔV of the unit pixel 111 is read.

Then, after the column lines V0, V1,... Are stabilized according to the amount of incident light, the ramp waveform RAMP is input as the reference voltage REF as a data count period, and compared with the voltages of arbitrary column lines V0, V1,. Is performed by the comparator 151.
In parallel with the input of the ramp waveform RAMP which is a staircase wave, the counter latch 152 counts up each. When the reference voltage REF is equal to Vx, the output COMPOUTi of the comparator 151 is inverted, and the count corresponding to the comparison period is held.
The counter value held in the counter latch 152 is scanned by the column scanning circuit 13 and input as a digital signal to the sense amplifier circuit 171 of the data output circuit 17 through the data transfer line 154, and sequentially detects and outputs the digital value. Is done.

  As described above, the pixel array unit 11 in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, the plurality of data transfer lines 154-0 to 164-n that transfer digital data, and the data transfer line 154 Connected to the connected data output circuits 17-0 to 17-n and the corresponding data transfer line 154, holds the digital value corresponding to the analog input level read through the column line of the pixel array unit 11, and converts the digital value to the data It has a plurality of counter latches 152-0 to 152-n for transferring to the transfer line 154 and a column scanning circuit 13 for selecting a plurality of holding circuits by a selection signal synchronized with a drive clock. The circuit 13 receives the master clock MCK supplied from the clock supply circuit 21 through a predetermined wiring, and latches 131-0 to 131-0 constituting the shift register 131. The data output circuits 17-0 to 17-n distribute the output data of the sense amplifier circuits 171-0 to 171-n according to the capture clock SACK whose phase is adjusted with respect to the master clock MCK. By taking in, the following effects can be obtained.

In other words, the position dependent component due to the data transfer distance can be removed from the skew component of the data that has hindered the high speed during the horizontal transfer of the data of the image pickup unit, and the image sensor can be further increased in speed. Can contribute to the increase in size or size.
In addition, since data and a clock are transferred on the same transfer line, it is possible to relatively easily absorb the influence of process variations between chips and between wafers, and the yield can be improved. In addition, since the capture margin for data synchronization can be expanded, the design is facilitated, and the design period and man-hours can be reduced.

In the above description, the drive clock distribution in the column scanning circuit 13 is equal to the tree structure from substantially the center of the latches 131-0 to 131-n arranged in parallel as shown in FIGS. In the above description, the method of distributing the signals to each other or the method of sequentially distributing the data from the input of the sense amplifier circuits 171-0 to 171-n from the farthest end side latch 131-0 has been described as an example, but the present invention is limited to this. It is not a thing.
For example, as shown in FIG. 21, the latches 131-0 to 131-n arranged in parallel are distributed from the substantially central portion to the farthest end side and the nearest end side, and the farthest end latch 131-0 and the nearest end are arranged. It is also possible to configure such that distribution is performed from both sides of the end-side latch 131-n toward the central portion.

  A solid-state imaging device having such an effect can be applied as an imaging device for a digital camera or a video camera.

  FIG. 22 is a diagram illustrating an example of a configuration of a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

  As shown in FIG. 22, the camera system 40 guides incident light to a pixel area of the imaging device 41 to which the solid-state imaging device 10 according to the present embodiment is applicable and forms a subject image. ) Optical system, for example, a lens 42 that forms incident light (image light) on the imaging surface, a drive circuit (DRV) 43 that drives the imaging device 41, and a signal processing circuit that processes the output signal of the imaging device 41 ( PRC) 44.

  The drive circuit 43 includes a timing generator (not shown) that generates various timing signals including a start pulse and a clock pulse that drive a circuit in the imaging device 41, and drives the imaging device 41 with a predetermined timing signal. .

The signal processing circuit 44 performs signal processing such as CDS (Correlated Double Sampling) on the output signal of the imaging device 41.
The image signal processed by the signal processing circuit 44 is recorded on a recording medium such as a memory. The image information recorded on the recording medium is hard copied by a printer or the like. Further, the image signal processed by the signal processing circuit 44 is displayed as a moving image on a monitor including a liquid crystal display or the like.

  As described above, a high-precision camera can be realized by mounting the above-described solid-state imaging device 10 as the imaging device 41 in an imaging apparatus such as a digital still camera.

  DESCRIPTION OF SYMBOLS 10 ... Solid-state image sensor, 11 ... Pixel array part, 12 ... Row scanning circuit, 13 ... Column scanning circuit, 131 ... Shift register, 131-0-131-n ... Latch , 14 timing control circuit, 15 ADC group, 151 comparator 152, 152C asynchronous up / down counter, 153 column parallel ADC block, 154, 154-0 154-n: Data transfer line, 16: DAC, 17, 17D, 17E ... Data output circuit, 171, 171-0, 171-n, 171C, 171D ... Sense amplifier (S / A) ) Circuit, 172.172-0 to 172-n, 172D, 172E... Data synchronization circuit, 173-0 to 173-n... First latch, 174-0 to 174-n. 175- 175-n ... first switch, 176-0-176-n ... second switch, 177-0-177-n ... take-in circuit, 178 ... data output circuit, 20 ... Output data processing circuit, 21... Clock supply circuit, 22, 22A, 27, 28... Phase adjustment unit, 23... Repeater, 24-0 to 24-n, 24C. 25, 25M, 25P ... pseudo clock transfer line, 26 ... sense amplifier circuit, 27 ... phase adjustment unit, 28 ... phase adjustment unit, 30, 30A-H ... data transfer system, 40 ... Camera system, 41 ... Imaging device, 42 ... Lens, 43 ... Drive circuit, 44 ... Signal processing circuit, LCLK1 ... Drive clock supply line, LCLK2 ... Drive clock Wiring, LMCK1 LMCK1A ··· master clock supply lines, LSACK, LSACKH ··· clock supply lines, LSLD1~LSLD4 ··· shield line, LSTRT ··· start clock supply line

Claims (8)

A plurality of transfer lines for transferring data;
Detecting the data transferred to the transfer line, and a plurality of data output section for Write-output takes the detected data in synchronization with a sampling clock,
A plurality of holding units arranged in parallel holding data corresponding to the input level and transferring the data to the corresponding transfer line in response to a selection signal;
A capture clock supply section for supplying the capture clock to the plurality of data output sections;
A clock supply unit for supplying at least a master clock; and
A scanning unit that generates the selection signal in synchronization with a driving clock based on the master clock and outputs the selection signal to the holding unit;
A pseudo transfer line wired in the same direction as the transfer line;
In response to the selection signal that is arranged corresponding to the parallel arrangement of the holding units and is generated in synchronization with the drive clock, pseudo data that has the same frequency as the data and is a repeating pattern of 1 and 0 is obtained. A plurality of pseudo data storage units that transfer to the corresponding pseudo transfer line,
The transfer line is
Wired in the parallel arrangement direction of the holding units, connected to the corresponding data output unit arranged in the direction,
The scanning unit is
A plurality of selection signal generators arranged corresponding to the parallel arrangement of the holding units, and outputting the selection signals to the corresponding holding units in synchronization with a supplied drive clock;
A clock supply line that propagates the master clock and supplies the master clock as a drive clock to the plurality of selection signal generation units,
The capture clock supply unit
Supplying the pseudo data to the plurality of data output units as the capture clock ;
The data output part
A capture unit that captures data in a complementary manner in synchronization with both the falling edge and the rising edge at the time of pseudo data level transition as the capture clock;
A data transfer circuit having a data synchronization circuit for re-fetching data fetched by the fetch unit with a clock based on the master clock . The scanning unit is
The master clock is propagated from the input side of the data output unit to the farthest end side by the clock supply line, and is located from the selection signal generation unit located at the farthest end to the nearest end from the input side of the data output unit. data transfer circuit according to claim 1, wherein supplying the drive clock in order toward the selection signal generating unit. The scanning unit is
A drive clock supply line that sequentially propagates the drive clock is wired in the same direction as the transfer line,
3. The data transfer circuit according to claim 2 , wherein a sum of a delay component of the drive clock and a delay component from the holding unit to an input of the data output unit is constant regardless of an arrangement position of the holding unit. The scanning unit is
A drive clock supply line that sequentially propagates the drive clock is wired in the same direction as the transfer line,
The capture clock supply unit
The data transfer circuit according to claim 2, wherein a clock propagated through the drive clock supply line is supplied to the plurality of data output units as the capture clock. The scanning unit is
A master clock supply line for propagating the master clock is formed so as to be parallel to the drive clock supply line, and is connected to the drive clock supply line on the farthest end side from the input side of the data output unit,
The data transfer circuit according to claim 4, wherein a shield line connected to a fixed potential is formed at least between the master clock supply line and the drive clock supply line. The capture clock supply unit has a phase adjustment function of the supply clock.
The data transfer circuit according to claim 1. An imaging unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A plurality of transfer lines for transferring data;
Detecting the data transferred to the transfer line, and a plurality of data output section for Write-output takes the detected data in synchronization with a sampling clock,
A plurality of holding units arranged in parallel holding data corresponding to the input level and transferring the data to the corresponding transfer line in response to a selection signal;
A capture clock supply section for supplying the capture clock to the plurality of data output sections;
A clock supply unit for supplying at least a master clock; and
A scanning unit that generates the selection signal in synchronization with a driving clock based on the master clock and outputs the selection signal to the holding unit;
A pseudo transfer line wired in the same direction as the transfer line;
In response to the selection signal that is arranged corresponding to the parallel arrangement of the holding units and is generated in synchronization with the drive clock, pseudo data that has the same frequency as the data and is a repeating pattern of 1 and 0 is obtained. A plurality of pseudo data storage units that transfer to the corresponding pseudo transfer line,
The transfer line is
Wired in the parallel arrangement direction of the holding units, connected to the corresponding data output unit arranged in the direction,
The scanning unit is
A plurality of selection signal generators arranged corresponding to the parallel arrangement of the holding units, and outputting the selection signals to the corresponding holding units in synchronization with a supplied drive clock;
A clock supply line that propagates the master clock and supplies the master clock as a drive clock to the plurality of selection signal generation units,
The capture clock supply unit
Has a phase adjustment function of the supply clock,
Supplying the pseudo data to the plurality of data output units as the capture clock ;
The data output part
A capture unit that captures data in a complementary manner in synchronization with both the falling edge and the rising edge at the time of pseudo data level transition as the capture clock;
A solid-state imaging device having a data synchronization circuit that takes in data taken in by the fetching unit again with a clock based on the master clock . A solid-state image sensor;
An optical system for forming a subject image on the solid-state image sensor;
A signal processing circuit for processing an output image signal of the solid-state imaging device,
The solid-state imaging device is
An imaging unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A plurality of transfer lines for transferring data;
Detecting the data transferred to the transfer line, and a plurality of data output section for Write-output takes the detected data in synchronization with a sampling clock,
A plurality of holding units arranged in parallel holding data corresponding to the input level and transferring the data to the corresponding transfer line in response to a selection signal;
A capture clock supply section for supplying the capture clock to the plurality of data output sections;
A clock supply unit for supplying at least a master clock; and
A scanning unit that generates the selection signal in synchronization with a driving clock based on the master clock and outputs the selection signal to the holding unit;
A pseudo transfer line wired in the same direction as the transfer line;
In response to the selection signal that is arranged corresponding to the parallel arrangement of the holding units and is generated in synchronization with the drive clock, pseudo data that has the same frequency as the data and is a repeating pattern of 1 and 0 is obtained. A plurality of pseudo data storage units that transfer to the corresponding pseudo transfer line,
The transfer line is
Wired in the parallel arrangement direction of the holding units, connected to the corresponding data output unit arranged in the direction,
The scanning unit is
A plurality of selection signal generators arranged corresponding to the parallel arrangement of the holding units, and outputting the selection signals to the corresponding holding units in synchronization with a supplied drive clock;
A clock supply line that propagates the master clock and supplies the master clock as a drive clock to the plurality of selection signal generation units,
The capture clock supply unit
Has a phase adjustment function of the supply clock,
Supplying the pseudo data to the plurality of data output units as the capture clock ;
The data output part
A capture unit that captures data in a complementary manner in synchronization with both the falling edge and the rising edge at the time of pseudo data level transition as the capture clock;
A camera system having a data synchronization circuit that re-captures data captured by the capture unit with a clock based on the master clock .

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