JP2011171889A - Solid-state imaging element and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element and an imaging apparatus which reduces the effect caused by wiring delay in a transfer bus, and which can attain improvement in the transfer rate. <P>SOLUTION: The imaging apparatus is provided with a plurality of latch units which are prepared for each pixel columns which constitute a pixel array unit, transform pixel values of the pixel to digital pixel data, and holds the pixel data; a plurality of driver units which are prepared for every latch units, and output signals, according to the pixel data held in the latch units to a transfer bus; a column scanning unit which controls the plurality of the driver units and outputs signals according to the pixel data held in the latch units to the transfer bus; a sense amplifier unit which amplifies the signal output to the transfer bus; and a data capture unit which captures the signals amplified by the sense amplifier unit to synchronize a predetermined clock. The shorter the transfer distance from the driver unit to the sense amplifier unit is among the plurality of the drivers, the lower the drive capacity of the signal to the transfer bus is set. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device represented by a CMOS image sensor and an imaging device including the same.

  In recent years, imaging devices that can capture and store images using a solid-state imaging device, such as digital still cameras and digital video cameras, have become widespread. A CCD image sensor is the most common solid-state imaging device used in such imaging devices. However, in recent years, the number of pixels in a solid-state imaging device has further increased, and therefore, a CMOS image sensor has attracted attention. ing.

  The CMOS image sensor has features such as high-speed reading, high sensitivity, and low power consumption compared to a CCD image sensor. In addition, the CMOS image sensor has an advantage that the number of peripheral ICs can be reduced because analog circuits and logic circuits using the CMOS process can be mixed in the same chip.

  The CMOS image sensor has an FD amplifier for each pixel, selects a pixel group in one row in the pixel array, and simultaneously reads out the output from the FD amplifier of each pixel constituting the pixel group in the column direction. The column parallel output type is the mainstream.

  Various signal output circuits for such a column parallel output type CMOS image sensor have been proposed. One of the most advanced forms is a CMOS image sensor of a type in which an analog-digital converter (hereinafter referred to as “ADC”) is provided for each pixel column and a pixel signal is extracted as digitized pixel data. (For example, refer to Patent Document 1).

  Here, the configuration of the data transfer system in the conventional column parallel output type CMOS image sensor will be described with reference to FIG.

  As shown in FIG. 12, the conventional column parallel output type CMOS image sensor includes a latch unit 110 and a driver unit 120 for each pixel column. The latch unit 110 holds pixel data after A / D conversion, and this pixel data is transferred from the latch unit 110 by the driver unit 120 selected by the column scanning unit 130 to have a plurality of horizontal transfer lines 141. It is output to the bus 140. The column scanning unit 130 includes a shift register, and outputs a pulse signal having a predetermined width (hereinafter referred to as “selection signal”) in units of columns. The driver unit 120 is selected by this selection signal.

  The sense amplifier unit 150 is connected to the transfer bus 140, amplifies the pixel data read from the latch unit 110 with an analog small amplitude, and outputs the amplified pixel data to the data capturing unit 160. The data capturing unit 160 plays a role of reliably latching the pixel data amplified by the sense amplifier unit 150 based on a predetermined latch timing signal (hereinafter referred to as “latch clock”).

  Since the CMOS image sensor 100 employs a column parallel reading method, scanning in the column direction (horizontal scanning) needs to be performed at high speed. However, since the latch unit 110 is arranged in a wide range corresponding to each pixel column, the transfer bus 140 becomes long. Therefore, in data transfer via the transfer bus 140, wiring delay occurs due to parasitic capacitance, parasitic resistance, and the like. The wiring delay becomes larger as the data is transferred from the latch unit 110 far from the sense amplifier unit 150.

  The data read from each latch unit 110 is performed by being latched at a predetermined data latch timing in the data capturing unit 160. However, if the wiring delay is too large, it becomes difficult to latch at the predetermined data latch timing. . In particular, as the transfer speed (clock frequency) increases, the influence of this wiring delay increases and becomes a problem.

  With the expansion of the single-lens reflex camera market, CMOS image sensors have not only increased the number of pixels and the speed, but also increased in size, and the influence of this wiring delay has become more remarkable.

  It is possible to improve the propagation delay by increasing the amplification factor (gain) of the sense amplifier unit 150. However, when data is transferred from the driver unit 120 having a short distance to the sense amplifier unit 150 (hereinafter referred to as “transfer distance”), there is a possibility that a circuit oscillation problem may occur. Therefore, the amplification factor of the sense amplifier unit 150 is limited by the phase margin of the sense amplifier unit 150 in the case of data transfer with a short transfer distance, and thus has a limit.

  Therefore, as a technique for solving such a problem, the following Patent Document 1 proposes a configuration of a data transfer system shown in FIG.

  In this data transfer system configuration, the delay circuit 180 delays a selection signal input to a shift register corresponding to the driver unit 120 having a short transfer distance among a plurality of shift registers constituting the column scanning unit 130. Thereby, the input timing of the selection signal to the driver unit 120 having a long transfer distance becomes earlier than the input timing of the selection signal to the driver unit 120 having a short transfer distance.

  With this configuration, the driver unit 120 with a longer transfer distance operates earlier, and the driver unit 120 with a shorter transfer distance operates slower. For this reason, the wiring delay is canceled out, and variations in propagation delay occurring in the transfer bus 140 are suppressed.

JP 2008-306695 A

  However, the configuration of the data transfer system described in Patent Document 1 does not solve the essence of propagation delay caused by the transfer bus. For this reason, if the transfer distance to the sense amplifier unit becomes longer as the number of pixels is increased and the size is increased, the variation in propagation delay may not be sufficiently suppressed. When transferring an isolated pattern, that is, the pattern of pixel data transferred to the transfer bus is set to a high level at a constant cycle such as 1 · 0 · 0 · 1 · 0 · 0 · 1 · 0. Similarly, when transferring pixel data to be transferred, there is a possibility that variation in propagation delay cannot be sufficiently suppressed.

It is an object of the present invention to provide a solid-state imaging device capable of reducing the influence of wiring delay in a transfer bus and increasing the transfer speed, and an imaging device including the same.

  Accordingly, in order to achieve the above object, the invention according to claim 1 is provided for each pixel array constituting the pixel array section and the pixel array section in which the pixels are arranged in a matrix in the solid-state imaging device. A plurality of latch units that convert the pixel value of the pixel into digital pixel data and hold the pixel data, and a signal corresponding to the pixel data that is provided for each latch unit and held in the latch unit, A plurality of driver units for outputting to the transfer bus; a column scanning unit for controlling the plurality of driver units to output a signal corresponding to the pixel data held in the latch unit to the transfer bus; and A sense amplifier unit that amplifies the output signal; and a data capturing unit that sequentially captures the signal amplified by the sense amplifier unit in synchronization with a predetermined clock. Higher transfer distance is short driver to the sense amplifier portion of the parts, and lower driving ability of the signal to the transfer bus.

  According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, each of the driver units includes a driving transistor whose output is connected to the transfer bus, Among the driver sections, the driver section with a shorter transfer distance to the sense amplifier section has a smaller transistor size for the driving transistor.

  According to a third aspect of the present invention, in the solid-state imaging device according to the first or second aspect, the sense amplifier unit includes switching means for switching the amplification factor to at least two stages, and the transfer distance is long. The amplification factor when amplifying the signal from the driver unit is larger than the amplification factor when a signal from the driver unit with a short transfer distance is amplified.

  According to a fourth aspect of the present invention, in the solid-state imaging device according to any one of the first to third aspects, the column scanning unit outputs a signal corresponding to the pixel data held in the latch unit. A delay circuit that delays a selection signal to be output from the driver unit to the transfer bus is provided for each latch unit, and the delay time is increased for the selection signal for the driver unit having a short transfer distance by the delay circuit.

  According to a fifth aspect of the present invention, in the solid-state imaging device according to any one of the first to fourth aspects, the column scanning unit can control the plurality of driver units in a plurality of scanning modes. In the plurality of scanning modes, a selection signal for outputting a signal corresponding to the pixel data held in the latch unit from the driver unit to the transfer bus is transmitted from a driver unit having a short transfer distance to a driver having a long transfer distance. And a second scanning mode in which the selection signal is sequentially output from a driver unit having a long transfer distance to a driver unit having a short transfer distance.

  The invention according to claim 6 is an imaging apparatus, further comprising a solid-state imaging device, wherein the solid-state imaging device includes a pixel array unit in which pixels are arranged in a matrix and each pixel column constituting the pixel array unit. A plurality of latch units that convert the pixel values of the pixels into digital pixel data and hold the pixel data, and are provided for each of the latch units according to the pixel data held in the latch unit A plurality of driver units for outputting a signal to a transfer bus; a column scanning unit for controlling the plurality of driver units to output a signal corresponding to pixel data held in the latch unit to the transfer bus; and A plurality of sense amplifiers that amplify signals output to the transfer bus; and a data capture unit that sequentially captures the signals amplified by the sense amplifiers in synchronization with a predetermined clock. Higher transfer distance is short driver to the sense amplifier portion of the driver was lower driving ability of the signal to the transfer bus.

  According to the present invention, it is possible to reduce the influence of wiring delay in the transfer bus and increase the transfer speed.

It is a figure which shows the structure of the imaging device which concerns on one Embodiment of this invention. It is a figure which shows the structure of the solid-state image sensor shown in FIG. It is a figure for demonstrating operation | movement of the solid-state image sensor shown in FIG. It is a figure which shows the structure of the transfer system of the solid-state image sensor shown in FIG. FIG. 4 is a diagram illustrating a configuration of a driver circuit illustrated in FIGS. 2 and 3. FIG. 4 is a diagram illustrating a configuration of a driver circuit illustrated in FIGS. 2 and 3. FIG. 4 is a diagram illustrating a configuration of a sense amplifier circuit illustrated in FIGS. 2 and 3. FIG. 4 is a diagram for explaining the operation of the sense amplifier circuit shown in FIGS. 2 and 3. FIG. 4 is a diagram for explaining the operation of the sense amplifier circuit shown in FIGS. 2 and 3. It is a figure which shows the structure of the other solid-state image sensor which concerns on one Embodiment of this invention. It is a figure which shows the structure of the other column scanning part which concerns on one Embodiment of this invention. It is a figure which shows the structure of the conventional solid-state image sensor. It is a figure which shows the structure of the conventional solid-state image sensor.

  Hereinafter, a configuration of a solid-state imaging device according to an embodiment of the present invention and an imaging device including the solid-state imaging device will be specifically described.

  The solid-state imaging device according to the present embodiment includes a pixel array unit, a plurality of latch units, a plurality of driver units, a column scanning unit, a transfer bus, a sense amplifier unit, a data capturing unit, and an output data processing unit. It has.

  Pixels are arranged in a matrix in the pixel array section. The latch unit is provided for each pixel column constituting the pixel array unit, converts the pixel value of each pixel constituting the pixel column into digital pixel data, and holds the pixel data.

  The driver unit is provided for each latch unit, and outputs a signal corresponding to the pixel data held in the latch unit to the transfer bus under the control of the column scanning unit.

  A sense amplifier unit is connected to the transfer bus, and a signal output from the driver unit to the transfer bus is amplified and output to the data capturing unit. The data capturing unit sequentially captures the signals amplified by the sense amplifier unit in synchronization with a predetermined clock and outputs the signals to the output data processing unit.

  Furthermore, in the solid-state imaging device according to the present embodiment, the driving capability of a signal to the transfer bus is lowered as the driver portion has a shorter transfer distance to the sense amplifier portion among the plurality of driver portions.

  With this configuration, the data propagation delay increases as the output from the driver unit has a shorter transfer distance to the sense amplifier unit. Therefore, the propagation delay from the driver unit having a short transfer distance to the sense amplifier unit is adjusted by the driver unit, and the difference in data propagation delay between the driver units due to the wiring load can be minimized.

  The drive capability of the driver unit can be adjusted, for example, by changing the transistor size of the driving transistor that constitutes the driver unit and whose output is connected to the transfer bus. In other words, the transistor for driving the driver section with a shorter transfer distance has a smaller transistor size and a larger on-resistance. By increasing the on-resistance of the driving transistor in this way, it is possible to increase the wiring resistance of the transfer bus in a pseudo manner, and to delay the transfer of data output from the sense amplifier unit. Thus, since it is only necessary to change the transistor size of the driving transistor, it is possible to suppress an increase in the cost of the solid-state imaging device.

  In addition, the sense amplifier unit has switching means for switching the amplification factor to at least two stages, and the amplification factor when the signal from the driver unit having a long transfer distance is amplified is determined by the signal from the driver unit having a short transfer distance. Is larger than the amplification factor when amplifying.

  With this configuration, even if the data propagation delay difference cannot be reduced sufficiently by merely adjusting the drive capability of the driver unit, the data propagation delay difference can be further reduced.

  The column scanning unit also includes a delay circuit for each latch unit that delays a selection signal for outputting a signal corresponding to the pixel data held in the latch unit from the driver unit to the transfer bus. In addition, the delay time is increased as the selection signal for the driver unit having a shorter transfer distance is provided by the delay circuit.

  With this configuration, even if the data propagation delay difference cannot be reduced sufficiently by merely adjusting the drive capability of the driver unit, the data propagation delay difference can be further reduced.

  In addition, the column scanning unit can control a plurality of driver units in a plurality of scanning modes. These scanning modes include a first scanning mode in which a selection signal is sequentially output from a driver section having a short transfer distance to a driver section having a long transfer distance, and a selection signal sequentially from a driver section having a long transfer distance to a driver section having a short transfer distance. Is included in the second scanning mode.

  With such a configuration, it is possible to read a signal according to the pixel data held in the latch unit from any direction, and for example, defective pixels can be processed efficiently. In the solid-state imaging device according to the present embodiment, the data propagation delay difference is reduced by adjusting the drive capability of the driver unit, adjusting the amplification factor of the sense amplifier unit, and a delay circuit that delays the selection signal. I am doing so. Therefore, even when the signal readout direction corresponding to the pixel data is changed, the data propagation delay difference can be reduced.

Hereinafter, a specific configuration of an imaging apparatus including the solid-state imaging device according to the present embodiment will be specifically described with reference to the drawings. The description will be given in the following order.
1. Configuration of imaging device 2. Configuration and operation of solid-state image sensor 1. First configuration for canceling wiring delay 4. Second configuration for canceling wiring delay Other embodiments

[1. Configuration of imaging equipment]
First, the configuration of the imaging device in the present embodiment will be described with reference to the drawings.

  As shown in FIG. 1, the imaging device 1 includes a solid-state imaging device 2, a signal processing circuit 3, a system controller 4, an input unit 5, and an optical block 6. The imaging device 1 is provided with a driver 7 for driving a mechanism in the optical block 6, a timing generator (TG) 8 for driving the solid-state imaging device 2, and the like.

  The optical block 6 includes a lens for condensing light from the subject onto the solid-state imaging device 2, a drive mechanism for moving the lens to perform focusing and zooming, a mechanical shutter, a diaphragm, and the like. The driver 7 controls the driving of the mechanism in the optical block 6 in accordance with a control signal from the system controller 4.

  The solid-state imaging device 2 is driven based on the timing signal output from the TG 8, converts incident light from the subject into an electrical signal, and outputs pixel data generated by digital conversion. The TG 8 outputs a timing signal under the control of the system controller 4.

  The signal processing circuit 3 performs various camera signal processing such as AF (Auto Focus), AE (Auto Exposure), defective pixel detection processing and correction processing, white balance adjustment, matrix processing, and the like on pixel data output from the solid-state imaging device 2. Execute.

  The system controller 4 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The CPU executes the programs stored in the ROM, thereby controlling the respective units of the imaging device 1 in an integrated manner and executing various calculations for the control. The input unit 5 includes operation keys, dials, levers, and the like that receive user operation inputs, and outputs a control signal corresponding to the operation inputs to the system controller 4.

  In this imaging device 1, the image data output from the signal processing circuit 3 is supplied to a graphic interface circuit (not shown) and converted into an image signal for display, whereby a camera-through image is displayed on a monitor (not shown). When the system controller 4 is instructed to record an image by a user input operation to the input unit 5 or the like, the image data from the signal processing circuit 3 is supplied to a CODEC (enCOder, DEcoder) and compressed and encoded. The processing is performed and recorded on the recording medium. When recording a still image, the signal processing circuit 3 supplies one frame of image data to the CODEC, and when recording a moving image, the processed image data is continuously supplied to the CODEC. .

[2. Configuration and operation of solid-state image sensor]
Next, the configuration and operation of the solid-state imaging device 2 will be specifically described with reference to FIGS. As the solid-state imaging device 2, a CMOS image sensor equipped with a column parallel ADC will be described as an example.

  As shown in FIG. 2, the solid-state imaging device 2 includes a pixel array unit 11, an ADC group 12, a digital-analog converter (hereinafter referred to as “DAC”) 13, a sense amplifier unit (S / A) 14, and data. A capturing unit 15 and an output data processing unit 16 are included.

  The pixel array unit 11 is configured by arranging pixels 11 a including photodiodes and in-pixel amplifiers in a matrix (matrix). The solid-state imaging device 2 controls a timing control unit 17 that generates an internal clock, a row scanning unit 18 that controls row scanning, and a column scanning as a control circuit for sequentially reading signals from the pixel array unit 11. A column scanning unit 19 is arranged. The column scanning unit 19 includes a shift register in which a plurality of flip-flops 60-1 to 60-n are connected in series (see FIG. 4).

  The ADC group 12 includes a plurality of analog-digital conversion devices (hereinafter referred to as “ADC”) including a comparator 30 and a counter latch 31. This ADC is arranged for each column line V0, V1,... And has an n-bit digital signal conversion function.

  The comparator 30 has a ramp waveform RAMP in which the reference voltage generated by the DAC 13 is changed stepwise, and the pixel line 11a through the column lines V0, V1,... For each row line H0, H1,. The obtained pixel signal is compared. This pixel signal is a signal corresponding to the pixel value of the pixel 11a, and is a signal having a voltage value corresponding to the photoelectric conversion amount in the pixel 11a.

  The counter latch 31 includes a counter unit 32, a latch unit 33, and a driver unit 34. The counter unit 32 includes n counter circuits 32 a, and count clocks CK <b> 1 to CKn are input from the timing control unit 17 to count the comparison time of the comparator 30. The count value counted by the counter unit 32 is held by a latch unit 33 having n latch circuits 33a. This count value is pixel data obtained by digitally converting the pixel signal output from the pixel 11a. The driver unit 34 includes n driver circuits 34a, and each driver circuit 34a reads out and amplifies a signal corresponding to pixel data from the corresponding latch circuit 33a. Note that reading of a signal corresponding to the pixel data from the latch circuit 33a is executed by selection signals HSEL1, HSEL2,..., Which are pulse signals of a predetermined width output from the column scanning unit 19.

  The output of each counter latch 31 is connected to two-phase transfer buses 20A and 20B each having n horizontal transfer lines 20a and 20b. Data read from the counter latch 31 to the transfer buses 20A and 20B is amplified by the sense amplifier unit 14 having n sense amplifier (S / A) circuits 35, and is synchronized with the capture clock CLK. It is taken in by. The pixel data captured by the data capturing unit 15 is output via the output data processing unit 16.

  Here, the operation of the solid-state imaging device 2 will be specifically described with reference to the timing chart of FIG. Since the operations for the column lines V0, V1,... Are the same, the operation for the column line V0 will be described here. Further, the pixel signal output from the pixel 11a to the column line V0 is a signal obtained by adding a signal component Vsig corresponding to the amount of incident light to the reset component ΔV after a reset component ΔV including noise of the pixel signal as a reference component. Is controlled by the row scanning unit 18 so that.

  As shown in FIG. 3, after the readout of the reset component ΔV of the pixel 11a to the column line V0 is stabilized (timing t0) in any row Hx, the reference voltage is changed with time from the DAC 13 to the comparator 30. The input of the stepped ramp waveform RAMP is started. At the same time, counting is started by the n counter circuits 32 a of the counter latch 31. Thereby, the comparison with the voltage of an arbitrary column line V0 is started by the comparator 30. At this time, the counter latch 31 is in the down-count state. Thereafter, when the ramp waveform RAMP and the voltage of the column line V0 become equal (timing t1), the output of the comparator 30 is inverted, and the count value corresponding to the comparison period is held in the n latch units 33 of the counter latch 31. .

  Next, in any row Hx, after the reading of the signal component Vsig of the pixel 11a to the column line V0 is stabilized (timing t2), the DAC 13 compares the comparator 30 with the reference voltage over time. Input of the ramp waveform RAMP is started. Further, counting is started by the n counter circuits 32 a of the counter latch 31. At this time, the counter latch 31 is in the up-count state. Thereafter, when the ramp waveform RAMP and the voltage of the column line V0 become equal (timing t3), the output of the comparator 30 is inverted, and the count value corresponding to the comparison period is held in the n latch units 33 of the counter latch 31. Is done.

  In this way, the count operation in the counter latch 31 is held at the same storage location (n latch units 33) as a down-count at the first read and as an up-count at the second read. Therefore, the count value corresponding to ΔV is automatically subtracted from the count value corresponding to Vsig + ΔV in the counter latch 31, and the count value held in the counter latch 31 corresponds to the signal component Vsig. It becomes.

  After the end of the AD conversion period, the column scanning unit 19 sequentially activates the selection signals HSEL1 to HSELn from the selection signals HSEL1 to HSELn. As a result, the n-bit digital signal held in the counter latch 31 provided corresponding to each pixel column is sequentially output to the sense amplifier unit 14 via the transfer buses 20A and 20B.

  The sense amplifier unit 14 amplifies the difference potential input through the two-phase transfer buses 20A and 20B and outputs the amplified difference potential to the data capturing unit 15. The data capturing unit 15 includes, for example, n flip-flop circuits 36, and latches the output from the sense amplifier unit 14 in synchronization with the supplied capturing clock CLK. The pixel data latched by the data capturing unit 15 is output to the output data processing unit 16 in synchronization with the clock CLK.

[3. First Configuration for Canceling Wiring Delay]
Next, in the solid-state imaging device 2 according to the present embodiment, a first configuration for canceling the wiring delay will be described with reference to FIGS.

  As shown in FIG. 4, the configuration of the data transfer system of the solid-state imaging device 2 is a driver unit having a short transfer distance among the plurality of flip-flops 60-1 to 60-n constituting the column scanning unit 19 by the delay circuit 50. The selection signal inputted to the flip-flop corresponding to 34 is delayed. Thereby, the input timing of the selection signal to the driver unit 34 with a long transfer distance is earlier than the input timing of the selection signal to the driver unit 34 with a short transfer distance.

  With this configuration, the driver unit 34 with a longer transfer distance operates earlier, and the driver unit 34 with a shorter transfer distance operates slower. Therefore, the wiring delay is canceled out, and the variation in propagation delay occurring in the transfer buses 20A and 20B can be reduced. In FIG. 4, reference numeral 51 denotes a delay circuit, and the amount of delay can be changed by control from the column scanning unit 19.

  Further, in the solid-state image pickup device 2, the driver circuit 34a is configured as follows, and this makes it possible to further reduce the variation in propagation delay that occurs in the transfer buses 20A and 20B.

  As shown in FIG. 5, the driver circuit 34a includes cascode-connected NMOS transistors Tr1 and Tr2, and cascode-connected NMOS transistors Tr3 and Tr4.

  The drain of the NMOS transistor Tr1 is connected to the horizontal transfer line 20a, and the source thereof is connected to the drain of the NMOS transistor Tr2. The drain of the NMOS transistor Tr3 is connected to the horizontal transfer line 20b, and the source thereof is connected to the drain of the NMOS transistor Tr4. The sources of the NMOS transistors Tr2 and Tr4 are connected to the ground.

  The output of the latch circuit 33a is connected to the gate of the NMOS transistor Tr2, and the output of the latch circuit 33a is inverted and input to the gate of the NMOS transistor Tr4 via the inverter circuit INV. The selection signal HSELx (1 ≦ x ≦ n) is connected to the gates of the NMOS transistors Tr1 and Tr3, and the image for one bit held in the latch circuit 33a is set by setting the selection signal HSELx to the high level. A differential signal corresponding to the data is output to the horizontal transfer lines 20a and 20b. The signal output from the driver circuit 34a to the horizontal transfer line 20a and the signal output from the driver circuit 34a to the horizontal transfer line 20b are signals having opposite polarities, and a differential signal is constituted by these signals. The

  In the driver unit 34 having n driver circuits 34a configured as described above, the driving capability of signals to the transfer buses 20A and 20B is lowered as the driver unit 34 has a shorter transfer distance to the sense amplifier unit 14.

  Here, as shown in FIG. 6, the driver circuit of the driver unit 34 having a long transfer distance is a driver circuit 34a-1, the driver circuit of the driver unit 34 having an intermediate transfer distance is a driver circuit 34a-m, and the transfer distance is The driver circuit of the long driver unit 34 is referred to as driver circuits 34a-n.

  At this time, the drive capability of the driver circuit 34a is reduced in the order of the driver circuit 34a-1, the driver circuit 34a-m, and the driver circuit 34a-n. That is, the drive capability of the driver circuit 34a-m is made lower than the drive capability of the driver circuit 34a-1, and the drive capability of the driver circuit 34a-n is made lower than the drive capability of the driver circuit 34a-m. Note that the load 80 in FIG. 6 is a pseudo-representation of the wiring resistance and the wiring capacitance of the horizontal transfer lines 20a and 20b (transfer buses 20A and 20B) as a wiring load.

  With this configuration, the output delay from the driver unit 34 having a shorter transfer distance to the sense amplifier unit 14 increases the propagation delay of the image data. Therefore, the propagation delay from the driver unit 34 to the sense amplifier unit 14 with a short transfer distance is adjusted by the driver unit, and the data propagation delay difference due to the wiring load of the transfer buses 20A and 20B can be suppressed.

  Note that the change in the driving capability of the driver circuit 34a may be sequentially reduced one by one from the driver circuit 34a-1 to the driver circuit 34a-n, but may be reduced in units of a plurality. The accuracy can be improved by reducing the drive capability one by one, and the design cost can be reduced by reducing the drive capability by a plurality of units.

  The drive capability of the driver unit 34 can be adjusted, for example, by changing the transistor size of the driving NMOS transistors Tr1 and Tr3 (see FIG. 5) connected to the transfer buses 20A and 20B. That is, the NMOS transistors Tr1 and Tr3 of the driver unit 34 having a shorter transfer distance have a smaller transistor size and a larger on-resistance.

  By increasing the on-resistances of the NMOS transistors Tr1 and Tr3 in this way, the wiring resistance of the transfer buses 20A and 20B is increased in a pseudo manner, and the propagation delay of the pixel data output from the sense amplifier unit 14 is increased. Can do. As described above, since the drive capability of the driver section 34 can be changed only by changing the transistor size of the NMOS transistors Tr1 and Tr3, the manufacturing cost and the design cost can be suppressed, and thus the increase in the cost of the solid-state imaging device is suppressed. can do.

[4. Second Configuration for Canceling Wiring Delay]
As described above, in the solid-state imaging device 2, the data propagation delay is adjusted by changing the drive capability of the driver unit 34 to reduce the influence of the wiring delay in the transfer buses 20A and 20B. By configuring the amplifier unit 14 as follows, the influence of wiring delay is further reduced.

[4.1. Configuration of Sense Amplifier 14]
First, the configuration of the sense amplifier unit 14 according to the present embodiment will be specifically described with reference to the drawings. The sense amplifier unit 14 has n sense amplifier circuits 35, and each sense amplifier circuit 35 is configured as shown in FIG.

  As shown in FIG. 7, the sense amplifier circuit 35 includes current supply circuits 40 and 40 ′, source grounded amplifiers 41 and 41 ′, a reference voltage generation circuit 42, and a differential amplifier 43.

  The current supply circuits 40 and 40 'supply current to the driver circuit 34a that outputs a signal corresponding to the data held in the latch circuit 33a via the transfer buses 20A and 20B. As a result, a voltage corresponding to the data held in the latch circuit 33a is input to the input of the common source amplifiers 41 and 41 'via the driver circuit 34a and the transfer buses 20A and 20B.

  The common-source amplifiers 41 and 41 'compare the input voltage with the reference voltage VREF generated by the reference voltage generation circuit 42, and output output voltages OUT1 and OUT2 corresponding to the comparison result. The differential amplifier 43 receives the output voltages OUT1 and OUT2 of the common source amplifiers 41 and 41 'and outputs a voltage corresponding to the output voltages OUT1 and OUT2. The output of the differential amplifier 43 becomes the output voltage SAOUT of the sense amplifier circuit 35.

  The current supply circuit 40 is a circuit that supplies current to the driver circuit 34a via the horizontal transfer line 20a of the transfer bus 20A. The current supply circuit 40 is provided with a plurality of current supply units 40a, 40b, and 40c, and current can be supplied from at least one of these current supply units to the transfer bus 20A. The current supply units 40a, 40b, and 40c are controlled to supply and stop current based on control signals Ga, Gb, and Gc output from the column scanning unit 19.

  The current supply units 40a, 40b, and 40c supply current to the horizontal transfer line 20a by the driving transistors Tr11, Tr21, and Tr31. Since the configurations of the current supply units 40b and 40c are the same as the configuration of the current supply unit 40a, the configuration of the current supply unit 40a will be specifically described below.

  The current supply unit 40a includes transistors Tr12 to Tr14 and an inverter circuit INV2 in addition to the driving transistor Tr11, and controls the transistor Tr11 based on the control signal Ga output from the column scanning unit 19. The transistors Tr13 and Tr14 are connected to the output voltage OUT1 of the common source amplifier 41, and the transistor Tr11 is also used as a feedback transistor. That is, the output voltage OUT1 of the common-source amplifier 41 changes based on the potential of the horizontal transfer line 20a that changes according to the current supply from the transistor Tr11. The transistor Tr11 changes according to the output voltage OUT1 of the common-source amplifier 41. The current value supplied to the horizontal transfer line 20a changes.

  The specific configuration of the current supply unit 40a is as follows. That is, as shown in FIG. 7, the source of the transistor Tr11 is connected to the power supply of the voltage VDD, and the drain is connected to the horizontal transfer line 20a. The source of the transistor Tr12 is connected to the power supply of the voltage VDD, and the drain is connected to the gate of the transistor Tr11. The source of the transistor Tr13 is connected to the gate of the transistor Tr11 and the drain of the transistor Tr14, and the drain is connected to the source of the transistor Tr14. Then, the control signal Ga is input to the gates of the transistors Tr12 and Tr13, and the control signal Ga 'is input to the gate of the transistor Tr14 to control the on / off of the transistor Tr11. Both the drain of the transistor Tr13 and the source of the transistor Tr14 are connected to the output node of the common-source amplifier 41, and the transistor Tr11 has a feedback function. The transistors Tr11, Tr12, and Tr14 are PMOS transistors, and the transistor Tr13 is an NMOS transistor. As shown in FIG. 7, the configuration of the current supply circuit 40 ′ is the same as the configuration of the current supply circuit 40, and thus the description thereof is omitted here.

  The common source amplifier 41 includes transistors Tr41 to Tr44. The common source amplifier 41 compares the output voltage of the current supply circuit 40 input to each of the transistors Tr42 and Tr44 and the reference voltage VREF generated by the reference voltage generation circuit 42, and outputs an output voltage OUT1 corresponding to the comparison result. To do. The PMOS transistor Tr41 and the NMOS transistor Tr42 are cascode-connected, and are connected between the power supply of the voltage VDD and the ground. Similarly, the PMOS transistor Tr43 and the NMOS transistor Tr44 are cascode-connected, and are connected between the power supply of the voltage VDD and the ground. The gate of the PMOS transistor Tr43 is connected to the gate and source of the PMOS transistor Tr41, thereby forming a current mirror circuit. Since the configuration of the common source amplifier 41 ′ is the same as that of the common source amplifier 41, the description thereof is omitted here.

  The reference voltage generation circuit 42 includes a current source IA connected in series and a diode-connected transistor Tr60 between the power supply of the voltage VDD and the ground, and generates a reference voltage VREF.

  The differential amplifier 43 includes transistors Tr51 to Tr54. The output voltages OUT1 and OUT2 of the common source amplifiers 41 and 41 ′ are input to the gates of the transistors Tr53 and Tr51, and the output voltages OUT1 and OUT2 are output from the drain of the transistor Tr53. The corresponding voltage is output. Note that the PMOS transistor Tr51 and the NMOS transistor Tr52 are cascode-connected and connected between the power supply of the voltage VDD and the ground. Similarly, the PMOS transistor Tr53 and the NMOS transistor Tr54 are cascode-connected and connected between the power supply of the power supply VDD and the ground. The gate of the NMOS transistor Tr52 is connected to the gate and source of the NMOS transistor Tr52 to form a current mirror circuit.

  Diode-connected NMOS transistors Tr35 and Tr35 'are connected to the horizontal transfer lines 20a and 20b of the transfer buses 20A and 20B. On the other hand, according to the data held in the latch circuit 33a, the driver circuit 34a has one of the two horizontal transfer lines 20a and 20b connected to the ground through the transistor, and the other is not connected and is opened. Become. When the driver circuit 34a opens the horizontal transfer line 20a without being connected to the ground via a transistor, a current is supplied from the current supply circuit 40 to the NMOS transistor Tr35, and the NMOS transistor Tr35 functions as a diode. Therefore, a voltage is generated between the source and drain of the NMOS transistor Tr35, the horizontal transfer line 20a becomes a predetermined voltage, and the output voltage OUT1 of the common source amplifier 41 becomes a high potential. On the other hand, when the horizontal transfer line 20b is opened without being connected to the ground by the driver circuit 34a, the NMOS transistor Tr35 ′ functions as a diode for the same reason, and the horizontal transfer line 20b becomes a predetermined voltage. The output voltage OUT2 of the common source amplifier 41 ′ becomes a high potential.

  As described above, in the solid-state imaging device 2 according to the present embodiment, each current supply circuit 40, 40 'has a plurality of current supply units. The column scanning unit 19 controls these current supply units, thereby switching the amplification factor of the sense amplifier circuit 35 to at least two stages, thereby further reducing the influence of wiring delay.

[4.2. Operation of Sense Amplifier 14]
Hereinafter, switching of the amplification factor of each sense amplifier circuit 35 constituting the sense amplifier unit 14 will be specifically described with reference to FIG.

  The plurality of current supply units 40a to 40c and 40a ′ to 40c ′ provided in the current supply circuits 40 and 40 ′ have the same current supply capability, and are controlled by the column scanning unit 19 as shown in FIG. Is done.

  When the column scanning unit 19 sequentially selects the driver unit 34 for outputting a signal from the driver unit 34 having a long transfer distance to the driver unit 34 having a short transfer distance, the column scanning unit 19 controls the current supply circuits 40 and 40 'as follows. Then, the current supply amounts of the current supply circuits 40 and 40 ′ are switched in three stages. Here, the driver unit 34 to which the selection signals HSEL1 to HSEL (n / 3-1) are input becomes a driver unit 34 having a long transfer distance (hereinafter referred to as “far-end driver unit 34”). In addition, the driver unit 34 to which the selection signals HSEL (n / 3) to HSEL (2n / 3-1) are input has a driver unit 34 having an intermediate transfer distance (hereinafter referred to as “middle end driver unit 34”). It becomes. Further, the driver unit 34 to which the selection signals HSEL (2n / 3) to HSELn are input becomes a driver unit 34 having a short transfer distance (hereinafter referred to as “near-end driver unit 34”). Here, for convenience, n is a multiple of 3.

  In this case, when the column scanning unit 19 selects the near-end driver unit 34 as the driver unit 34 that outputs a signal, the column scanning unit 19 supplies current from the current supply units 40a and 40a 'by the control signal Ga. At this time, the current value of the current supplied from the current supply circuits 40, 40 ′ to the near-end driver unit 34 via the transfer buses 20A, 20B is constant according to the current supply capability of the current supply units 40a, 40a ′. Can be kept within range.

  Further, when the column scanning unit 19 selects the middle driver unit 34 as the driver unit 34 that outputs a signal, the column scanning unit 19 supplies current from the current supply units 40a, 40b, 40a ′, and 40b ′ by the control signals Ga and Gb. Let it be done. Since the wiring resistances of the transfer buses 20A and 20B are larger than in the case of the near-end driver unit 34, if only current is supplied from the current supply units 40a and 40a ′, the current supplied to the middle-end driver unit 34 Cannot be maintained within a certain range. However, since current is also supplied from the current supply units 40b and 40b ', the current value of the current supplied to the middle driver unit 34 can be maintained within a certain range.

  Further, when the column scanning unit 19 selects the far-end driver unit 34 as the driver unit 34 that outputs a signal, the current supply units 40a to 40c and 40a 'to 40c' receive currents from the control signals Ga, Gb, and Gc. Let the supply go. Compared with the case of the middle-end driver unit 34, the wiring resistance of the transfer buses 20A and 20B is increased. Therefore, if only current supply from the current supply units 40a, 40b, 40a ′, and 40b ′ is provided, the far-end driver unit 34 is provided. The current value of the current supplied to can not be maintained within a certain range. However, since current is also supplied from the current supply units 40c and 40c ', the current value of the current supplied to the far-end driver unit 34 can be maintained within a certain range.

  Thus, the current value of the current supplied from the sense amplifier unit 14 to the far-end driver unit 34 from the near-end driver unit 34 via the transfer buses 20A and 20B can be kept within a certain range. The difference in data propagation delay between the units 34 can be suppressed.

  In the example illustrated in FIG. 8, the current supply units 40a to 40c and 40a ′ to 40c ′ have been described as having the same current supply capability. However, the current supply units 40a to 40c and 40a ′ to 40c ′ have different currents. It can also be a supply capacity.

  The current supply capability of the current supply unit 40c is higher than the current supply capability of the current supply units 40a and 40b, and the current supply capability of the current supply unit 40b is higher than the current supply capability of the current supply unit 40a. For example, the current supply capability of the current supply unit 40b is set to twice the current supply capability of the current supply unit 40a, and the current supply capability of the current supply unit 40c is set to three times the current supply capability of the current supply unit 40a.

  In this case, when the column scanning unit 19 selects the near-end driver unit 34 as the driver unit 34 that outputs a signal, the column scanning unit 19 supplies current from the current supply units 40a and 40a 'by the control signal Ga. At this time, the current value of the current supplied from the current supply circuits 40, 40 ′ to the near-end driver unit 34 via the transfer buses 20A, 20B is constant according to the current supply capability of the current supply units 40a, 40a ′. Can be kept within range.

  Further, when the middle scanning unit 34 is selected as the driver unit 34 for outputting a signal, the column scanning unit 19 supplies current from the current supply units 40b and 40b 'by the control signal Gb. Compared with the case of the near-end driver unit 34, the wiring resistance of the transfer buses 20A and 20B is increased, so that the current supply unit 40b and 40b 'supplies a current twice that of the current supply units 40a and 40a'. As a result, the current value of the current supplied to the middle-end driver unit 34 can be maintained within a certain range.

  When the column scanning unit 19 selects the far-end driver unit 34 as the driver unit 34 that outputs a signal, the column scanning unit 19 supplies current from the current supply units 40c and 40c 'by the control signal Gc. Compared to the case of the middle-end driver unit 34, the wiring resistance of the transfer buses 20A and 20B is increased, so that the current supply units 40c and 40c 'supply a current three times that of the current supply units 40a and 40a'. Thereby, the current value of the current supplied to the far-end driver unit 34 can be maintained within a certain range.

  The current supply capability of the current supply units 40a to 40c and 40a 'to 40c' can be changed according to the transistor sizes of the driving transistors Tr11, Tr21, and Tr31. For example, when the current supply capability is decreased in the order of the current supply units 40a, 40b, and 40c, the transistor size of the transistor Tr31 is larger than the transistor size of the transistor Tr21, and the transistor size of the transistor Tr21 is larger than the transistor size of the transistor Tr11. It is also bigger.

  For example, when the column scanning unit 19 selects the far-end driver unit 34 as the driver unit 34 that outputs a signal, the column scanning unit 19 activates the selection signals HSEL1 to HSEL (n / 3-1) (High level). Only the control signal Gc can be made active (High level). By doing so, current consumption can be suppressed. In addition, the column scanning unit 19 can activate the necessary control signals Ga, Gb, and Gc only when activating any selection signal HSEL1 to HSELn. By doing in this way, current consumption can be further suppressed.

  In the above description, the column scanning unit 19 controls the control signals Ga, Gb, and Gc corresponding to the selection signals HSEL1 to HSELn. However, the control signal Ga, Gb, and Gc is controlled by detecting the transfer distance. You can also In the above description, each of the current supply circuits 40 and 40 ′ is provided with three current supply units. However, it can be arbitrarily increased or decreased in consideration of cost and accuracy.

  As described above, in the solid-state imaging device 2 according to the present embodiment, each current supply circuit 40, 40 ′ has a plurality of current supply units, and the column scanning unit 19 controls these current supply units. Thus, the influence of the wiring delay is reduced by switching the amplification factor of the sense amplifier circuit 35. For this reason, the size in the vertical direction can be suppressed, and an isolated pattern can be transferred regardless of the transfer distance. In addition, since the current supply unit is switched according to the transfer distance, it is easy to obtain a phase margin of the circuit, and the circuit design is easy.

[5. Other Embodiments]
In the solid-state imaging device 2 described above, the delay circuit 50 selects a shift register corresponding to the driver unit 34 having a short transfer distance from among the plurality of flip-flops 60-1 to 60-n constituting the column scanning unit 19. Although the signal HSEL is delayed, as shown in FIG. 10, the outputs from the flip-flops 60-1 to 60-n are connected to the driver unit 34 via the delay circuits 53-1 to 53-n. Also good. In this case as well, the selection signal HSELx corresponding to the driver unit 34 having a short transfer distance is delayed.

  That is, in the column scanning unit 19, for each latch unit 33, a delay circuit that delays the selection signals HSEL1 to HSELn for outputting a signal corresponding to the pixel data held in the latch unit 33 from the driver unit 34 to the transfer buses 20A and 20B. 53-1 to 53-n are provided. Then, the delay time is increased by the selection circuit HSELx for the driver unit having a short transfer distance by the delay circuit. With this configuration, the driver unit 34 with a longer transfer distance operates earlier, and the driver unit 34 with a shorter transfer distance operates slower. Therefore, the wiring delay is canceled out, and the variation in propagation delay occurring in the transfer buses 20A and 20B can be reduced.

  The delay circuits 53-1 to 53-n can improve versatility by using a variable delay circuit that can adjust a delay amount by controlling the column scanning unit 19 or the like. In FIG. 11, reference numeral 52 denotes a delay circuit, and the delay amount can be changed by control from the column scanning unit 19.

  Further, the solid-state imaging device 2 can control the plurality of driver units 34 in a plurality of scanning modes. For example, by configuring the column scanning unit 19 'as shown in FIG. 11, the plurality of driver units 34 can be controlled in the first scanning mode and the second scanning mode. In the first scanning mode, the selection signal HSELx is sequentially output from the driver unit having a short transfer distance to the driver unit having a long transfer distance. In the second scanning mode, the selection signal HSELx is sequentially output from the driver unit 34 having a long transfer distance to the driver unit 34 having a short transfer distance.

  In FIG. 11, the column scanning unit 19 ′ includes a shift register including a plurality of flip-flops 61-1 to 61-n in addition to a shift register including a plurality of flip-flops 60-1 to 60-n. It has a register. Of these shift registers, switches SW1 to SWn for determining which one of the shift registers to use as the selection signals HSEL1 to HSELn are provided. The column scanning unit 19 switches between the first scanning mode and the second scanning mode by controlling the switches SW1 to SWn. The switches SW1 to SWn are switched based on the value of the internal register. The value of the internal register can be changed by an external control signal.

  Although some of the embodiments of the present invention have been described in detail with reference to the drawings, these are exemplifications, and the present invention is implemented in other forms with various modifications and improvements based on the knowledge of those skilled in the art. Is possible.

DESCRIPTION OF SYMBOLS 1 Imaging device 2 Solid-state image sensor 3 Signal processing circuit 11 Pixel array part 12 ADC group 14 Sense amplifier part 15 Data acquisition part 16 Output data processing part 18 Row scanning part 19 Column scanning part 20a, 20b Horizontal transfer line 20A, 20B Transfer bus 30 comparator 31 counter latch 32 counter unit 32a counter circuit 33 latch unit 33a latch circuit 34 driver unit 34a driver circuit 35 sense amplifier circuits 40 and 40 'current supply circuits 40a to 40c, 40a' to 40c 'current supply units 50 to 52 , 53-1 to 53-n delay circuits 60-1 to 60-n, 61-1 to 61-n flip-flops

Claims (6)

A pixel array unit in which pixels are arranged in a matrix;
A plurality of latch units that are provided for each pixel column constituting the pixel array unit, convert pixel values of the pixels into digital pixel data, and hold the pixel data;
A plurality of driver units that are provided for each of the latch units and that output signals corresponding to the pixel data held in the latch units to a transfer bus;
A column scanning unit that controls the plurality of driver units to output a signal corresponding to the pixel data held in the latch unit to a transfer bus;
A sense amplifier for amplifying the signal output to the transfer bus;
A data capturing unit that sequentially captures the signal amplified by the sense amplifier unit in synchronization with a predetermined clock; and
A solid-state imaging device in which a driver unit having a shorter transfer distance to the sense amplifier unit among the plurality of driver units has a lower drive capability of a signal to the transfer bus. Each of the driver units has a driving transistor whose output is connected to the transfer bus,
2. The solid-state imaging device according to claim 1, wherein a driver unit having a shorter transfer distance to the sense amplifier unit among the plurality of driver units has a smaller transistor size of the driving transistor. The sense amplifier unit has switching means for switching the amplification factor in at least two stages, and the amplification factor when the signal from the driver unit with a long transfer distance is amplified is the signal from the driver unit with a short transfer distance. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is larger than an amplification factor at the time of amplification. The column scanning unit includes, for each latch unit, a delay circuit that delays a selection signal for outputting a signal corresponding to the pixel data held in the latch unit from the driver unit to the transfer bus. The solid-state imaging device according to claim 1, wherein a delay time is increased for a selection signal for a driver unit having a short transfer distance by a circuit. The column scanning unit can control the plurality of driver units in a plurality of scanning modes,
In the plurality of scanning modes, a selection signal for outputting a signal corresponding to the pixel data held in the latch unit from the driver unit to the transfer bus is transmitted from a driver unit having a short transfer distance to a driver unit having a long transfer distance. 5. A first scanning mode for sequentially outputting the first and second scanning modes, and a second scanning mode for sequentially outputting the selection signal from a driver unit having a long transfer distance to a driver unit having a short transfer distance. Solid-state image sensor. Equipped with a solid-state image sensor,
The solid-state imaging device is
A pixel array unit in which pixels are arranged in a matrix;
A plurality of latch units that are provided for each pixel column constituting the pixel array unit, convert pixel values of the pixels into digital pixel data, and hold the pixel data;
A plurality of driver units that are provided for each of the latch units and that output signals corresponding to the pixel data held in the latch units to a transfer bus;
A column scanning unit that controls the plurality of driver units to output a signal corresponding to the pixel data held in the latch unit to a transfer bus;
A sense amplifier for amplifying the signal output to the transfer bus;
A data capturing unit that sequentially captures the signal amplified by the sense amplifier unit in synchronization with a predetermined clock; and
An imaging device in which a driver unit having a shorter transfer distance to the sense amplifier unit among the plurality of driver units has a lower drive capability of a signal to the transfer bus.

Images