KR101452496B1 - Data transfer circuit, solid-state imaging device and camera system - Google Patents

Abstract

A data transfer circuit including a plurality of data transfer lines, a plurality of data output units, a plurality of data holding units, a data capture clock supply unit, a data capture clock supply unit, a clock supply unit, and a column scan unit.

A solid-state imaging device, a pixel array unit, a row scanning circuit, a column scanning circuit

Description

TECHNICAL FIELD [0001] The present invention relates to a data transfer circuit, a solid-state image pickup device,

Cross reference of related application

The present invention includes technical contents relating to Japanese Patent Application JP 2007-125741 and JP 2007-256856 submitted to the Japanese Patent Office on May 10, 2007 and September 28, 2007, the entire contents of which are incorporated herein by reference .

The present invention relates to a data transfer circuit, a solid-state image pickup device represented by a CMOS image sensor, and a camera system.

2. Description of the Related Art In recent years, a CMOS image sensor has attracted attention as a solid-state imaging device used as an image sensor instead of a CCD.

This is because an exclusive process is required for manufacturing the CCD pixel and a plurality of power source voltages are required for the operation of the CCD pixel. In addition, in the case of a CCD, it is necessary to operate a chip by combining a plurality of chips or peripheral chips. Therefore, a CMOS image sensor is used as a sensor for solving each of various problems raised in a system based on CCD pixels, such as a problem of complicating a system.

The CMOS image sensor can be manufactured by applying the same manufacturing process as a general CMOS type integrated circuit. Further, the CMOS image sensor can be driven by using a single power source. In addition, an analog circuit or a logic circuit using a CMOS process can be mixed in the same chip as the CMOS image sensor. Therefore, the CMOS image sensor has a plurality of great advantages, which can reduce the number of peripheral ICs.

The data output circuit of the CCD is a one-channel data output circuit using an FD amplifier having a floating diffusion (FD) layer. On the other hand, in the case of a CMOS image sensor, each pixel generally has an FD amplifier. The output selects any one row of the pixel array and simultaneously reads the pieces of information from the pixels of the selected row in the row direction to generate the output of the CMOS image sensor. Thus, the output of the CMOS image sensor is generally an output that is parallel to the pixel column of the pixel array.

This is because it is difficult to obtain a sufficient driving capability in the FD amplifier disposed in the pixel. Therefore, it is necessary to lower the data rate, and parallel processing is advantageous.

A variety of data output circuits of a CMOS image sensor having an output in parallel to a pixel row of the pixel array have been proposed. According to one of the most advanced forms of the data output circuit, each column is provided with an analog-to-digital converter and outputs a pixel signal as a digital signal. In the following description, the analog-digital conversion device is referred to as an ADC (Analog Digital Converter).

A CMOS image sensor equipped with such an on-row ADC for every pixel column (ADC) is disclosed in, for example, "An Integrated 800x600 CMOS Image System," ISSCC Digest of Technical Papers, pp. 304-305, Feb., 1999) and Japanese Patent Laid-Open No. 2005-323331.

1 is a block diagram showing a configuration example of a column-parallel ADC-mounted solid-state image pickup device 1 (CMOS image sensor).

The solid-state image pickup device 1 includes a pixel array section 2 as an image pickup section, a row scanning circuit 3, a column scanning circuit 4, a timing control circuit 5, an ADC group 6, And a data output circuit 9 including a device 7, a counter 8, and a sense amplifier circuit S / A. Hereinafter, the digital-analog converter 7 is abbreviated as a DAC (Digital-Analog Converter).

The pixel array unit 2 is constituted by unit pixels 2-1 each including a photodiode and an intra-pixel amplifier arranged in a matrix. The timing control circuit 5 is a circuit for generating an internal clock, and the row scanning circuit 3 is a circuit for controlling a row address and a row scanning. The column scanning circuit 4 is a circuit for generating column addresses and controlling column scanning. In the solid-state image pickup device 1, the row scanning circuit 3, the column scanning circuit 4 and the timing control circuit 5 are employed as a control circuit for reading signals from the pixel array unit 2. [

The ADC group 6 has a function of converting an analog signal into n-bit type digital data, and a plurality of column lines V0, V1, ..., And an ADC block 6-3. Specifically, in the ADC group 6, pixel heating lines V0, V1, ..., The same plurality of comparators 6-1 connected to one of the comparators 6-1 and 6-2 and the same plurality of memory units 6-2 each associated with one of the comparators 6-1 are provided. Each comparator 6-1 outputs a ramp waveform reference voltage RAMP generated by the DAC 7 as a signal having a step waveform to a row line H0, H1, ..., And the pixel column lines V0, V1 ... With the analog signal generated by the unit pixel 2-1 connected to the comparator 6-1. Each memory unit 6-2 is used to store the contents of the counter that performs the counting operation to measure the length of the comparison time performed by the comparator 6-1. In the above-mentioned on-row ADC, a specific one of the comparators 6-1 and a memory 6-2 connected to a specific comparator are provided.

The output of the memory device 6-2 is connected to a horizontal transmission line 6-4 of 2n-bit width, that is, a 2n horizontal data transmission line. Further, the horizontal transmission line 6-4 is connected to the output circuit via a data output circuit 9 including 2n-sense amplifiers for 2n bits, respectively.

Here, the operation of the solid-state image sensor (CMOS image sensor) 1 will be described with reference to the timing chart of Fig. 2 and the block diagram of Fig.

Data is read out from the unit pixel 2-1 of an arbitrary row Hx, and the pixel column lines V0, V1 ... The DAC 7 inputs to the comparator 6-1 the ramp waveform PAMP of the stepped shape in which the reference voltage is time-varied by the DAC 7. The comparator 6-1 compares the ramp waveform reference voltage RAMP with the voltage of the pixel heating line Vx, respectively.

The first count is made in the counter 8 while the DAC 7 provides the ramp waveform reference voltage RAMP as a signal having a step wave to the comparator 6-1. Here, when the ramp waveform reference voltage RAMP becomes equal to the voltage Vx of the pixel heating line, the output of the comparator 6-1 maintains the content of the counter 8 in the memory device 6-2 as data indicating the comparison period . At the first reading, the reset component? V of the unit pixel 2-1 is read. In the reset component DELTA V, noise fluctuating for each unit pixel 2-1 is included as an offset. However, the variation of the reset component? V is generally small. The reset level is uniform for all the unit pixels 2-1. Thus, the output of any column line Vx is approximately known.

Therefore, at the time of reading the first reset component? V, it is possible to shorten the comparison period performed by the comparator 6-1 by adjusting the ramp waveform reference voltage RAMP. In this example, 7-bit data representing up to 128 clock pulses are counted to perform comparison.

The second reading is performed by the same operation as the first reading. However, in the second reading operation, the reset component? V and the signal component corresponding to the incident light amount are read out from the unit pixel 2-1.

That is, the data is read out from the unit pixel 2-1 of an arbitrary row Hx, and the heat lines V0, V1 ... The DAC 7 supplies the ramp waveform reference voltage RAMP as a stepped signal to the comparator 6-1. Each comparator 6-1 compares the ramp waveform reference voltage RAMP with an arbitrary voltage of the pixel heating line Vx.

The second count is made in the counter 8 while the DAC 7 supplies the ramp waveform reference voltage RAMP, which is a signal having a stepped waveform. Here, the output of the comparator 6-1 is inverted to hold the contents of the counter 8 in the memory device 6-2 when the voltage Vx of the RAMP and the pixel heating line becomes equal. At this time, the length of the comparison period performed by the comparator 6-1 in the second reading operation is stored in a position different from the storing position of the length of the comparison period performed by the comparator 6-1 in the first reading operation do.

At the end of the AD conversion period, the column scanning circuit 4 outputs the n-bit digital signal indicating the length of the comparison period performed by the comparator 6-1 in the first read operation and the n- Bit digital signal indicating the length of the comparison period performed by the data output circuit 9 from the memory unit 6-2 to the data output circuit 9 through the horizontal data transmission line 6-4 having a width of 2n bits do. In the data output circuit 9, the sequential subtracting circuit subtracts the n-bit digital signal representing the length of the comparison period performed in the first read operation from the n-bit digital signal indicating the length of the comparison period performed in the second read operation , And outputs the difference to the external circuit as the subtraction result. Then, the same operation is continuously performed for each row to generate a two-dimensional image.

In the solid-state image pickup device (CMOS image sensor) 1 as described above, a parallel reading method is employed. Therefore, the scanning in the row direction (vertical scanning) is very slow. On the other hand, the scanning operation in the column direction is very fast because all data of a unit pixel of one row must be read within a 1H (horizontal scan) period.

However, in the solid-state image pickup device 1 (CMOS image sensor) as described above, the horizontal data transmission line is very long. Horizontal data transmission lines typically have a length of 7 mm. Therefore, due to factors such as the parasitic capacitance and the parasitic resistance of the horizontal data transmission line, the detection time difference largely fluctuates between the data transmission line segment close to the sense circuit and the data transmission line segment including the sense amplifier, which is separated from the data output circuit.

Generally, the counting data from the counter latch memory unit 6-2 of each pixel string arranged in a wide range is serially read and data is transferred to the data output circuit 9 through the horizontal data transmission line 6-4 The pieces of data received from all the memory units 6-2 are read simultaneously with respect to the data latch timing of the data output circuit 9 including the sense amplifier circuit.

In this case, the data output circuit 9 outputs the data input from the memory section 6-2 close to the data output circuit 9 and the data input from the memory section 6-2 far from the data output circuit 9 Must always be latched at the same timing.

However, when the memory section 6-2 is separated from each other in a wide area, the difference in data transmission line delay time between the memory sections 6-2 is very large, making it difficult to simultaneously latch the data pieces from the source. The higher the transmission rate (i.e., the higher the clock frequency), the greater the effect of the time delay of the imaging data transmitted along the horizontal data transmission line 6-4.

2. Description of the Related Art In recent years, image sensors have been progressing not only in the adoption of a plurality of unit pixels and in the speedup operation but also in the enlargement. As a result, the effect of the time delay of the imaging data transmitted along the horizontal data transmission line hampers the thermal (horizontal) scanning acceleration of the image sensor.

The inventor of the present invention can reduce the influence of the time delay of the imaging data transmitted along the transmission line to the data output circuit and drive the data output circuit to read the data accurately and precisely, A data transfer circuit capable of accelerating the scanning speed has been revolutionized, and a camera system employing a solid-state image pickup device as well as a solid-state image pickup device employing a data transfer circuit has been revolutionized.

According to an embodiment of the present invention, there is provided a data transmission system comprising: a plurality of transmission lines, each of which is used to transmit data; a transmission line for detecting the data transmitted by one of the transmission lines, A plurality of data output sections arranged to form a parallel circuit and each used to hold data in accordance with an input level and each of which is responsive to the selection signal to output the data A plurality of holding units used to transfer the data held in one data transmission line included in a transmission line; a capture clock signal supply unit configured to supply the capture clock signal to each of the data output units; A clock signal supply unit configured to supply a clock signal, And a scanning unit configured to generate a signal and output the selection signal to each of the holding units, wherein the data transmission line is arranged in a direction in which the holding unit is arranged to form the parallel circuit, Wherein the column scanning unit is arranged in a direction in which the data holding unit is arranged to form the parallel circuit and is used to generate the selection signal in synchronization with the received driving clock signal, A plurality of selection signal generation units for outputting the selection signal to a data holding unit included in the data holding unit as a data holding unit corresponding to the selection signal; And a plurality of driving clock signals And the data capture clock supply unit supplies a clock signal having the master clock signal or the master clock signal as a reference signal to the data transfer circuit for supplying the capture clock signal to each of the plurality of data output units, Is provided.

According to another embodiment of the present invention, there is provided an image sensing apparatus comprising: an image sensing unit arranged to form a matrix and each including a plurality of pixels used for performing photoelectric conversion processing; a plurality of data transmission lines each used for transmitting data; A plurality of data output sections each of which is used to detect data transmitted by one of the data transmission lines and to capture the detected data in synchronization with a data capture clock signal; Each of which is used to hold data in accordance with a level and which is responsive to a select signal to transmit the held data to a data transmission line associated with the held data, And the data capture clock signal to the data output section A clock supply unit configured to generate at least a master clock signal; and a column selection unit configured to generate the selection signal in synchronization with the driving clock signal, Wherein the data retaining unit is arranged in a direction in which the data retaining unit is arranged to form the parallel circuit and is also connected to each of the data output units arranged in the same direction, Each of which is used to generate the selection signal in synchronization with the received driving clock signal, and which, as a data holding section corresponding to the selection signal, Which is output to the data holding unit included in the And a drive clock propagation line for propagating the master clock signal and supplying the master clock signal as the drive clock signal to each of the select signal generators, wherein the data capture clock supplier comprises: Signal or a clock signal having the master clock signal as a reference signal is supplied to each of the data output sections as the data capture clock signal.

According to another embodiment of the present invention, there is provided a solid-state imaging device including a solid-state imaging device, an optical system for imaging an image on the imaging device, and a signal processing circuit for processing an image signal output by the solid- An image sensing unit arranged to form a matrix and each including a plurality of pixels used for performing a photoelectric conversion process, a plurality of data transmission lines each used for transmitting data, and a plurality of data transmission lines, A plurality of data output sections used to capture the data detected in synchronization with the data capture clock signal and a data latch circuit arranged to form a parallel circuit, And in response to the selection signal, each of the data transmission lines associated with the held data A data capture clock supply unit configured to supply the data capture clock signal to each of the data output units; and a control unit configured to control at least a master And a column scanning unit configured to generate the selection signal in synchronization with the driving clock signal and outputting the selection signal to each of the data holding units, Wherein the data holding section is arranged in a direction in which the holding section is arranged to form a parallel circuit and is also connected to each of the data output sections arranged in the same direction, Each of the received drive clock signals A plurality of selection signal generation units used for generating the selection signal in synchronization with each other and used for outputting the selection signal to a data holding unit included in the data holding unit as a data holding unit corresponding to the selection signal, And a drive clock propagation line for propagating the master clock signal and supplying the master clock signal as the drive clock signal to each of the selection signal generators, wherein the data capture clock supplier supplies the master clock signal, A clock signal having a signal as a reference signal is supplied to the data output section as the data capture clock signal.

According to the present invention, the influence of the time delay of the imaging data transmitted along the horizontal data transmission line to the data output unit can be reduced. Therefore, the data output unit can capture the imaging data with high accuracy and high precision.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

3 is a block diagram showing an exemplary configuration of an on-a-row ADC type solid-state image pickup device (CMOS image sensor) including a data transfer circuit according to an embodiment of the present invention. 4 is a diagram showing a more specific configuration example of the data transmission system of the parallel ADC type solid-state image pickup device of Fig.

3, the solid-state image pickup device 10 includes a pixel array unit 11, a row scanning circuit 12, a column scanning circuit 13, a timing control circuit 14, an ADC group A plurality of data output circuits (data detection circuits) 17 each including a sense amplifier (S / A) circuit 15, a DAC 16, and a sense amplifier (S / A) circuit 171,

The pixel array unit 11 is configured in such a manner that the unit pixels 111 are arranged in matrix form (matrix shape) of M rows and N columns. Each unit pixel 111 includes a photodiode and an intra-pixel amplifier.

The timing control circuit 14 is a circuit for generating an internal clock signal, and the row scanning circuit 12 is a circuit for generating a row address and controlling a row scanning operation. The column scanning circuit 13 is a circuit for generating a column address and controlling a column scanning operation. The solid-state image sensing device 10 further includes a row scanning circuit 12, a column scanning circuit 13, and a timing control circuit 14 as a control circuit for sequentially reading signals of the pixel array unit 11 do.

The ADC group 15 having a function of converting an analog signal into digital data forms a parallel ADC block 153 for a plurality of heat lines V0, V1, .... Specifically, the ADC group 15 includes not only the same plurality of comparators 151 connected to one of the pixel heating lines V0, V1, ..., but also the same plurality of comparators 151 connected to one of the comparators 151 And an asynchronous up / down counter (hereinafter referred to as a counter latch) 152. In the exemplary configuration of Fig. 3, the ADC group 152 includes (n + 1) comparators 151, i.e., comparators 151-0 through 151-n, as shown in FIG. A counter latch 152 connected together with a particular comparator 151 and a particular comparator 151 in the comparator forms a parallel ADC 15A for the pixel column associated with the particular comparator 151. [ Each of the comparators 151 generates a ramp waveform reference voltage RAMP generated by the DAC 16 as a signal having a stepped waveform by selecting one of the line H0, H1, ... and the pixel line V0, V1, ..., With the analog signal generated by the specific unit pixel 111 connected to the comparator 151 by one of the signals. While receiving the output of the comparator 151, each of the counter latches 152 determines whether or not the time length of the comparison performed by the comparator 151, that is, the time length of the comparison performed by the analogue pixel 111 generated by the specific unit pixel 111 of the pixel string of the pixel matrix Up or count-down operation for counting the number of clock pulses generated by the timing control circuit 14 in order to measure the amount of the signal.

The output of each counter latch 152 is connected to the data transmission line 154. The data transmission line 154 is also connected to the input terminal of the sense amplifier circuit of the data output circuit 17. [

The counter latch 152 executes the function of the data holding circuit as follows. At the initial stage, the counter latch 152 is set to a count-down state in which a countdown operation is performed in order to measure the amount of the reset voltage appearing on the unit pixel 111. When the output COMPOUTi of the comparator 151 is inverted, the counter latch 152 stops the count-down operation and maintains the count value.

When counter latch 152 initiates a count-down operation, counter latch 152 typically includes an initial value of zero. The initial count value is an arbitrary value of the gradation of the AD conversion performed by the ADC 15A. Therefore, the count value latched at the end of the count-down operation indicates a reset count period proportional to the reset component DELTA V of the unit pixel 111 described above.

Thereafter, the counter latch 152 is set to the count-up state in which the count-up operation is performed to measure data indicating the amount of light incident on the unit pixel 111. [

When the output COMPOUTi of the comparator 151 is inverted, the counter latch 152 stops the count-up operation and outputs a count value indicating the period of the comparison process performed by the comparator 151, The count value indicating the difference between the reset component DELTA V and the imaging data generated in the unit pixel 111 is latched.

The counter value finally latched in the counter latch 152 is used as a digital signal when the scanning operation performed by the column scanning circuit 13 hits the counter latch 152 via the data transmission line 154 And is supplied to the sense amplifier circuit 171.

Typically, the column scanning circuit 13 is activated by being driven by the master clock MCK after, for example, the start pulse STR is supplied. The column scanning circuit 13 supplies the selection signal to the counter latch 152 through the selection line SEL and asserts the data latched in the counter latch 152 on the data transmission line 154. [ The column scanning circuit 13 outputs a selection signal to the counter latch 152 through the selection line SEL in synchronization with the driving clock pulse CLK derived from the master clock pulse MCK, that is, the driving clock pulse CLK based on the master clock pulse MCK, .

The ADC 15A provided in the solid-state image pickup device 10 shown in Fig. 3 will be described with reference to Fig. 4, which is a block diagram showing a typical configuration of a more detailed data transmission system.

As shown in Fig. 4, the data transmission system includes counter latches 152-0 to 152-n, and uses as many serial circuits as data bits. The serial circuits provided with the data bits respectively include a counter CNT, a latch LTC, and a drive transistor circuit DRV Tr connected in series with each other. Typically the number of data bits is 10 or 12. The number of counter latches 152-0 to 152-n described above is n + 1, and the data transmission system shown in Fig. 4 is composed of (n + 1) parallel ADCs 15A.

In the operation of the transmission data, the column scan circuit 13 sequentially supplies selection signals to the counter latches 152-0 to 152-n through the selection lines SEL0 to SELn, respectively. The sequential operation of sequentially supplying the selection signal to the counter latches 152-0 to 152-n is started by the start pulse at the selected start position and is shifted by a shift register or the like used in the column scanning circuit 13 By successively selecting the pixel columns to be displayed. The information of 0 or 1 generated by each drive transistor circuit DRV Tr is read by the data transmission line 154. Information appearing on the data transmission line 154 is detected by the sense amplifier circuit 171 used in the data output circuit 171 connected to the data transmission line 154. [ The data output circuit 17 outputs the information detected by the data output circuit 17 to the output data processing circuit 20.

5 is a diagram showing a specific example of the drive transistor circuit DRV Tr used in the counter latch 152 according to the present embodiment. 5, the drive transistor circuit DRV Tr typically includes an NMOS (n-channel MOS) selection transistor NT1 and an NMOS data transistor NT2, which are connected to a data line 154 and a predetermined potential Are connected in series with each other. The gate of the NMOS select transistor NT1 is connected to one of the select lines SEL0 to SELn driven by the column scan circuit 13. [ On the other hand, the NMOS data transistor NT2 is connected to the latch LTC.

One of the selection lines SEL0 to SELn connected to the column scanning circuit 13 is connected to the gate of the NMOS selection transistor NT1 through the NMOS data NT2 which enters the ON or OFF state in accordance with the data latched in the latch LTC driving the NMOS data transistor NT2 And drives the transistor NT2 in a state in which the data transmission line 154 is connected. The information generated by the NMOS data transistor NT2 is read by the data transmission line 154 and detected by the sense amplifier circuit 171 serving as a data detection circuit.

When the data latched in the latch LTC is 1, a current path is generated and a current flows. When the data latched in the latch LTC is 0, the current path is cut off and no current flows.

In the data transmission system according to the present embodiment, the operation of reading the latched data of the counter latch 152 on the data transmission line 154 and the operation of detecting the data read on the data transmission line 154 are the same as the operations of the output data processing circuit Is performed in synchronization with the drive clock signal CLK based on the master clock signal MCK generated by the master clock supply circuit 21, which is provided in the data input stage of the master clock supply circuit 20.

The present embodiment is characterized in that the clock signal CLK is supplied to the counter latch 152 through a data transmission line 154 serving as a data bus by appropriately varying the time delay of the driving clock pulse CLK generated in the column scanning circuit 13 for supplying the selection signal to the counter latch 152 And is designed so as to be able to compensate for a variation in time delay of data propagated from the counter latch 152 to the sense amplifier circuit 171. [

The following description is directed to the counter latch 152 via the data transfer line 154 by an appropriate variation of the time delay of the drive clock pulse CLK generated in the column scan circuit 13 that supplies the select signal to the counter latch 152 A plurality of examples used for illustrating a data transmission system capable of compensating for a change in time delay of data propagated to the sense amplifier circuit 171 will be described.

≪ First Configuration Example of Data Transmission System &

Fig. 6 is a diagram showing a first configuration example of the data transmission system 30 according to the present embodiment.

The column scanning circuit 13 in the data transmission system 30 of this embodiment is basically a shift register 131 for sequentially shifting the start pulse STRT in synchronization with the driving clock CLK based on the master clock MCK. The sequentially shifted start pulse STRT generates select signals HSEL0 to HSELn for driving select lines SEL0 to SELn, respectively. Typically, the shift register 131 uses flip-flops 131-0 to 131n, each of which functions as a selection signal generator and latches the start pulse STRT and serves as one of the selection signals HSEL0 to HSELn.

In the column scanning circuit 13 used in the data transmission system shown in Fig. 6, the master clock supply circuit 21 supplies the master clock signal MCK to the shift register 13, which is composed of the selection signal generating units 131-0 to 131- To the column scanning circuit 13 via the master clock waveguide line LMCK1 connected to the input of the buffer 132 provided at a position near the approximate center of the buffer 131 to form a parallel circuit when viewed from the buffer 132 And causes the selection signal generating units 131-0 to 131-n to uniformly propagate the driving clock signal CLK generated by the buffer 132. [

The buffer 132 receives the master clock signal MCK and outputs the driving clock signal CLK to the selection signal generators 131-0 to 131-n through the driving clock transmission line LCLK1 and the driving clock distribution lines LCLK2-0 to LCLK2- -n). The driving clock propagation line LCLK1 is arranged in the direction in which the selection signal generating units 131-0 to 131-n are arranged.

The driving clock distribution lines LCLK2-0 to LCLK2-n start from the junction point on the driving clock propagation line LCLK1 and terminate at positions close to the clock input terminals of their respective selection signal generation units 131-0 to 131-n. The driving clock distribution lines LCLK2-0 to LCLK2-n are vertical to the direction of the selection lines SEL0 to SELn for conveying the selection signals HSEL0 to HSELn, that is, the arrangement directions of the selection signal generation units 131-0 to 131- Direction or in a direction perpendicular to the arrangement direction of the drive clock propagation lines LCLK1.

The master clock generator 21 also supplies the start pulse STRT to the column scanning circuit 13 via the start pulse wave line LSTRT connected to the data input terminal of the selection signal generator 131-0. The master clock generating unit 21 receives the master clock signal MCK as the data capture clock signal SACK through the phase adjusting unit 22 for transmitting the master clock signal MCK to the data output circuits 17-0 to 17- To the data output circuits 17-0 to 17-n. The data capture clock signal SACK line is supplied from the phase adjusting unit 22 to the data output unit 17-n of the latest stage from the position near the data input terminal of the data output circuit 17-0 at the farthest end from the phase adjusting unit 22, To a position near the data input terminal. The data input terminal of the data output circuit 17-n is an input terminal of the sense amplifier circuit 171 used in the data output circuit 17. [ The data-trapping clock signal SACK line is arranged in the same direction as the select lines SEL0 to SELn for transmitting the select signals HSEL0 to HSELn, that is, in the direction perpendicular to the arrangement direction of the drive clock transmission line LCLK1.

The data output circuits 17-0 to 17-n are connected to the respective data transmission lines 154-0 to 154-n. The data output circuits 17-0 to 17-n include sense amplifier circuits 171-0 to 171-n and data synchronization circuits 172-0 to 172-n, respectively. The sense amplifier circuit 171 detects the image pickup data on the data transmission line 154. That is, the sense amplifier circuit 171 receives and amplifies the image pickup data. The data synchronization circuits 172-0 to 172-n capture the image sensing data output by the sense amplifier circuit 171 in synchronization with the data capture clock signal SACK supplied by the data capture clock signal SACK line, To the output data processing unit 20. Typically, data sync circuit 172 is a flip flop driven by a data capture clock signal SACK.

In the typical configuration of the data transmission system 30 shown in Fig. 6, the master clock supply circuit 21 supplies the master clock signal MCK as the data capture clock signal SACK through the above-described data capture clock signal SACK to the data output circuit N to the data output circuits 17-0 to 17-n through the phase adjustment section 22 that transmits the data to the data synchronization circuits 172-0 to 172-n used in the respective data output circuits 17-0 to 17-n .

The phase adjustment section 22 adjusts the phase of the master clock signal MCK in the time delay adjustment processing so that the image pickup data outputted by the sense amplifier circuit 171 can be captured with high accuracy by the data synchronization circuit 172 .
The phase adjusting section 22 adjusts the phase of the master clock signal MCK in consideration of the propagation delay generated in the column scanning circuit 13 as the propagation delay of the master clock signal MCK propagated through the column scanning circuit 13. [

The phase adjustment section 22 outputs the imaging data from the counter latches 152-0 to 152-n to the data transmission lines 152-0 to 152-n driven by the selection signal lines HSEL0 to HSELn appearing on the selection lines SEL0 to SELn, respectively, N to the data output circuits 17-0 to 17-n through the transmission lines 154-0 to 154-n.

The typical configuration of the data transmission system 30 as shown in Fig. 6 is that between the start pulse propagation line LSTRT propagating the start pulse STRT generated by the master clock generation unit 21 and the master clock propagation line LMCK1, A shield line LSLD1 provided between the start pulse transmission line LSTRT and the drive clock propagation line LCLK1 and between the start pulse propagation line LSTRT and the drive clock distribution wiring LCLK2-0 is used. The shield line LSLD1, which is maintained at a predetermined fixed potential such as the potential of the ground, is connected between the start pulse propagation line LSTRT and the master clock propagation line LMCK1, between the start pulse propagation line LSTRT and the drive clock propagation line LCLK1, And the effect of interference between the driving clock line LCLK2 and the driving clock line LCLK2.

Likewise, the typical configuration of the data transmission system 30 shown in FIG. 6 is also arranged on the output side of the phase adjusting section 22 for adjusting the phase of the master clock signal MCK in parallel with the master clock transmission line LMCK1 and the master clock transmission line LMCK1 And a shield line LSLD2 provided between the driving clock propagation lines LCLK1. The shield line LSLD2, in which a predetermined fixed potential such as the potential of the ground is maintained, is used to eliminate undesirable effects such as the effect of interference between the master clock propagation line LMCK1, the drive clock propagation line LCLK1, and other clock propagation lines .

Fig. 7 shows a timing chart of the data transmission system 30 shown in Fig. 7, the shift register 131 for performing a column (horizontal) scanning operation is connected to the master clock generation unit 21, SELEL, SEL1, ..., SELn, respectively, after a delay of several hours on the basis of the master clock signal MCK generated by the select signal HSEL0, HSEL1, ..., SELn in synchronization with the drive clock signal CLK. , And HSELn sequentially as a signal for selecting the counter latch 152 (each serving as a data storage unit).

The pieces of the image pickup data stored in the counter latch 152 are read out on the data transmission lines 154-0 to 154-n and the data output circuits 17-0 to 17- amplified by the sense amplifiers 171-0 to 171-n, respectively, which are used in the respective sense amplifiers 171-1 to 171-n. The sense amplifiers 171-0 to 171-n output data AMPOUT [n: 0] as a result of amplification.

Data AMPOUT [n: 0] read by the sense amplifiers 171-0 to 171-n from the data transmission lines 154-0 to 154-n are finally asserted on the data capture clock signal SACK line In synchronization with the data capture clock signal SACK, to the data synchronization circuits 172-0 to 172-n as a signal derived from the phase adjustment processing performed by the phase adjustment unit 22 on the master clock signal MCK. Then, the data synchronization circuits 172-0 to 172-n transmit the data AMPOUT [n: 0] to the output data processing circuit 20. [

6, the phase adjusting unit 22 basically delays the master clock pulse MCK supplied to the data synchronizing circuit 172 through the phase adjusting unit 22, (That is, the variation of the time delay of the imaging data propagated from the counter latch 152 to the sense amplifier circuit 171 through the data transmission line 154) by the transmission line (or the data bus) 154 to an appropriate value To set the amount of phase adjustment at an appropriate value. Therefore, fluctuations in data transmission delay between the data transmission lines 154-0 to 154-n can be absorbed. As a result, the imaging data can be detected and output with high accuracy.

However, in some cases, it may be difficult for the data transmission system 30 to detect and output the imaging data appearing on the data transmission lines 154-0 to 154-n with high accuracy because of the following reasons.

Particularly, when the phase adjustment section 2 is used to perform only the phase adjustment processing, the ability to perform the above processing by the fluctuation of the clock frequency and the data transmission time delay is limited. In synchronization with the data capture clock signal SACK asserted on the data capture clock signal SACK line as a signal derived from the phase adjustment processing (i.e., phase delay processing) performed by the phase adjustment unit 22 on the master clock signal MCK, The operation performed by the data synchronizing circuits 172-0 to 172-n to acquire the data AMPOUT [0: n] from the pixel column (horizontal) scanning circuits 13-1 to 13- May be unsuccessful in some cases due to the improved speed of operation performed by the processor. The cause of unsuccessful motion is not just high speed. Another possible cause is the fact that the transmitted imaging data contains an extremely large skew component.

The skew components included in the transmitted data can be classified into the following four large categories.

The first category is used in the sense amplifier circuits 171-0 to 171-n and / or the counter latches 152-0 to 152-n used in the data output circuits 17-0 to 17-n, respectively Which is caused by so-called manufacturing process variation, as variation of the transfer time delay between the MOS transistors NT1 and NT2.

The second category includes a skew component caused by a transmission time delay variation caused by the pattern of the image pickup data transmitted through the data transmission lines (i.e., the horizontal signal lines) 154-0 to 154-n. The pattern of the imaging data is 1.0.1.0.1.0. Or a dynamic pattern such as 0.0.0.1.0.0. Or the like.

The third category includes skew components caused by noise, such as substrate noise and clock noise, as follows. A large noise will result in an abnormal event such as the reversal of the imaging data transmitted through the data transmission lines 154-0 to 154-n. However, even though the noise is not large, such noise may overlap each other in the image pickup data to be transmitted, causing occurrence of a phenomenon such as chattering in the vicinity of the threshold of the output amplifier circuit 171. [ Such a phenomenon increases the time required to reliably determine the amount of imaging data.

The fourth category is derived from the difference in physical distance to the sense amplifier circuit 171 used in the data output circuit 17 between the data latches 152 outputting the image pickup data transmitted through the data transmission line 154 And a skew component caused by a transmission time delay variation. The difference in physical distance is caused depending on whether the counter latch 152 is provided at a position far from the sense amplifier circuit 171 or at a position substantially adjacent to the sense amplifier circuit 171. [ In the typical configuration of the data transmission system 30, the counter latch 152-0 at the left end is the farthest from the sense amplifier circuit 171 while the counter latch 152-n at the right end is the sense amplifier circuit 171).

Therefore, the data AMPOUT [n: 0] generated by the sense amplifiers 171-0 to 171-n has a very long intermediate period. 7, the time delay caused by the sense amplifier circuit 171-0 associated with the counter latch 152-0 selected at the farthest end from the sense amplifier circuit 171 and the time delay caused by the counter latch 152 -0), the sum of the time delays of the selection signals HSEL0 is set so that the selection signals HSEL0 and HSELn are shifted intentionally at different timings in order to eliminate the fluctuation of the data transmission line time delay between the data transmission lines 154-0 to 154- The time delay caused by the sense amplifier circuit 171-n associated with the counter latch 152-n selected in the last stage of the sense amplifier circuit 171 and the time delay caused by the selection of the counter latch 152- Is different from the sum of the time delays of the selection signals HSELn. Therefore, it is difficult to set an appropriate data capture timing by using only a single data capture clock signal SACK in order to eliminate the difference in the delay time sum. The sum of the time delay caused by the sense amplifier circuit 171 and the time delay of the selection signal HSEL used for selecting the counter latch 152 associated with the sense amplifier circuit 171 is the sum of the data AMPOUT [n: 0.0 > 0]. ≪ / RTI > In some cases, in the worst case, it may not be possible to set the data capture timing using a single data capture clock signal SACK to obtain stable completion data AMPOUT [n: 0].

The skew component naturally caused by the difference in transmission distance exists in the structure of the image sensor. Also, in recent years, efforts to increase the size of the image sensor to follow the increasing number of pixels and increasing processing speed and the expanded market of single lens reflex cameras have made many advances. Therefore, the countermeasure against the skew component caused by the difference in the transmission distance plays an important role in improving the speed of the pixel row (horizontal) scanning operation.

Based on the foregoing, the following description describes a typical configuration of a data transmission system capable of appropriately following the increasing number of pixels and increasing processing speed of a CMOS image sensor.

≪ Second Configuration Example of Data Transmission System &

8 is a diagram showing a second configuration example of the data transmission system 30A according to the embodiment.

The data transfer system 30A of FIG. 8 is different from the data transfer system 30 of FIG. 6 in that in the case of the data transfer system 30 of FIG. 6, the master clock propagation line LMCK1 is connected to the selection signal generator 131- In the case of the data transmission system 30A of Fig. 8, the master clock propagation line LMCK1A is connected to the data output circuits 17-0 to 17-n in the vicinity of the central portion of the horizontal layout of the data output circuits 17-0 to 17- The input terminals of the sense amplifier circuits 171-0 to 171-n are wired to a position exceeding the position of the selection signal generating section 131-0, which is the selection signal generating section 131 at the farthest end from the data input terminal, Are used for the data output circuits 17-0 to 17-n, respectively. 8, the master clock propagation line LMCK1A is wired to a position exceeding the position of the selection signal generator 131-0 through the buffer 132, Is connected to the driving clock propagation line LCLK1 at a position exceeding the position of the driving clock propagation line 131-0. The driving clock propagation line LCLK1 extends in the direction perpendicular to the pixel column line (i.e., the direction perpendicular to the driving clock distribution line LCLK2).

8, the driving clock propagation line LCLK1 is generated in the column scanning circuit 13 so that the master clock propagation line LMCK1A is connected to the data output circuits 17-0 to 17-n, The output of the sense amplifier circuits 171-0 to 171-N is folded to a position exceeding the position of the selection signal generating section 131-0, which is the selection signal generating section 131 at the far- n are used for the data output circuits 17-0 to 17-n, respectively.

The driving clock distribution lines LCLK2-0 to LCLK2-n start from the junction on the driving clock propagation line LCLK1 and terminate at the position closest to the clock input ends of the respective selection signal generating units 131-0 to 131-n. The driving clock distribution lines LCLK2-0 to LCLK2-n are wired in the column line direction, that is, in the direction perpendicular to the direction of the driving clock propagation line LCLK1.

Therefore, in the data transmission system 30A shown in Fig. 8, the data transfer circuits 17-0 to 17-n located at the farthest far end from the data input terminals (i.e., the sense amplifier circuits 171-0 to 171- The input terminals of the data output circuits 17-0 to 17-n are connected to the data output circuits 17-0 to 17-n by the selection signal HSEL0 for the selection signal generator 131-0, The selection signals HSEL0 to HSELn are sequentially supplied to the arrays of the selection signal generating units 131-0 to 131-n in the order of termination by the selection signal HSELn for the selection signal generating unit 131-n closest to the data input terminal do.

8, the direction of propagation of the driving clock signal CLK along the array of the selection signal generating units 131-0 to 131-n is the same as that of the sense amplifier circuits 171-0 to 171-n The counter latches 152-0 to 152-n are the same as the transfer direction of the picked-up image data from the counter latches 152-0 to 152-n. In other words, the data transmission system 30A includes a driving-clock propagation line LCLK1 for passing the time constant of the capacitance and the driving clock signal CLK propagated to the selection signal generation units 131-0 to 131-n in the column scanning circuit 13 A change in the time delay caused by the resistance of the data latches 171-0 to 171-n from the counter latches 152-0 to 152-n to the sense amplifier circuits 171-0 to 171- Bus) by a variation of the time delay caused by the resistance of each.

Preferably, the time delay caused by the segment of the driving clock propagation line LCLK1, which is passed by the driving clock signal CLK propagated to an arbitrary specific portion of the selection signal generating portion 131 of the column scanning circuit 13, The sum of the time delays of the imaging data from the counter latch 152 on the same pixel row to the corresponding sense amplifier circuit 171 as the specific selection signal generating unit 131 is made constant irrespective of the selected pixel column position . As a result, the timing margin for driving the data output circuit 17 can be sufficiently taken, so that high-speed driving and high-speed reading are possible.

8, the driving clock waveguide line LCLK1 is connected to the driving clock distribution wiring LCLK2-n (that is, at the rightmost end of the layout of the selection signal generating units 131-0 to 131-n) (That is, the arrangement directions of the selection signal generating units 131-0 to 131-n) from the junction point with the driving clock distribution wiring LCLK2 of the repeater 23 Respectively. After passing through the repeater 23, the driving clock propagation line LCLK1 is wired in the hot line direction (direction orthogonal to the wiring direction of the selection signal generating units 131-0 to 131-n), and the data capture clock signal SACK is generated Is connected to the phase (delay) adjusting section 22A.

The start pulse propagation line LSTRT for transmitting the start pulse STRT in parallel to the master clock propagation line LMCK1A of the column scanning circuit 13 is connected to the data input terminals of the data output circuits 17-0 to 17- N from the last-stage selection signal generating section 131-n of the sense amplifier circuits 171-0 to 171-n used for the output circuits 17-0 to 17-n, respectively, To the generation section 131-0. Next, the start pulse supply line LSTRT is connected to the data input terminal of the selection signal generator 131-0, further extending in the direction of the hot line (i.e., the direction perpendicular to the direction of the drive clock signal LCLK1).

Therefore, in the data transmission system 30A of Fig. 8, for example, between the start pulse propagation line LSTRT for transmitting the start pulse STRT generated by the master clock generation unit 21, between the master clock propagation line LMCK1, A shield line LSLD1A is wired between the pulse propagation line LSTRT and the drive clock distribution wiring LCLK2-0. The shield line LSLD1A, which is held at a predetermined fixed potential, for example, the ground potential, is connected between the start pulse propagation line LSTRT and the master clock propagation line LMCK1, and between the start pulse propagation line LSTRT and the drive clock distribution line LCLK2-0 Lt; RTI ID = 0.0 > undesired < / RTI >

Similarly, in the data transmission system 30A of Fig. 8, the shield line LSLD2A is used between the master clock propagation line LMCK1A and the drive clock propagation line LCLK1 parallel to the master clock propagation line LMCK1A. The shield line LSLD2A is wired over a region in the vicinity of the drive clock distribution lines LCLK2-0 to LCLK2-n of the drive clock propagation line LCLK1 and a region in the vicinity of the output side of the phase adjustment portion 22 for adjusting the phase of the master clock MCK . The shield line LSLD2A, which is held at a predetermined fixed potential, for example, the ground potential, is used to suppress an undesirable influence such as interference between the master clock propagation line LMCK1A and the drive clock distribution line LCLK1. In the same way, in the data transmission system 30A of Fig. 8, the shield line LSLD3A is wired between the array of the selection signal generation units 131-0 to 131-n and the drive clock propagation line LCLK1. The shield line LSLD3A, which is held at a predetermined fixed potential, for example, the ground potential, is used to suppress the influence of interference or the like between the array of the selection signal generating units 131-0 to 131-n and the driving clock supply line LCLK1.

In the data transmission system 30A of Fig. 8, the shield line LSLDA is wired in such a manner that the start pulse supply line LSTRT is sandwiched between the shield line LSLDA and the shield line LSLD1A. Therefore, the shield line LSLD4A is provided on the lowermost side in Fig. Since the power line or the like is generally provided at the lowermost side of the drawing, the shield line LSLD4A is disposed between the start pulse propagation line LSTRT and the power supply line or the like.

When the master clock supply line LMCK1A is wired close to the power supply wiring instead of the start clock transmission line LSTRT, the shield line LSLD4A is wired between the master clock supply line LMCK1A and the power supply wiring.

FIG. 9 is a timing chart of the data transmission system 30A of FIG.

9 (a) shows a timing chart of the waveform of the master clock MCK generated in the master clock supply circuit 21. In Fig. 9B is a circuit diagram of the sense amplifier circuits 171-0 to 17-n used for the data input terminals of the data output circuits 17-0 to 17-n, that is, the data output circuits 17-0 to 17- Timing chart of the waveform of the driving clock signal CLK appearing on the driving clock propagation line LCLK1 connected to the clock input end of the selection signal generator 131-0 which is the farthest end side from the input terminal of the selection clock generator 171-n. 9C is a circuit diagram of a sense amplifier used for each of the data input terminals of the data output circuits 17-0 to 17-n of the drive clock propagation line LCLK1, that is, the data output circuits 17-0 to 17- Timing charts of the waveforms of the driving clock signal CLK appearing on the driving clock transmission line connected to the clock input terminal of the selection signal generating section 131-n, which is the latest one end from the input terminals of the circuits 171-0 to 171-n. 9D shows the timing of the waveform of the data capture clock signal SACK supplied from the output of the phase adjustment section 22A to the clock input terminal of the data synchronization circuit 172-n of the data output circuit 17-n at the latest stage A chart is shown. 9E shows the timing of the waveform of the data capture clock signal SACK supplied from the output of the phase adjustment section 22A to the clock input terminal of the data synchronization circuit 172-0 of the data output circuit 17-0 at the farthest end A chart is shown.

FIG. 9F shows a timing chart of a waveform of a selection signal (or a selection pulse) output by the selection signal generator 131-0 of the column scanning circuit 13. FIG. (G) of FIG. 9 shows the state of the selection signal (or signal pulse) SELn output by the selection signal generation section 131-n of the column scanning circuit 13, in which n is an integer having a value of typically 4,000 2 shows a timing chart of the waveform. 9 (h) shows a timing chart of the image pickup data transmitted from the counter latch 152-0 provided on the uppermost layer to the data transmission line 154-0. 9 (i) shows a timing chart of the image pickup data transmitted from the data transmission line 154-0 to the input terminal of the sense amplifier circuit 171-0 of the data output circuit 17-0 provided on the uppermost layer . 9 (j) shows a timing chart of the image pickup data transmitted from the data transmission line 154-n to the input terminal of the sense amplifier circuit 171-n of the data output circuit 17-n provided at the lowest layer . 9 (k) shows a timing chart of the image pickup data outputted by the data synchronizing circuit 171-n of the data output circuit 17-0 provided on the uppermost layer. 9 (1) shows a timing chart of an image taken by the data output from the data synchronization circuit 172-n of the data output circuit 17-n provided in the lowermost layer.

In the data transmission system 30A shown in Fig. 8, the propagation directions of the drive clock signal CLK along the drive clock propagation line LCLK1 parallel to the arrays of the select signal generators 131-0 to 131-n are the data transmission lines N from the counter latches 152-0 to 152-2 through the sense amplifiers 171-0 to 171-n through the sense amplifiers 171-0 to 171-n, the drive clock transmission lines LCLK1 And data transmission lines (i.e., data buses) 154-0 to 154-n are arranged. As apparent from the timing chart shown in Fig. 9, the driving clock signal line LCLK1, which is passed by the driving clock signal CLK supplied to the selection signal generating units 131-0 to 131-n in the column scanning circuit 13, The change in the time delay is caused by the data transfer lines 154-0 to 154-n from the counter latches 152-0 to 152-n to the sense amplifier circuits 171-0 to 171- Lt; / RTI >

The data transmission system 30A shown in Fig. 8 further includes a portion of the drive clock propagation line LCLK1 passed through the arbitrary one of the selection signal generation units 131 in the column scanning circuit 13 by the driving clock signal CLK And the time delay due to the portion of the data transmission line 154 as a time delay of propagation from the counter latch 152 on the same pixel column as the specific selection signal generation portion 131 to the corresponding sense amplifier circuit 171 Is constantly provided regardless of the position of the selected pixel column.

In such a configuration, a sufficient timing margin for driving the sense amplifier circuits 171-0 to 171-n and the data synchronization circuits 172-0 to 172-n can be read, so that high-speed drive and read operation can be performed have.

The data transmission system 30A shown in Fig. 8 is further analyzed below. It is assumed that the pixel row N1 adjacent to (or adjacent to) the data output circuit 17 is selected. In this case, the timing difference Tdiff_n between the data capture clock signal SACK and the image pickup data supplied to the data output circuit 17 is given as follows.

Tdiff_n? T1

The timing difference Tdiff_f between the data capture clock signal SACK supplied to the data output circuit 17 and the image pickup data is given by the following equation when the pixel column F1 far from the data output circuit 17 is selected.

Tdiff_f? T2

The physical layout is designed to set the relation T1 < RTI ID = 0.0 ># T2 < / RTI >

Tdiff_f? Tdiff_n

That is, the timing difference Tdiff_ between the clock signal supplied to the data output circuit 17 and the image pickup data is almost fixed regardless of the position of the selected pixel column. That is, the timing difference Tdiff_ between the data capture signal SACK and the imaging data is almost fixed, and does not depend on the position of the selected pixel column.

Therefore, the operating frequency F of the following circuit is given as follows.

F = 2 x 1 / (Tdiff_f-Tdiff_n) =?

This means that the upper limit of the actual operating frequency is rate-controlled by the upper limit operating frequency of the latter circuit itself. That is, there is no timing restriction according to the position of the selected pixel column.

The data transmission system 30A shown in Fig. 8 has a structure in which the driving clock signal CLK passed through the arbitrary one of the selection signal generation units 131 in the column scanning circuit 13 by the driving clock signal CLK, The data transmission line 154 as a time delay due to the segment of LCLK1 and the time delay from the counter latch 152 on the same pixel column as the specific selection signal generation unit 131 to the corresponding sense amplifier circuit 171, Is constantly provided regardless of the position of the selected pixel row. Therefore, a sufficient timing margin for driving the sense amplifier circuits 170-0 to 170-n and the respective data synchronization circuits 172-0 to 172-n can be taken, and high-speed drive and read operation can be performed .

≪ Third Configuration Example of Data Transmission System &

10 is a diagram showing a third configuration example of the data transmission system according to the embodiment. 11 is a diagram specifically showing a circuit of the third configuration example of the data transmission system 30B shown in Fig. 10 such as the data transmission system according to the embodiment.

The data transmission system 30B shown in Figs. 10 and 11 is configured to solve the problem of data skew generated in a column (horizontal) scanning operation. In particular, the data transmission system 30B shown in Figs. 10 and 11 is configured to solve the problem of the dependence of the transmission distance at the position of the pixel column.

First, the basic principle of the third configuration example will be described with reference to FIG.

10 includes, in addition to a data storage unit (or a data latch shown in FIG. 10) for storing data bits of all the counter latches 152, a series of fixed data 1.0.1.0. 6 in that pseudo memory units 24-0 to 24-n are provided for memorizing the pseudo-random numbers and the like. The fixed data is read out on the pseudo clock transmission line 25 at the same time that the picked-up data is read out on the data transmission line 154.

In the data transmission system 30B, the fixed data appearing on the pseudo clock transmission line 25 is supplied to the sense amplifier circuits 171-0 to 171-n via the sense amplifier circuit 26 and the phase adjustment unit 27 N to the data synchronization circuit 172-0 to 172-n as a data capture clock signal SACKD for determining the timing of capturing the data AMPOUT [n: 0]

By designing the data transmission system 30B in such a configuration, the transmission distance of the image pickup data propagated to the data output circuit 17 is always the same as the transmission distance of the pseudo clock signal propagated to the data output circuit 17. [ Therefore, the transmission time delay due to the transmission distance of the imaging data is always the same as the transmission time delay due to the transmission distance of the pseudo clock signal.

As a result, the skew component due to the transmission distance is removed. As described above, the skew component due to the transmission distance is a component belonging to the fourth category of the four categories for classifying the skew component. Therefore, the data capture margin increases, so that the captured image data can be captured stably.

11 is a diagram showing in more detail a third configuration example of the data transmission system 30B of Fig. 11, each of the pseudo-clock storage units 24-0 to 24-n used in the data transmission system 30B is provided at the output terminals of the counter latches 152-0 to 152-n And a driving transistor DRV Tr having the same structure as the driving transistor DRV Tr.

Namely, each of the pseudo clock storage units 24-0 to 24-n includes NMOS select transistors PNT1 and NMT2 which form a series circuit between a line having a predetermined potential equal to the ground potential and a pseudo clock transmission line 25, The data transistor PNT2 is used.

The gate of the NMOS select transistor PNT1 is connected to one of the selection lines SEL0 to SELn driven by the column scanning circuit 13. [ On the other hand, the gate of the NMOS data transistor PNT2 on any even-numbered pixel column is connected to the ground potential through the inverter INV1. In the configuration shown in Fig. 11, the even-numbered pixel columns are the pixel columns of the pseudo-clock storage units 24-0, 24-2, ..., and 24-n-1.

On the other hand, the gate of the NMOS data transistor PNT2 on any odd-numbered pixel column is directly connected to the ground potential. 11, odd-numbered pixel rows are pixel columns of the pseudo-clock memory units 24-1, 24-3, ..., and 24-n.

As described above, according to the present embodiment, the configuration of each of the pseudo-clock storage units 24-0 to 24-n is basically the same as the configuration of each of the counter latches 152-0 to 152-n. However, the configuration of each of the pseudo-clock memories 24-0 to 24-n does not include a latch for storing the imaging data. Instead of such a latch, the gate of the NMOS data transistor PNT2 receives a signal having logic level 1 output by the inverter INV1 physically embedded and grounded or logic level 0 generated by ground. That is, the gate of the NMOS data transistor PNT2 is a series of fixed data 1.0.1.0. And the like.

As described above, according to the present embodiment, it is possible to eliminate the position-dependent skew component due to the transmission distance of the image pickup data as a component belonging to one of the four categories of the skew component that interfered with the speed-up during data transmission . Therefore, this embodiment can contribute to the speed-up of the image sensor and / or the enlargement of the sensor.

Further, since the imaging data and the pseudo clock signal are transmitted through the same pseudo clock transmission line 25 as the data transmission line 154 and the data transmission line 154, respectively, the embodiment can make the change of the process between the chips and / Which is easy to absorb. Thus, the yield can be improved. Further, since the data capture margin in the synchronization processing executed by the data synchronization circuit 172 can be expanded, the design is facilitated. Thus, the design period and the number of processes can be reduced.

≪ Fourth Configuration Example of Data Transmission System &

12 is a diagram showing a fourth configuration example of the data transmission system according to the present embodiment.

The data transmission system 30C shown in Fig. 12 is different from the sense amplifier circuits 171-0 to 171-n included in the data transmission system 30B in that the differential type sense amplifier circuits 171C-0 to 171C -n) is used in the data transmission system 30B shown in Fig.

The configuration of the data transmission system 30C is almost the same as that of the data transmission system 30B. However, in order to use the differential sense amplifier circuits 171C-0 to 171-n, two pseudo clock data transmission lines 25P and 25M as well as two data transmission lines 154P and 154M are provided for each data transmission channel. Is required. The counter latches 152C-0 to 152C-n in the same pixel column output complementary imaging data to the data transmission lines 154-0P and 154-0M to 154-nP and 154-nM, respectively, The units 24C-0 to 24C-n output complementary pseudo clock signals to the pseudo clock data transmission lines 25P and 25M.

12, the driving transistor circuit DRV Tr used in each of the counter latches 152C-0 to 152C-n is normally connected to a line having a predetermined potential (for example, a ground potential) and a data transmission line 154 (N-channel MOS) selection transistor NT1 and an NMOS data transistor NT2 which are connected in series to each other between a gate electrode of the transistor MN1 and a gate electrode of the transistor MN1 (or the data transmission line 154-nP of the lowest layer). The gate of the NMOS select transistor NT1 is connected to the selection lines SEL0 to SELn driven by the column scanning circuit 13 and the gate of the NMOS data transistor NT2 is connected to the latch LTC included in the above- And is connected through an inverter INV2. The driving transistor circuit DRV Tr used in each of the counter latches 152C-0 to 152C-n is connected to a line having a predetermined potential (for example, a ground potential) and a data transmission line 154-0M NMOS (n-channel MOS) select transistor NT3 and an NMOS data transistor NT4 which are connected in series with each other between the data transfer line (data transfer line 154-nM). And the gate of the NMOS select transistor NT3 is connected to one of the selection lines SEL0 to SELn driven by the column scanning circuit 13. [ On the other hand, the gate of the NMOS data transistor NT4 is directly connected to the latch LTC included in the aforementioned series circuit which is the same as the drive transistor circuit DRV Tr.

12, each of the pseudo clock storage units 24C-0 to 24C-n is configured to form a serial circuit between a line having a predetermined potential (for example, a ground potential) and a pseudo clock transmission line 25P An NMOS select transistor PNT1 and an NMOS data transistor PNT2 connected to each other are used.

The gate of the NMOS select transistor PNT1 is connected to one of the selection lines SEL0 to SELn driven by the column scanning circuit 13. [ And the gate of the NMOS data transistor PNT2 in any even-numbered pixel column is connected to the ground potential through INV1. In the configuration shown in Fig. 12, the even-numbered pixel columns are the pixel columns of the pseudo-clock storage units 24C-0, 24C-2, ..., 24C-n-1.

On the other hand, the gate of the NMOS data transistor PNT2 in any odd pixel column is directly connected to the ground potential. In the configuration shown in Fig. 12, odd-numbered pixel columns are pixel columns of pseudo-clock storage units 24C-1, 24C-3, ..., 24C-n.

Each of the pseudo clock storage units 24C-0 to 24C-n includes NMOS select transistors PNT3 (PNT3) connected to each other to form a series circuit between a line having a predetermined potential (for example, ground potential) And the NMOS data transistor PNT4.

And the gate of PNT3 is connected to one of the selection lines SEL0 to SELn driven by the column scanning circuit 13. [ On the other hand, the gate of PNT4 in any even pixel train is directly connected to the ground potential.

However, the gate of PNT4 in any odd pixel train is connected to the ground potential through inverter INV3.

According to the embodiment shown in Fig. 12, by adopting the above-described differential configuration, in addition to the above-mentioned effects, the data transmission system 30C has an effect of increasing the noise margin, so that the third category among the four skew component categories It is possible to efficiently remove the skew component caused by the noise during transmission of the imaging data as the belonging component.

≪ Fifth Configuration Example of Data Transmission System &

13 is a diagram showing a fifth configuration example of the data transmission system according to the present embodiment. 14 is a timing chart of the data transmission system 30D of Fig.

The data transfer system 30D shown in Fig. 13 is different from the data transfer system 30C shown in Fig. 12 in that, in the case of the data transfer system 30D shown in Fig. 13, And is executed at the level switching edge of the clock signal. Specifically, when the pseudo clock signal makes a transition from the low level "1" to the low level "0" and when the pseudo clock signal makes a transition from the low level "0" to the low level "1" 17 are captured. 13, the master clock signal having the phase adjusted by the phase adjusting unit 28 is used as the second data capture clock signal MCKD for capturing the imaging data, and the output data And outputs it to the processing circuit 20.

Each of the data output circuits 17D-0 to 17D-n includes respective sense amplifier circuits 171D-0 to 171D-n, data synchronization circuits 172D-0 to 172D-n, 173-0 to 173-n, the respective second latches 174-0 to 174-n, the respective first switches 175-0 to 175-n, and the respective second switches 176-0 ~ 176-n). The first latch 173 and the first switch 175 together form a first series circuit and the second latch 174 and the second switch 176 together form a second series circuit. The first serial circuit and the second serial circuit form a parallel circuit acting as a data capture circuit 177 between the sense amplifier circuit 171D and the data synchronization circuit 172D. That is, the data capturing circuits 177-0 to 177-n are included in the data output circuits 17D-0 to 17D-n, respectively.

More specifically, the data input terminals of the first latches 173-0 to 173-n and the second latches 174-0 to 174-n are connected to the outputs of the sense amplifier circuits 171D-0 to 171D- do. The data capture clock signal SACKD generated by the phase adjustment unit 27 is supplied to the clock input terminals of the first latches 173-0 to 173-n, and the data capture clock signal SACKD itself is supplied to the second latches 174-0 to 173- 174-n.

The outputs of the first latches 173-0 to 173-n are respectively provided to the data input terminals of the data synchronization circuits 172D-0 to 172D-n via the first switches 175-0 to 175-n. The outputs of the second latches 174-0 to 174-n are connected to the same data input terminals of the data synchronization circuits 172D-0 to 172D-n via the respective second switches 176-0 to 176- Respectively.

The inverted signal of the data capture clock signal SACKD is supplied to the inverting input of the first switch 175-0 to 175-n. When the data capture clock signal SACKD is at a low level, each of the first switches 175-0 to 175-n is held in the conductive state, and the captured data latched in the first latches 173-0 to 173- To the data synchronization circuits 172D-0 to 172D-n, respectively.

On the other hand, the data capture clock signal SACKD itself is provided to the inputs of the first switches 176-0 to 176-n. When the data capture clock signal SACKD is at the high level, the second switches 176-0 to 176-n are kept in the conductive state, and the captured data latched in the second latches 174-0 to 174-n, respectively To the data synchronization circuits 172D-0 to 172D-n, respectively.

Thus, the first switches 175-0 to 175-n and the second switches 176-0 to 176-n are complementarily turned on and off. As a result, the first switches 175-0 to 175-n latch the latch data of the first latches 173-0 to 173-n to the data input terminals of the data synchronizing circuits 172D-0 to 172D-n, respectively And the second switches 176-0 to 176-n transmit the latch data of the respective second latches 174-0 to 174-n to the data input terminals of the data synchronization circuits 172D-0 to 172D-n Respectively, in a complementary manner.

The reason why the data output circuit 17D is configured as described above will be described below.

The shift register 131 used in the column scanning circuit 13 operates in synchronization with the driving clock signal CLK based on the master clock signal MCK. Generally, the clock tree structure including the buffer 132 is employed to distribute the drive clock signal CLK to the select-signal generators 131-0 to 131-n used in the shift register 131. [ In such a tree structure, the wirings for distributing the drive clock signal CLK to the selection-signal generating units 131-0 to 131-n tend to be longer, respectively.

Therefore, since the wirings for distributing the driving clock signal CLK to the selection-signal generating units 131-0 to 131-n used in the shift register 131 tend to become longer due to the respective tree structures, the selection signals HSEL0 , HSEL1, ... , And HSELn may have a delay from the master clock signal MCK, respectively, and may be output by the selection-signal generating units 131-0 to 131-n.

Selection signals HSEL0, HSEL1, ... The counter latches 152-0 to 152-n selected by HSELn select the data transfer lines 154-0 to 154-n (strictly speaking, data transfer lines 154-0P to 154-nP, 154 -0 M to 154-nM), respectively. Similarly, the selection signals HSEL0, HSEL1, ... , Pseudo clock storage units 24-0 to 24-n selected by HSELn assert pseudo clock signals in pseudo clock data transmission lines 25 (strictly speaking, data transmission lines 25P and 25M) in the current mode . The data transmission lines 154-0P to 154-nP and 154-0M to 154-nM as well as the pseudo clock data transmission lines 25P and 25M) Even if the signal is asserted to the data transmission lines 154-0 to 154-n and the pseudo-clock data transmission line 25, some voltage fluctuation occurs.

Therefore, for each of the data transmission lines 154-0 to 154-n and the pseudo clock data transmission line 25, the charging time is required according to the time constant determined by the parasitic capacitance of the data transmission line and the parasitic resistance. However, since the time constant corresponding to the pixel column farthest from the sense amplifier circuit 171 is the largest, and the time constant corresponding to the pixel string closest to the pixel circuit 171 is the smallest, the charging time becomes longer. This difference in charging time causes a difference in the imaging data / pseudo clock signal transmission time delay between the pixel column near the remote pixel column and the pixel column near the remote pixel column.

In order to solve the problem of the difference in the imaging data / pseudo clock signal transmission time delay between the pixel column near the far pixel column and the pixel column close to the far pixel column, the image sensing data is outputted from the counter latches 152-0 to 152-n via the data transmission lines 154P and 154M The pseudo clock signal for capturing the image pickup data is transferred from the pseudo-clock storage units 24C-0 to 24C-n via the pseudo clock data transmission lines 25P and 25M to the data output circuit 17. As shown in the timing chart of Fig. 14, since the pseudo clock signal is transmitted from the built-in pseudo clock storage units 24C-0 to 24C-n in the same manner as the counter latches 152-0 to 152- As a signal, the pseudo clock signal has only a frequency which is not higher than half the frequency of the master clock signal MCK, such as the operating frequency for outputting the imaging data.

Therefore, when the data capture clock signal SACKD is used as a clock signal to capture the imaging data AMPOUT, it is necessary to capture the data AMPOUT for both the rising edge and the falling edge of the signal. The configuration shown in Fig. 13 includes the general data capturing circuits 177-0 to 177-n described above.

The data capturing circuits 177-0 to 177-n latch the image sensing data AMPOUT at the falling edge and the rising edge of the data capture clock signal SACKD, respectively, and latch the data AMPOUT during the low level and the high level of the signal SACKD, Latches, i.e., a first latch 173 and a second latch 174. The data trapping circuits 177-0 to 177-n are connected to two switches 173-1 to 177-n for selecting the output of the first latch 173 or the output of the second latch 174 during the low level and the high level of the data capture clock signal SACKD, I.e., a first switch 175 and a second switch 176.

More specifically, the data capture clock signal SACKD is supplied to the first latches 173-0 to 173-n and the second latches 174-0 to 174-n. The imaging data AMPOUT is transferred from the sense amplifier circuits 171D-0 to 171D-n to the second latches 174-0 to 174-n, respectively, at the rising edge of the data capture clock signal SACKD, And held in the second latches 174-0 to 174-n. During the high level of the data capture clock signal SACKD, the second switches 176-0 through 176-n provided subsequent to the second latches 174-0 through 174-n are in the conductive state, respectively, and the second latches 174- 0 to 174-n to the data synchronization circuits 172D-0 to 172D-n, respectively, as the data LAOUT0 to LAOUTn.

The imaging data AMPOUT is transmitted from the sense amplifier circuits 171D-0 to 171D-n to the first latches 173-0 to 173-n, respectively, at the falling edge of the data capture clock signal SACKD, And held in the first latches 173-0 to 173-n. During the low level of the data capture clock signal SACKD, the second switches 176-0 through 176-n are each in a non-conductive state, but the first switches 175-3 through 173-n provided subsequent to the first latches 173-0 through 173- -0 to 175-n are in the conductive state and the imaging data AMPOUT from each of the first latches 174-0 to 174-n are supplied to the data synchronization circuits 172D-0 to 172D-n as the imaging data LAOUT0 to LAOUTn, Respectively.

As described above, the image pickup data AMPOUT can be captured and synchronized using both edges of the data capture clock signal SACKD, i.e., the rising edge and the falling edge. In addition, the data capturing circuit 177 for acquiring and synchronizing the imaging data AMPOUT includes only two latches: a first latch and a second latch, and two switches, i.e., a first switch and a second switch It is noted that the data capturing circuit 177 can be designed to have the same degree of area as a circuit using a normal F / F (flip-flop).

The pseudo clock signal is generated in the same phase as the data because the pseudo clock signal basically has the same transfer time delay as the transfer time delay of the imaging data irrespective of the location of the selected pixel column. However, when the pseudo clock signal is used as the data capture clock signal, the imaging data may inevitably be captured as the imaging data AMPOUT during a predetermined period including the overlapping time of the edges of the data. In order to solve this problem, a phase adjustment unit 27 is used to generate a data capture clock signal SACKD that guarantees proper setup time and hold / hold time when latching the image pickup data AMPOUT. Adjust the phase appropriately.

7, which is a timing chart of the first configuration example of the data transfer system 30, data (data) AMPOUT [n: 0] output by the sense amplifier circuits 171-0 to 171- The setup time and hold time guaranteed by the capture clock signal SACKD can be set to a constant value at any time regardless of whether the selected pixel column is farther from the data output circuit 17 or close to the column.

The data LAOUT [n: 0] obtained as a result of a latch operation executed in synchronization with the data capture clock signal SACKD no longer includes skew components belonging to the first, second and third categories of the above four categories . As described above, the skew component belonging to the first category is caused by a transmission time delay variation caused by a so-called manufacturing process variation, and the skew component belonging to the second category is caused by a transmission time delay variation Lt; / RTI > The third category includes skew components caused by noise.

Since the image pickup data LAOUT [n: 0] is obtained as a result of the latch operation executed in synchronization with the data capture clock signal SACKD, the image pickup data LAOUT may still include skew components belonging to the fourth category. As described above, the skew component belonging to the fourth category is a time delay variation taking the master clock signal MCK as a reference, and the transmission due to the difference in the physical distance to the sense amplifier circuit 171 between the data latches 152 Is the skew component caused by the time delay variation. It is necessary to synchronize the imaging data LAOUT by using the master clock signal MCK and the data synchronization circuit 172D since the imaging data LAOUT must be finally transmitted to the output data processing circuit 20 driven to operate by the master clock signal MCK have.

As the skew component caused by the transmission time delay variation caused by the difference in the physical distance to the sense amplifier circuit 171 between the data latches 152 using the master clock signal MCK itself, the remaining skew It is also possible to provide a configuration for synchronizing the imaging data LAOUT including the components. However, in the configuration shown in Fig. 13, the data reacquisition master clock signal MCKD is generated by the phase adjusting unit 28 from the master clock signal MCK, a signal having a phase calculated from the phase of the master clock signal MCK, Is generated as a signal used for finally synchronizing the imaging data LAOUT including the remaining skew components as they are.

In the configuration shown in the figure, the data re-capture clock signal MCKD stores the imaging data LAOUT in the normal F / Fs serving as the data synchronization circuits 172D-0 to 172D-n, n: 0]. Nevertheless, the data re-capture clock signal MCKD is set and used to provide the most optimal timing in accordance with the phase of the data capture clock signal SACKD. Since the phase of the data re-capture clock signal MCKD is calculated based on the phase of the master clock signal MCK, the data re-capture clock signal MCKD does not include the position-dependent component.

Due to the position dependent component of the data capture clock signal SACKD, the set-up and hold-time margins change from column to column. However, since the skew components belonging to three of the four categories have been removed from the image pickup data LAOUT, the configuration in which the data capture clock signal SACK is used for the synchronization processing to simultaneously remove the skew components belonging to all four categories, 13, the configuration shown in Fig. 13 can perform synchronous processing, leaving a margin of proper setup and hold time.

13, the skew component is removed by dividing the four categories of skew components into a first group including a skew component belonging to the first, second and third categories, and a second group being a fourth category.

As described above, the skew component belonging to the first category is caused by a transmission time variation resulting from a so-called manufacturing process variation, and the skew component belonging to the second category is caused by a transmission time delay variation caused by a pattern of transmitted data Lt; / RTI > On the other hand, the third category includes the skew component caused by the noise, while the fourth category includes the physical distance from the data latch 152 to the sense amplifier circuit 171 as a delay variation based on the master clock signal MCK And the skew component caused by the transmission time delay fluctuation resulting from the difference of the transmission time delay. A data capture clock signal SACKD is then used in synchronization processing to remove skew components belonging to the first group, and a data capture clock signal MCKD is used for synchronization processing to remove the skew components belonging to the second group. The configuration shown in Fig. 13 can be referred to as being able to increase the margin of set-up and hold time in the process of capturing the image pickup data LAOUT.

However, in some embodiments described above, the phase adjustment section 22 (strictly speaking, the phase adjustment sections 22, 22A, 27, and 28) has a propagation delay of the master clock signal MCK propagated through the column scanning circuit 13 The phase of the master clock signal MCK is adjusted in the process of adjusting the time delay by considering the propagation delay generated in the column scanning circuit 13. [ The phase adjusting section 22 also supplies the image pickup data from the counter latches 152-0 to 152-n to data driven by the selection signals HSEL0 to HSELn respectively appearing on the selection lines SEL0 to SELn in accordance with the driving clock signal CLK The time delay generated in the operation of transmitting the data to the data output circuits 17-0 to 17-n via the transmission lines 154-0 to 154-n, respectively, is considered. Thus, the imaging data can be captured with high accuracy.

However, the propagation delay generated in the column scanning circuit 13 as the propagation delay of the master clock signal MCK propagated through the column scanning circuit 13 mainly depends on the driving clock propagation line LCLK1 and the data transmission lines 154-0 to 154- 22A, 27, 28) for generating a data capture clock signal SACK by delaying the master clock signal MCK for phase adjustment purposes, while being caused by the wiring load of the phase adjustment unit 22, 22A, 27, 28, ) Depends on the driving power of the transistor. That is, in order to perform an operation of capturing the imaging data with high accuracy, it is necessary to provide a large time margin to the column scanning circuit 13, even if the causes of two time delay irrelevant to each other change.

The following description describes a typical configuration that implements another method of ensuring time margins.

≪ Sixth Configuration Example of Data Transmission System &

15 is a diagram showing a typical configuration of a data transmission system according to the sixth configuration example according to the present embodiment. The data transmission system 30E shown in Fig. 15 is obtained by improving the first configuration of the data transmission system 30 shown in Fig. The data transmission system 30E shown in Fig. 15 has the following differences from the data transmission system 30 shown in Fig. 6 as follows.

First, the data output circuit 17E uses 2F / Fs provided in two different stages. The first F / F provided in the previous step serves as a data synchronization circuit 172E for acquiring the output of the sense amplifier circuit 171 in synchronization with the data capture clock signal SACK. The second F / F provided in the succeeding step is a final data output circuit 178 which outputs the image pickup data captured by the data sync circuit 172E from the sense amplifier circuit 171 in synchronization with the master clock signal MCK It plays a role.

Thus, the data synchronizing circuit 172E can capture (or latch) the imaging data with high accuracy or reliability from the sense amplifier circuit 171 in synchronization with the data capture clock signal SACK, while the final data output circuit 178 can capture Can output the captured data captured by the data synchronization circuit 172E from the sense amplifier circuit 171 in synchronization with the master clock signal MCK. As a result, the phase relation between the data output circuit 17E and the output data processing circuit 20 can be assured.

Next, the drive clock waveguide line LCLK1 serving as a line for propagating the drive clock signal CLK has a wiring load substantially equal to the wiring load of the line LSACK propagating the data capture clock signal SACK. In the configuration shown in Fig. 15, the reference notation RCLK indicates the wiring load of the driving clock propagation line LCLK1, while the reference notation RSACK indicates the wiring load of the data trapping clock propagation line LSACK. As shown in the figure, the wiring load is shown in the form of a circuit using resistors and capacitors, respectively.

That is, in the data transmission system 30E of the sixth configuration example shown in Fig. 15, the driving clock propagation line LCLK1 and the driving clock propagation signal LCLK2 are set so that the elements for delaying the driving clock signal CLK and the elements for delaying the data capturing signal SACK are coincident with each other Is designed to use a data capture clock propagation line LSACK having a wiring load RSACK substantially equal to the wiring load RCLK due to the line LCLK1. Therefore, a determination is made between the scanning operation performed in synchronization with the driving clock signal CLK of the column scanning section 13 and the data capturing (or latching) operation performed in synchronization with the data capture clock signal SACK of the data output section 17 fixed relationship is possible.

A plurality of points of the driving clock propagation line LCLK1 are connected to the gate for driving the shift register 131. [ When receiving the drive clock signal line CLK from the drive clock propagation line LCLK1, the gate connected to the point on the drive clock propagation line LCLK1 serves as another load generated by the drive clock propagation line LCLK1. In the data transmission system 30E of the sixth configuration example shown in Fig. 15, the other gate load generated by the drive clock propagation line LCLK1 is denoted by GCLK.

In the sixth configuration example of the present embodiment, the data trapping clock propagation line LSACK is provided with the data latch clock signal SACK, which is generated by the drive clock propagation line LCLK1 so that the element delaying the data capture clock signal SACK is equal to the element delaying the drive clock signal CLK. A gate load GSACK similar to the load GCLK is provided. Since the element for delaying the driving clock signal CLK is the same as the element for delaying the data catching clock signal SACK, the scan scanning operation performed in synchronization with the driving clock signal CLK in the column scanning section 13, It is possible to establish a definite relationship between the data capture (or latching) operation performed in synchronization with the data capture clock signal SACK within the data capture clock signal SACK.

As described above, the data transmission system 30E of the sixth configuration example shown in Fig. 15 such as the system according to the present embodiment is configured such that the driving clock signal CLK is synchronized with the element for delaying the data capture clock signal SACK, The data capture clock propagation line LSACK having a wiring load RSACK substantially equal to the wiring load RCLK generated by the propagation line LCLK1 and the driving clock propagation line LCLK1 is used. Therefore, a definite relationship is established between the scanning operation performed in synchronization with the driving clock signal CLK in the column scanning section 13 and the data capture (or latching) operation performed in synchronization with the data capture clock signal SACK in the data output section 17 It is possible to construct. As a result, a phase adjusting section is not required, and thus the time delay element of such phase adjusting section can be eliminated. Therefore, a definite relationship is established between the scanning operation performed in synchronization with the driving clock signal CLK in the column scanning section 13 and the data capture (or latching) operation performed in synchronization with the data capture clock signal SACK in the data output section 17 It is possible to construct.

≪ Seventh Configuration Example of Data Transmission System &

Next, the data transmission system 30F of the seventh configuration example according to the present embodiment will be described with reference to Fig. 16 is a diagram showing the data transmission system 30F of the seventh configuration example according to the present embodiment.

In the case of the data transmission system 30F of the seventh configuration example, the data transmission system 30F of the seventh configuration example shown in Fig. 16 is such that the gate load GSACKF generated by the data catching clock transmission line LSACK is transmitted to the data transmission system 30E Of FIG. 15 in that it is smaller than the gate load GSACK generated by the data trapping clock propagation line LSACK of the data capture clock propagation line LSACK of FIG.

The data transfer system 30F is configured to have a gate load GSACKF that is freely adjustable to any value within the range of the upper limit equal to 0 to the gate load GCLK.

Since the wiring load RCLK of the driving clock propagation line LCLK1 and the wiring load RSACK of the data capture clock propagation line LSACK are the same as in the sixth configuration example described above, the timing at which the driving clock signal CLK is input to the shift register 131 And the timing of the image data AMPOUT latched in the data synchronizing circuit 172 in synchronization with the data capture clock signal SACK are different from the difference between the gate load GCLK of the drive clock propagation line LCLK1 and the gate load GSACK of the data capture clock propagation line LSACK Lt; / RTI > Specifically, when compared with the data capture clock signal SACK, the drive clock signal CLK is delayed by a time delay amount corresponding to the difference between the gate load GCLK of the drive clock propagation line LCLK1 and the gate load GSACK of the data capture clock propagation line LSACK.

As described above, in the data transmission system 30E of the sixth configuration example, by the wiring load RCLK of the driving clock propagation line LCLK1 propagating the driving clock signal CLK and by the gate load GLCK of the driving clock transmission line LCLK1 The propagation time delay caused is caused by the wiring load RSACK of the data capture clock propagation line LSACK propagating the data capture clock signal SACK and also coincides with the propagation time delay caused by the gate load GSACK of the data capture clock propagation line LSACK I can not. However, the data transfer system 30F is designed in a seventh configuration in which the gate load GSACKF of the data capture clock propagation line LSACK can be freely adjusted to any value within the range of the upper limit such as 0 to the gate load GLCK as described above . That is, the sum of the wiring load RSACK of the data capture clock propagation line LASCK and the gate load GSACKF of the data capture clock propagation line LSACK can be freely adjusted. Therefore, in the case of the data transmission system 30F of the seventh configuration example, it is caused by the wiring load RCLK of the driving clock transmission line LCLK1 that propagates the driving clock signal CLK, and is caused by the gate load GLCK of the driving clock transmission line LCLK1. Is caused by the wiring load LSACK of the data capture clock propagation line LSACK propagating the data capture clock signal SACK and is also caused by the propagation time delay caused by the gate load GSACKF of the data capture clock propagation line LSACK at all times Match. As a result, the data reading operation performed to read the imaging data from the counter latch 152 to the data transmission line 154 in synchronization with the driving clock signal CLK and the data reading operation performed in the data output circuit 17 in synchronization with the data capture clock signal SACK It is possible to establish a reliable definite relationship between the data capture (latching) operation.

≪ Eighth Configuration Example of Data Transmission System &

Next, the data transmission system 30G of the eighth configuration example according to the present embodiment will be described with reference to Fig. 17 is a diagram showing the data transmission system 30G of the eighth configuration example according to the present embodiment.
The data transmission system 30G of the eighth configuration example shown in Fig. 17 differs from the data transmission system 30G of the eighth configuration example in that the data capture clock transmission line LSACK has no < RTI ID = 0.0 > The data transmission system 30E of the sixth configuration example shown in Fig.

In the case of the data transfer system 30G of the eighth configuration example, the data read operation performed in synchronism with the drive clock signal CLK for transferring the image pickup data from the counter latch 152 to the data transfer line 154 is performed by the data output circuit (Or latching) operation performed in synchronism with the data capture clock signal SACK of the control clock signal LCLK1 and the gate clock signal GCLK generated by the drive clock propagation line LCLK1. The main cause of the time delay of the driving clock signal CLK is the wiring load RCLK while the main cause of the time delay of the data capture clock signal SACK is the wiring load RSACK, so that if one of the time delays increases, the remaining time delay also increases . Therefore, it is possible to maintain the relationship between the phase of the drive clock signal CLK and the phase of the data capture clock signal SACK, even if the time delay state changes due to a cause such as fluctuation due to the wiring manufacturing process. As a result, the margin of the setup time is easily ensured.

A timing chart of the eighth configuration example is shown in Fig. 18 (a) shows a timing chart of the waveform of the master clock signal MCK generated by the master clock generating section 21. [ 18B shows a timing chart of the waveform of the drive clock signal CLK supplied from the data output circuit 17E to the clock supply terminal of the most-selected signal generating unit 131-0. 18C shows a timing chart of the waveform of the drive clock signal CLK supplied from the data output circuit 17E to the clock supply terminal of the selection signal generator 131-n of the latest stage. 18D shows a timing chart of the waveform of the data capture clock signal SACK supplied to the clock supply terminal of the data synchronization circuit 172E. Fig. 18E shows a timing chart of the image pickup data transmitted from the counter latch 152-0 to the data transmission line 154. Fig. Fig. 18F shows a timing chart of the image pickup data transmitted from the counter latch 152-n to the data transmission line 154. Fig. 18 (g) shows a timing chart of the image pickup data output outputted by the data synchronization circuit 172E. 18 (h) is a timing chart of the image pickup data outputted by the final data output circuit 178. In Fig.

As shown in Fig. 18, in the data transmission system 30G of the eighth configuration example, the timing of the data synchronization circuit 172E is controlled with high accuracy to ensure an appropriate timing margin.

≪ Ninth Configuration Example of Data Transmission System &

The data transmission system of the ninth configuration example according to the present embodiment will be described with reference to Fig. Fig. 19 shows a diagram showing a data transmission system 30H of the ninth configuration example.

In the data transmission system 30H of the ninth configuration example, as shown in Fig. 19, the data capture clock propagation line LSACKH is shorter than the drive clock propagation line LCLK1. Therefore, the wiring load RSACKH generated by the data capture clock propagation line LSACKH is smaller than the wiring load RCLK generated by the driving clock propagation line LCLK1. As a result, the time delay in accordance with the data capture clock propagation line LSACKH is shorter than the time delay in accordance with the drive clock propagation line LCLK1. That is, the data scanning operation performed in synchronization with the driving clock signal CLK to read the imaging data from the counter latch 152 to the data transmission line 154 is performed in the data output circuit 17 in synchronization with the data capture clock signal SACKH The data capture operation is undoubtedly more delayed than the delay. Therefore, it is possible to maintain the relationship between the phase of the drive clock signal CLK and the phase of the data capture clock signal SACK. As a result, in the data transmission system 30H of the ninth configuration example, it is possible to ensure a sufficient time delay.

In the data transmission system 30H of the ninth configuration example shown in Fig. 19, similar to the data transmission system 30F of the seventh configuration example already described with reference to Fig. 17, the data capture clock signal It is possible to make the gate load GSACK generated by the data catch propagation line LSACK propagating the SACK smaller than the gate load GCLK generated by the driving clock propagation line LCLK1 propagating the driving clock signal CLK.

Instead of shortening the data capture clock propagation line LSACKH as in the case of the data transmission system 30H of the ninth configuration example, the configuration of another configuration provided as a modified version of the data transmission system 30H of the ninth configuration example shown in Fig. 19 It is the drive charge line LCLK1 that is made longer than the data capture clock propagation line LSACK so as to provide a time delay element related to the data capture clock signal SACK to the drive clock propagation line CLK propagating through the drive clock propagation line LCLK1. As another configuration provided as a modified version of the data transmission system 30H of the ninth configuration example, in order to provide a time delay element related to the data capture clock signal SACK on the driving clock signal line CLK propagated through the driving clock propagation line LCLK1, And the driving clock propagation line LCLK1 is connected to the external gate load GCLKH.

That is, in the ninth configuration, the wiring load RCLK (including the gate load GCLK) generated by the drive clock propagation line LCLK1, the data capture clock signal SACK is set so that the wiring load RCLK and the wiring load RSACK can be freely set, respectively It is possible to change both the generated wiring load RSACK (including the gate load GSACK), or both the wiring load RCLK and the wiring load RSACK. Therefore, it is possible to establish a definite relationship between the phase of the drive clock signal CLK and the data capture clock signal SACK. As a result, in synchronization with the drive clock signal CLK, a data read operation is performed to assert the image pickup data from the counter latch 152 to the data transfer line 154, and a data read operation performed in synchronism with the data capture clock signal SACK, It is possible to establish a reliable definite relationship between the data capture (or latching) operation performed in the memory cell.

As a typical technique for changing the wiring and the gate load generated by the clock transmission line, the sixth to ninth configurations of the above-mentioned data transmission system adjust the length (or arrangement) of the clock transmission line. For example, the gate load GSACK generated by the data capture clock propagation line LSACK is changed. However, it should be noted that the implementation of the present invention is by no means limited to this configuration example. That is, it is possible to apply any other technique to change the wiring and the gate load generated by the clock propagation line.

As described above, in the sixth to ninth configurations of the data transmission system, when it is desired to provide a delay element to the clock signals CLK and SACK to adjust the relationship between the clock signal CLK and the phase of the SACK, the wires LCLK1 and LSACK To increase the load and / or to provide a gate load to the lines LCLK1 and LSACK, the data capture clock propagation line LSACK which propagates the drive clock propagation line LCLK1 and / or the data capture clock signal line SACK propagating the drive clock signal CLK Adjust the length (or placement). As a result, it is possible to set a sufficient timing margin.

In the following description, an operation performed by the solid-state image sensor (or CMOS image sensor) according to the present embodiment will be described with reference to the timing chart shown in Fig. 20 and the block diagram of Fig.

After the first operation of reading data from the unit pixel 111 on the row Hx and transferring the data to the pixel column lines V0, V1, ... is stabilized, the DAC 16 converts the ramp waveform reference voltage RAMP into a step waveform And supplies it to the comparator 151 as a signal having The comparator 151 compares the ramp waveform reference voltage RAMP with the voltage appearing on the pixel line Vx connected to the comparator 151 as the voltage representing the data read from the unit pixel 111 connected to the pixel line Vx.

While the DAC 16 supplies the ramp waveform voltage RAMP as a reference signal having a step waveform to the comparator 151, the counter latch 152 performs a reset counting operation for the first read operation, And the reset data is read out from the pixel 111.

At the initial time, the counter latch 152 is set to a count-down state in which a countdown operation is performed to measure the amount of the reset voltage appearing in the unit pixel 111. [ When the voltage of the ramp waveform reference voltage RAMP becomes equal to the voltage appearing on the pixel heating line Vx connected to the comparator 151 as the voltage representing the data read from the unit pixel 111 connected to the pixel heating line Vx, The output COMPOUTi is inverted, the counter latch 152 stops the count-down operation, and latches the count value indicating the reset component DELTA V of the unit pixel 111. [

When counter latch 152 initiates the count-down operation described above, counter latch 152 typically maintains an initial count value of zero. The initial count value is an arbitrary value of the gradation of the AD conversion performed by the ADC 15A. Therefore, the count value latched at the end of the count-down operation indicates a reset count period proportional to the reset component DELTA V of the unit pixel 111 described above.

Then, the ramp waveform reference voltage RAMP, which indicates the count period after the heat lines V0, V1, ... enters a stable state in which the voltage is output in accordance with the amount of incident light, And is supplied to the comparator 151 as a reference voltage REF having a step waveform that is compared with the voltage appearing on the corresponding hot line.

The counter latch 152 performs a count-up operation this time while the DAC 16 supplies the ramp waveform voltage RAMP to the comparator 151 as a reference voltage having a step waveform. When the ramp waveform reference voltage RAMP representing the counting period becomes equal to the voltage appearing on the corresponding hot line Vx, the output COMPOTi of the comparator 151 is inverted, the counter latch 152 stops the count-up operation, That is, the difference between the reset component? V of the unit pixel 111 and the image pickup data generated in the unit pixel 111 is latched.

The counting result stored in the counter latch 152 is scanned by the column scanning circuit 13 and supplied to the sense amplifier circuit 171 used in the data output circuit 17 via the data transmission line 154 as a digital signal. In this manner, the digital image pickup data is sequentially detected and output by the data output circuit 17. [

As described above, in the solid-state image pickup device provided by the present invention,

A pixel array unit (or image acquisition unit) 11 arranged to form a matrix and each including a plurality of unit pixels used for performing photoelectric conversion processing,

A plurality of data transmission lines 154-0 through 154-n for transmitting the digital data read from the unit pixels,

A plurality of data output sections 17-0 to 154-n each used for detecting digital data transmitted by one of the data transmission lines 154-0 to 154-n and for capturing detected digital data in synchronization with the data capture clock signal SACK, 0 to 17-n)

Each of which is arranged to form a parallel circuit and which is used to hold digital data representing the level of an analog input appearing on the hot line of the pixel array unit 11 and each of which is a data transmission line associated with the held data, A plurality of counter latches 152-0 to 152-n used for transferring data held in the data transmission lines included in the data transmission lines 154-0 to 154-n,

A data capture clock supply unit 22 for supplying the data capture clock signal SACK to the data output units 17-0 to 17-n,

A master clock supply circuit 21 for generating at least a master clock signal MCK,

Generates a selection signal in synchronization with the driving clock signal CLK based on the master clock signal MCK and outputs a selection signal to each of the counter latches 152-0 to 152-n and one of the counter latches 152-0 to 152- And a column scanning unit 13 for outputting a signal for selecting a pixel,

The data transmission lines 154-0 to 154-n are arranged in the direction in which the data counter latches 152-0 to 152-n form parallel circuits, and their respective data output portions 17-0 To 17-n,

The column scanning unit 13,

The data counter latches 152-0 to 152-n are arranged so as to form a parallel circuit, and the master clock signal MCK And outputs the selection signal to the counter latch included in the counter latches 152-0 to 152-n as a counter latch corresponding to the selection signal, respectively A shift register 131 having a plurality of selection signal generating units (or latches) 131-0 to 131n,

A predetermined drive clock transmission line is used which propagates the master clock signal MCK and supplies the master clock signal MCK to each of the selection signal generation units 131-0 to 131-n as the drive clock signal CLK,

The data capture clock supply unit 22 adjusts the phase of the master clock signal MCK to generate the data capture clock signal SACK and uses the data capture clock signal SACK in the data output units 17-0 to 17- N to the data output units 17-0 to 17-n as signals used for capturing the image pickup data from the sense amplifier circuits 171-0 to 171-n.

In the above-described configuration, in the operation of horizontally transferring the image pickup data from the image pickup section 11 to the data output section 17, the position-dependent component caused by the transmission distance of the data can be eliminated. As described above, the position dependent component is one of the data skew components, each of which interferes with efforts to increase the processing speed. Thus, the processing speed of the image sensor can be increased, and / or the size of the image sensor can be further increased.

Further, since the image pickup data can be transmitted through a line similar to a line that propagates a clock signal, the effect of inter-chip and / or inter-wafer process variation can be relatively easily absorbed. Thus, the yield can be improved. Further, since the data capture margin can be increased in the synchronization processing performed in the data synchronization circuit 172, the design work can be further simplified. Therefore, the design period and the number of airflows can be reduced.

The shift register 131 used in the column scanning circuit 13 operates in synchronization with the driving clock signal CLK based on the master clock signal MCK. Typically, the drive clock signal CLK is uniformly distributed in the select signal generators 131-0 to 131-n used in the shift register 131 through the clock tree as shown in Figs. 6 and 8 . Alternatively, the drive clock signal CLK is sequentially supplied to the selection signal generation section 131 and is supplied from the input of the sense amplifier circuits 171-0 to 171-n to the selection signal generation section 131-0 at the farthest end do. It should be noted that the technique employed by the present invention as a technique of distributing the driving clock signal CLK is not limited to the above description.

For example, the drive clock signal CLK divides the propagation of the drive clock signal CLK at approximately the center of the array of select signal generators 131-0 to 131-n, as shown in the configuration of Fig. 21, From the inputs of the amplifier circuits 171-0 to 171-n from the inputs of the most-selected signal generating unit 131-0 and the sense amplifier circuits 171-0 to 171-n, 131-n used in the shift register 131 by starting the distribution from the selection signal generating sections 131-1 to 131-n.

The solid-state image sensor having the above-described effects can be applied as an image sensor to a digital or video camera.

22 shows a typical configuration diagram of a camera system 40 to which a solid-state image pickup device according to an embodiment of the present invention is applied.

22, the camera system 40 uses an imaging device 41, a lens 42, a DRV (driving circuit) 43, and a PRC (signal processing circuit) 44. The image pickup device 41 is the solid-state image pickup device 10 according to the present embodiment. The lens 42 is an optical system for guiding the incident light to the pixel region of the imaging element 41. Typically, the lens 42 is a lens that generates an image on the imaging surface of the imaging element 41 based on the incident light. The driving circuit 43 is a circuit for driving the imaging element 41 and the signal processing circuit 44 is a circuit for processing a signal output by the imaging element 41. [

The driving circuit 43 has a timing generator not shown in the drawing. The timing generator is a circuit that generates various timing signals including a start pulse and a clock pulse for driving a circuit inside the image pickup device 41. [ That is, the driving circuit 43 drives the imaging element 41 by using a predetermined timing signal.

Further, the signal processing circuit 44 performs signal processing such as CDS (Correlated Double Sample) processing on the signal output by the image pickup element 41. The image signal obtained as a result of the processing performed by the signal processing circuit 44 is stored in a storage medium such as a memory. The image information stored in the storage medium can be printed by a printer or the like to generate a hard copy. Further, the image information stored in the storage medium can be displayed as a moving image on a monitor such as an LCD unit.

By applying the solid-state image sensing device 10 to an image sensing device such as a digital still camera as the above-described image sensing device 41, a high-precision camera can be realized.

It should also be understood by those skilled in the art that various changes, combinations, and subcombinations may be made, depending on design requirements and other factors, without departing from the scope of the appended claims or equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a configuration example of a solid-state image pickup device (CMOS image sensor) with a column parallel ADC. Fig.

Fig. 2 is a timing chart for explaining the operation of the solid-state image pickup device of Fig. 1; Fig.

3 is a block diagram showing a configuration example of a solid-state image pickup device (CMOS image sensor) mounted on a column parallel ADC according to an embodiment of the present invention.

Fig. 4 is a diagram showing a more specific configuration example of a data transmission system including a data transmission circuit mounted in the column parallel ADC solid-state image pickup device of Fig. 3; Fig.

5 is a circuit diagram showing a specific example of the drive transistor DRV Tr in the counter latch circuit according to the present embodiment.

6 is a diagram showing a first configuration example of a data transmission system according to the present embodiment;

7 is a timing chart of the data transmission system of Fig. 6; Fig.

8 is a diagram showing a second configuration example of the data transmission system according to the present embodiment;

9 is a timing chart of the data transmission system of Fig. 8; Fig.

FIG. 9A is a timing chart of the waveform of the master clock signal; FIG.

FIG. 9B is a timing chart of the waveform of the drive clock signal furthest from the drive signal. FIG.

FIG. 9C is a timing chart of waveforms of the drive clock signals closest to each other; FIG.

9 (d) shows the waveform of the nearest data capture clock signal.

FIG. 9 (e) is a timing chart of the waveform of the farthest data capture clock signal; FIG.

Fig. 9 (f) is a timing chart of the waveform of the furthest selection signal (or the furthest selection pulse).

Fig. 9 (g) is a timing chart of the waveform of the closest selection signal (or the closest selection pulse). Fig.

9 (h) is a diagram showing a timing chart of the image pickup data transmitted to the data transmission line provided in the uppermost layer.

Fig. 9 (i) is a timing chart of the image pickup data transmitted from the data transmission line to the sense amplifier circuit in the uppermost layer.

Fig. 9 (j) is a timing chart of imaging data transmitted from the data transmission line to the sense amplifier circuit in the lowest layer. Fig.

FIG. 9 (k) is a timing chart of image sensing data output by the data synchronization circuit provided on the uppermost layer. FIG.

9 (1) shows a timing chart of the image pickup data outputted by the data synchronization circuit provided in the lowest layer.

10 is a diagram showing a third configuration example of the data transmission system according to the present embodiment.

Fig. 11 is a diagram specifically showing a third configuration example of the data transmission system of Fig. 10 according to the present embodiment; Fig.

12 is a diagram showing a fourth configuration example of the data transmission system according to the present embodiment;

13 is a diagram showing a fifth configuration example of the data transmission system according to the present embodiment.

14 is a timing chart of the data transmission system of Fig. 13; Fig.

15 is a diagram showing a sixth configuration example of the data transmission system according to the present embodiment;

16 is a diagram showing a seventh configuration example of the data transmission system according to the present embodiment;

17 is a diagram showing an eighth configuration example of the data transmission system according to the present embodiment.

FIG. 18 is a timing chart of the data transmission system of FIG. 17; FIG.

FIG. 18A is a timing chart of the waveform of the master clock signal; FIG.

Fig. 18 (b) is a timing chart of the waveform of the drive clock signal furthest away; Fig.

FIG. 18C is a timing chart of waveforms of the drive clock signals closest to each other; FIG.

FIG. 18D is a timing chart of the waveform of the data capture clock signal; FIG.

18 (e) is a timing chart of the image pickup data outputted from the furthest counter latch; Fig.

18 (f) is a timing chart of the image pickup data outputted from the nearest counter latch; Fig.

FIG. 18G is a timing chart of the image pickup data outputted by the data synchronization circuit. FIG.

FIG. 18 (h) shows a timing chart of the image pickup data outputted by the final data output circuit; FIG.

19 is a diagram showing a ninth configuration example of the data transmission system according to the present embodiment;

FIG. 20 is a timing chart for explaining the operation of the solid-state image pickup device of FIG. 3; FIG.

21 is a view for explaining another example of clock distribution in the column scanning circuit according to the present embodiment;

22 is a diagram showing an example of the configuration of a camera system to which the solid-state image pickup device according to the embodiment of the present invention is applied;

Description of the Related Art

10: Solid-state image pickup device

11: Pixel array part

12: row scanning circuit

13: Thermal scanning circuit

131: Shift register

131-0 to 131-n: latch

14: Timing control circuit

15: ADC group

151: comparator

152, 152C: Asynchronous up / down counter

153: Thermal parallel ADC block

154, 154-0 to 154-n: Data transmission lines

16: DAC

17, 17D, 17E: Data output circuit

171 to 171-n, 171C and 171D: sense amplifier (S / A) circuit

172, 172-0 to 172-n, 172D and 172E:

173-0 to 173-n: first latch

174-0 to 174-n: the second latch

175-0 to 175-n: first switch

176-0 to 176-n: second switch

177-0 to 177-n: Capture circuit

178: Data output circuit

20: Output data processing circuit

21: Clock supply circuit

22, 22A, 27, 28: phase adjustment section

23: Repeater

24-0 to 24-n, 24C: pseudo-clock memory unit

25, 25M, 25P: pseudo clock transmission line

26: Sense amplifier circuit

27:

28:

30, 30A to H: Data transmission system

40: Camera system

41:

42: Lens

43: driving circuit

44: Signal processing circuit

LCLK1: clock supply line

LCLK2: clock minute wiring

LMCK1, LMCK1A: Master clock supply line

LSACK, LSACKH: Clock supply line

LSLD1 to LSLD4: Shield line

LSTRT: Start clock supply line

Claims (22)

A plurality of data transmission lines each used for transmitting data, A plurality of data output sections for detecting the data transmitted by one of the data transmission lines and for capturing the detected data in synchronization with a data acquisition acquire clock signal, Each of which is used to hold data in accordance with an input level and which, in response to the selection signal, is maintained in one data transmission line included in the data transmission line as a data transmission line associated with the held data A plurality of data holding units used for transmitting the data, A data capture clock supply unit configured to supply the data capture clock signal to each of the data output units; A clock supply unit configured to generate at least a master clock signal, And for generating the selection signal in synchronization with the driving clock signal, and for outputting the selection signal to each of the data holding units, / RTI > The data transmission line includes: Wherein the data holding section is arranged in a direction in which the data holding section is arranged to form the parallel circuit, and is connected to each data output section arranged in the same direction, The column scan unit includes: Wherein the data holding unit is arranged in a direction in which the data holding unit is arranged to form the parallel circuit and each of the data holding units is used to generate the selection signal in synchronization with the received driving clock signal, A plurality of selection signal generation units used for outputting to one data holding unit included in the data holding unit, And a drive clock waveguide for propagating the master clock signal and supplying the master clock signal as the drive clock signal to each of the selection signal generators, Wherein the data capture clock supply unit comprises: And supplies the master clock signal or the clock signal having the master clock signal as a reference signal to each of the plurality of data output sections as the capture clock signal. The method according to claim 1, Wherein the driving clock propagation line included in the column scanning unit comprises: Propagates the master clock signal from the input of the data output section to the far-end side (end side farthest) In order from the input of the data output section to the input end of the data output section starting from the selection signal generation section located at the farthest end and ending at the selection signal generation section positioned at the end side closest position And selectively supplies the master clock signal as the drive clock signal to the selection signal generation unit. 3. The method of claim 2, The driving clock waveguide line included in the column scanning unit as a line for selectively supplying the driving clock signal to the selection signal generating unit sequentially selected is wired in the same direction as the data transmission line, A time delay of the driving clock signal that has reached the one of the selection signal generating units of the selection signal generating unit through the driving clock propagation line, Wherein the sum of the delay times of data when propagated from the data line to the input of the data output unit through one of the data transmission lines is constant regardless of the position of the pixel line. 3. The method of claim 2, The driving clock waveguide line included in the column scanning unit as a line for selectively supplying the driving clock signal to the sequentially selected selection signal generating unit is wired in the same direction as the data transmission line, Wherein the data capture clock supply section supplies a drive clock signal propagated through the drive clock propagation line to each of the data output sections as the data capture clock signal. 3. The method of claim 2, Wherein the column scan unit includes a master clock propagation line for propagating the master clock, The master clock propagation line is wired in the same direction as the drive clock propagation line, Wherein the column scanning unit includes a shield line provided between at least the driving clock waveguide and the master clock waveguide, And the shield line is set to a fixed potential. The method according to claim 1, A pseudo data transmission line wired in the same direction as the data transmission line, In response to the selection signal generated in synchronization with the drive clock signal based on the master clock signal, a plurality of pseudo data storage units Further comprising: Wherein the data capture clock supply unit supplies the pseudo data asserted to the pseudo data transmission line to each of the data output units as the data capture clock signal. The method according to claim 6, Wherein the pseudo data stored in the pseudo data storage section is a repetition pattern of 1 and 0 and has a repetition frequency equal to a frequency of data transmitted through the data transmission line. 8. The method of claim 7, Wherein each of the data output units is configured to output, in synchronization with both the level transition rising edge of the pseudo data supplied as the data capture clock signal to the data output unit, the level transition falling edge of the pseudo data, or both the level transition rising and falling edges And a data capturing circuit configured to complementarily capture the data complementarily transmitted to the data output section through the data transmission line. 9. The method of claim 8, Wherein each of the data output units includes a data synchronizing unit configured to re-capture data captured by the data capturing unit in synchronization with a clock signal having the master clock signal as a reference signal. The method according to claim 1, Wherein the data capture clock supply unit has a function of adjusting a phase of a clock signal supplied to the data capture clock supply unit. 3. The method of claim 2, Wherein the data capture clock supply unit comprises: And a data capturing clock waveguide line having the same wiring load as the wiring load by the driving clock waveguide line, And supplies the master clock signal or a clock signal having the master clock signal as a reference signal to the data output section via the data capture clock propagation line as the data capture clock signal. 12. The method of claim 11, Wherein at least one of the wiring load by the data capture clock propagation line and the wiring load by the drive clock propagation line can be changed. As a solid-state imaging device, An imaging section arranged to form a matrix and each including a plurality of pixels used for performing photoelectric conversion processing; A plurality of data transmission lines each used for transmitting data, A plurality of data output sections each used for detecting data transmitted by one of the data transmission lines and for capturing the detected data in synchronization with the data capture clock signal, Each of which is used to hold data in accordance with an input level, each of the data being held in response to a select signal, the data being held as a data transfer line associated with the held data, A plurality of data holding units used for transferring data to the data transmission lines of the data storage unit, A data capture clock supply unit configured to supply the data capture clock signal to each of the data output units; A clock supply unit configured to generate at least a master clock signal, And for generating the selection signal in synchronization with the driving clock signal, and for outputting the selection signal to each of the data holding units, Lt; / RTI > Wherein the data transmission line is arranged in a direction in which the data holding unit is arranged to form the parallel circuit and is also connected to each of the data output units arranged in the same direction, The column scan unit includes: Wherein the data holding unit is arranged in a direction in which the data holding unit is arranged to form the parallel circuit, and each of the data holding units is used to generate the selection signal in synchronization with the received driving clock signal, A plurality of selection signal generation units for outputting the selected data to one data holding unit included in the data holding unit; And a drive clock waveguide for propagating the master clock signal and supplying the master clock signal as the drive clock signal to each of the selection signal generators, Wherein the data capture clock supply unit supplies the master clock signal or a clock signal having the master clock signal as a reference signal to each of the data output units as the data capture clock signal. 14. The method of claim 13, Wherein the driving clock propagation line included in the column scanning section propagates the master clock signal from the input of the data output section to the far- The driving clock propagation line is sequentially selected in the order starting from the selection signal generation unit located at the farthest end side from the input of the data output unit and ending at the selection signal generation unit positioned at the latest end side from the input of the data output unit And selectively supplying the master clock signal as the driving clock signal to the selection signal generation unit, The driving clock propagation line is arranged in the same direction as the data transmission line, And the data capture clock supply unit supplies the drive clock signal as the data capture clock signal to each of the data output units via the drive clock waveguide. 14. The method of claim 13, A pseudo data transmission line arranged in the same direction as the data transmission line, And a plurality of pseudo data storage sections, each of which is used for storing pseudo data output to the pseudo data transmission line in response to a selection signal generated in synchronization with the drive clock signal based on the master clock signal, Further comprising: And the data capture clock supply unit supplies the pseudo data asserted to the pseudo data transmission line to each of the data output units as the data capture clock signal. 14. The method of claim 13, Wherein the data capture clock supply unit comprises: And a data trapping clock waveguide having a wiring load identical to the wiring load of the drive clock waveguide, And supplies the master clock signal or a clock signal having the master clock signal as a reference signal as the data capture clock signal to the data output unit via the data capture clock propagation line. 17. The method of claim 16, Wherein at least one of a wiring load by the data-capturing clock propagation line and a wiring load by the driving clock propagation line can be changed. State image pickup device, An optical system for imaging an image on the solid- A signal processing circuit for processing an image signal output by the solid- Lt; / RTI > The solid- An imaging section arranged to form a matrix and each including a plurality of pixels used for performing photoelectric conversion processing; A plurality of data transmission lines each used for transmitting data, A plurality of data output sections each used for detecting the data transmitted by one of the data transmission lines and for capturing the detected data in synchronization with the data capture clock signal, Each of which is arranged to form a parallel circuit, each used to hold data in accordance with an input level, and in response to a selection signal, each of the data lines, which is held in the data transmission line included in the data transmission line as a data transmission line associated with the held data A plurality of data holding units used for transmitting the data, A data capture clock supply unit configured to supply the data capture clock signal to each of the data output units; A clock supply unit configured to generate at least a master clock signal, And for generating the selection signal in synchronization with the driving clock signal, and for outputting the selection signal to each of the data holding units, Lt; / RTI > Wherein the data transmission line is arranged in a direction in which the data holding unit is arranged to form a parallel circuit and is also connected to each of the data output units arranged in the same direction, The column scan unit includes: Wherein the data holding unit is arranged in a direction in which the data holding unit is arranged to form the parallel circuit and each of the data holding units is used to generate the selection signal in synchronization with the received driving clock signal, A plurality of selection signal generation units used for outputting to the data holding unit included in the data holding unit as a holding unit, And a drive clock waveguide for propagating the master clock signal and supplying the master clock signal as the drive clock signal to each of the selection signal generators, Wherein the data capture clock supply unit supplies the master clock signal or a clock signal having the master clock signal as a reference signal to the data output unit as the data capture clock signal. 19. The method of claim 18, The drive clock propagation line included in the column scan section propagates the master clock signal from the input of the data output section to the far- Wherein the drive clock propagation line is sequentially selected from the input of the output data output unit in the order starting from the selection signal generation unit located at the farthest end and ending at the selection signal generation unit located at the latest end from the input of the data output unit The master clock signal is selectively supplied to the selection signal generation unit as the driving clock signal, The driving clock propagation line is arranged in the same direction as the data transmission line, And the data capture clock supply unit supplies the drive clock signal through the drive clock propagation line to each of the data output units as the data capture clock signal. 19. The method of claim 18, A pseudo data transmission line arranged in the same direction as the data transmission line, And a plurality of pseudo data storage sections, each of which is used to store pseudo data to be output to the pseudo data transmission line in response to the selection signal generated in synchronization with the drive clock signal based on the master clock signal, Further comprising: Wherein the data capture clock supplier supplies the pseudo data asserted on the pseudo data transmission line to each of the data output portions as the data capture clock signal. 19. The method of claim 18, Wherein the data capture clock supply unit comprises: And a data trapping clock waveguide having a wiring load identical to the wiring load of the drive clock waveguide, And supplies the master clock signal or a clock signal having the master clock signal as a reference signal as the data capture clock signal to the data output unit via the data capture clock propagation line. 22. The method of claim 21, Wherein at least one of a wiring load by the data capture clock propagation line and a wiring load by the drive clock propagation line can be changed.

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