JP4953970B2 - Physical quantity detection device and driving method thereof - Google Patents

Description

  The present invention relates to a two-dimensional physical quantity detection device for detecting a physical quantity distribution of particle radiation such as visible light, electromagnetic waves, alpha rays, and beta rays, and more specifically, photoelectric conversion elements arranged in a matrix, etc. The present invention relates to a solid-state imaging device provided with a sensing element and an A / D conversion circuit receiving an output signal from the sensing element, and an imaging system.

  In addition to the CCD (Charge Coupled Device) type sensor (hereinafter referred to as “CCD sensor”), which has been the mainstream as an image sensor, MOS utilizing the standard process used in logic LSIs today. Type image sensors (hereinafter referred to as “MOS sensors”) have become widely available on the market. Unlike the CCD sensor, the MOS sensor has a feature that various analog circuits and digital circuits can be integrated on the same substrate as the pixel array. In CCD sensors, analog front-end processors (hereinafter referred to as AFE) specialized for analog signal amplification functions and A / D conversion functions, and digital signal processing processors (hereinafter referred to as DSPs) equipped with AFE functions are used for A / D conversion. A digital output can be obtained only by connecting a separate chip having a function to the pixel array. On the other hand, a MOS sensor in which an A / D conversion circuit and a pixel array are integrated on the same chip has already been commercialized.

  The A / D conversion circuit mounted on the MOS sensor includes a pipeline type A / D conversion method that is also widely used in AFE, and a column that performs A / D conversion of pixel data for one line simultaneously in parallel. There are various types of proposals including a type A / D conversion method, and a method of performing A / D conversion on all pixel data simultaneously and in parallel. Even if only the column-type A / D conversion method is selected, for example, there are configurations shown in Patent Documents 1 to 3.

  FIG. 16 is a diagram showing a configuration of a MOS sensor according to a first conventional example described in Patent Document 1. In FIG.

  The MOS sensor according to the first conventional example includes a column A / D conversion circuit 1106 configured by a comparator 1107 and a digital memory 1108 for each column of pixels 1101. The binary value output from the binary counter 1104 is input to a D / A conversion circuit (hereinafter referred to as DAC) 1105. The DAC 1105 generates an analog ramp voltage (triangular wave) 1122 corresponding to the input binary value, and outputs the analog ramp voltage 1122 to the comparator 1107 as a reference potential. The output of the binary counter 1104 is also input to a binary → Gray code converter 1115, converted into a Gray code, and then distributed to the digital memory 1108 of each column. A pixel signal is input from the pixel 1101 through the readout signal line 1103 to the other input portion of the comparator 1107 in each column A / D conversion circuit 1106.

  Next, the A / D conversion operation of the MOS sensor according to the first conventional example will be described. First, in synchronization with the clock signal 1121 input from the clock generation circuit 1120, the binary counter 1104 starts counting from its initial value, and at the same time, the DAC 1105 starts generating the analog ramp voltage 1122. Then, a readout signal from the pixel 1101 in each column and a common analog ramp voltage 1122 that changes in synchronization with the count value of the binary counter 1104 are input to the comparator 1107 in each column. In parallel with this, the count value of the binary counter 1104 is converted into the gray code count value 1124 by the binary → Gray code converter 1115 and distributed to the digital memory 1108. When the magnitude relationship between the two input signals to the comparator 1107 in a certain column is switched, the output signal of the comparator 1107 is inverted, and the digital memory 1108 in that column stores the gray code meter output from the binary → Gray code converter 1115. The numerical value 1124 is held. Since the analog ramp voltage 1122 input to the comparator 1107 and the gray code count value 1124 input to the digital memory 1108 are synchronized with each other via the binary counter 1104, the readout signal (( Analog signal) is A / D converted into a value (digital signal) held in the digital memory.

  As described above, in the MOS sensor according to the first conventional example disclosed in Patent Document 1, the gray code is used as a method for expressing the digital value supplied to the digital memory. As a result, the Gray code count value 1124 always transitions with a minimum Hamming distance of “1”, so that even if there is a skew between the bits distributed as the clock, the sampling error can be reduced. Further, in the Gray code, only one bit among all the bits is inverted in the preceding and following count values, so noise is suppressed. In addition, power consumption can be reduced.

  FIG. 17 is a diagram showing a configuration of a MOS sensor according to a second conventional example described in Patent Document 2 and Patent Document 3. In FIG. The configuration of the MOS sensor according to the second conventional example including another column type A / D conversion circuit will be described with reference to FIG.

  The MOS sensor according to the second conventional example includes a column A / D conversion circuit 1106 configured by a comparator 1107 and a column counter 1208 for each column of the pixels 1101. The clock generation circuit 1120 supplies the clock signal 1121 not only to the binary counter 1104 but also to the column counter 1208 in the column A / D conversion circuit 1106. The binary value output from the binary counter 1104 is input to a D / A conversion circuit (DAC) 1105, and the DAC 1105 generates an analog ramp voltage (triangular wave) 1122 according to the input binary value. The analog ramp voltage 1122 is input to the comparator 1107 as a reference potential. A pixel signal is input from the pixel 1101 through the readout signal line 1103 to the other input of the comparator 1107.

  In the MOS sensor according to the second conventional example shown in FIG. 17, the only signal supplied to the column A / D conversion circuit array is the clock signal 1121 generated by the clock generation circuit 1120.

  Next, the A / D conversion operation of the MOS sensor according to the second conventional example will be described.

  First, the column counter 1208 and the binary counter 1104 in the column A / D conversion circuit 1106 are initialized by an initialization signal (not shown), and the initial value of the analog ramp voltage 1122 is input from the DAC 1105 to one input unit of the comparator 1107. Keep supplying. Next, a pixel signal is read from the pixels 1101 in the selected row and supplied to the other input portion of the comparator 1107. In this state, by starting input of the clock signal 1121 to the binary counter 1104 and the column counter 1208, the binary counter 1104 starts counting from its initial value. Then, the DAC 1105 also starts generating the analog ramp voltage 1122 from the initial value according to the count value of the binary counter 1104. The column counter 1208 in the column A / D conversion circuit 1106 also starts counting the input clock signal 1121.

  Next, when the magnitude relationship between the two signals input to the comparator 1107 in a certain column is switched and the output signal of the comparator 1107 is inverted, the clock signal 1121 input to the column counter 1208 in that column is masked, and the column The counter 1208 holds the count value at that time. Since the analog ramp voltage 1122 and the count value of the column counter 1208 are synchronized with each other by the clock signal 1121, the value (digital signal) in which the readout signal (analog signal) from the pixel is held in the digital memory by the above operation. A / D conversion is performed.

  The two A / D conversion methods described above are of a type called a ramp type A / D conversion (Ramp Run-up ADC) among column A / D conversion methods, and are generally used for A / D conversion. According to the classification, all are of a kind called counting ADC (counting A / D conversion). Using a triangular wave as a reference potential is equivalent to converting an analog signal potential from a pixel into a length of time, and A / D conversion is performed by measuring the length of time using a fixed frequency clock signal. There is this name to realize.

  For example, in the case of 10-bit A / D conversion, when comparing a signal from a pixel with a reference potential (analog ramp voltage) generated by a DAC, it is necessary to count the number of gradations of 10 bits (that is, 1024 times). There is. If there is only one signal from the pixel, A / D conversion is completed at the stage where the magnitude relationship between the signal potential and the reference potential is inverted, and the subsequent comparison operation becomes unnecessary, but it is mounted on the MOS type sensor. As in the case, for example, when A / D conversion is performed on pixels for one row in parallel, it is not possible to confirm whether conversion has been completed for all the pixels with a normal configuration. Necessary.

  Here, consider a mobile phone camera as an example of a specific product. The number of Mega class pixels has become common even in mobile phones. For example, specifications of 5 million pixels and a frame rate of 15 frames / sec are required.

For ease of explanation, assuming that the aspect ratio of a pixel array of 5 million pixels is 2000 rows × 2500 columns and there is no blanking period for further simplification, the readout period of one row is
15frame / sec × 2000 lines / frame = 30Kline / sec
It becomes. That is, the readout rate for one row is 30 KHz.

When "lamp type A / D conversion" is applied to this product, if it is 10 bit A / D conversion, it is necessary to compare the number of gradations 2 ¹⁰ = 1024 times during the readout time of one row. It is necessary to change the count value of the counter to be output to the digital memory at about 1000 times the read rate and about 30 MHz.

In this calculation, a standby period until the A / D conversion circuit receives data from the pixel and a transfer period of the A / D conversion result to the output memory, that is, a period during which comparison operation as A / D conversion cannot be performed are taken into consideration. In addition, since the OB (Optical Black) pixel period and the blanking period are excluded in addition to the number of pixels, the frequency actually becomes higher than the estimated frequency (for example, about 50 MHz).
Japanese Patent Laying-Open No. 2005-347931 (FIG. 2) USP 5,877,715 JP 2005-323331 A

  Not only the ramp type A / D conversion but also the column type A / D conversion in which pixels for one row are converted simultaneously, the A / D conversion rate is determined by the following equation.

Conversion rate = (frame rate) x (number of lines in one frame)
Here, the “number of rows in one frame” includes not only a period for reading an effective pixel but also a period for reading a signal from an OB pixel and a blanking period.

  Although the number of rows in one frame corresponds to approximately the square root of the number of pixels, it is well known that the number of pixels in the field of digital still cameras (DSC) has increased dramatically in recent years. In addition, DSC has a growing need for moving image shooting, and the number of pixels and the frame rate tend to increase. Therefore, it can be said from the above formula that the conversion rate of the column type A / D conversion tends to increase.

  Now, the number of comparisons per unit time in a column-type and count-type A / D conversion circuit such as a ramp-type A / D conversion circuit (that is, the number of changes in the counter value distributed to the digital memory, hereinafter referred to as comparison frequency). ) Has the following relationship with the number of gradations of A / D conversion and the conversion rate.

Comparison frequency = (number of gradations) / [{1 / (conversion rate)} − υ]
Number of gradations = 2 ^{(conversion bit width)}
Here, υ is a period during which comparison operation as A / D conversion is not possible. When υ is approximated to zero, simply comparison frequency = (number of gradations) x (conversion rate)
It becomes. That is, it can be seen that the ramp type A / D conversion circuit has a feature that the comparison frequency for conversion is doubled only by increasing the conversion bit width by one bit.

  For example, the influence on the comparison frequency of A / D conversion in the image sensor of 5 million pixels described above is that the 10-bit A / D conversion bit width is increased to 11 bits, and 5 million pixels is quadrupled 20 million pixels. It can be seen that this is the same as when the number is increased.

  However, from the viewpoint of improving the image quality, the conversion accuracy of A / D conversion is also required, and there is a potential need of 14 bits or 16 bits as a bit width.

  When the bit width of A / D conversion is 14 bits, the frequency of the counter output to the digital memory of 5 million pixels described above is 800 MHz which is 16 times the bit width of 10 bits, and in the case of 16 bits, the bit width Is 3.2 GHz, which is 64 times that of 10 bits, which causes a problem in the distribution of the counter count value signal to the digital memory unit.

Specifically, the following problems occur.
(1) Even in a chip, it is extremely difficult to generate a clock in the GHz order.
(2) Even if a clock can be generated, a circuit for the number of pixels in one row becomes a wiring load, and the wiring is long and the parasitic RC is large, so that it is difficult to drive correctly in the entire area of the digital memory. is there.
(3) Although measures such as enhancement of the clock driver capability, driving from both sides of the digital memory, and insertion of a repeater can be considered, even if a drive waveform capable of operating is managed, the power consumption increases significantly. Therefore, it is not appropriate as a solution. In addition, when one repeater is inserted for each of a plurality of columns, there is a concern that noise in that cycle is generated in the image. In addition, repeaters are added to all the columns. In addition to further increase in power consumption and chip area, there is a concern that the delay of the clock due to the repeater becomes large and the original operation of the ramp type A / D converter circuit cannot be performed. .

  In the following, the problem (2) above will be described in detail. Normally, one lamp type A / D conversion circuit is provided for one column or a plurality of pixel columns. Therefore, for example, when a ramp-type A / D conversion circuit is provided for each column, the clock signal to be supplied to each bit of the digital memory is equivalent to the number of pixels in one row (2,500 columns in the case of 5 million pixels described above). Digital memory is the load. Although the length of the wiring depends not only on the number of pixels but also on the size of the pixel, an image sensor called a large format has an imaging surface equivalent to a 35 mm film size. Therefore, the parasitic RC is also considerably large.

  FIG. 18A is a diagram schematically showing the relationship between the clock signal supplied to the digital memory of the MOS sensor of the same type as the first conventional example shown in FIG. 16 and the position of the digital memory, for example. ) Is a diagram showing clock waveforms at point A and point C in (a) when the clock frequency is f, and (c) is point A and point A in (a) when the clock frequency is 2f. FIG. 6 is a diagram showing a clock waveform at a point C. Note that the MOS sensor shown here is not provided with the binary → Gray code converter 1115.

  As shown in FIG. 18A, the clock waveform becomes dull due to the parasitic RC component as it moves away from the clock generation circuit 1120 (or binary → Gray code converter 1115) from point A, point B, and point C. In such a case, as shown in FIGS. 18 (b) and 18 (c), there is no problem at point A at any frequency, but at point C, the RC load increases, so both the rise time and fall time are large. Extend. For this reason, especially at the frequency 2f, the clock signal cannot fully swing, and the signal amplitude is small. Thus, as the frequency is increased in order to increase the conversion accuracy, there is a higher possibility that a problem occurs in the A / D conversion operation in a column having a long distance from the clock signal supply source.

  In the first conventional example shown in FIG. 16, the least significant bit is represented by a Gray code representation, and the other bits are represented by a binary representation, so that the switching rate (frequency) required compared to the case where only the binary representation is used. Can be halved.

  However, with this alone, the clock frequency at 14 bits is only 400 MHz and the frequency at 16 bits is 1.6 GHz, and the difficulty is somewhat lowered, but the above three problems remain.

  An object of the present invention is to provide a solid-state imaging device capable of high-speed and high-speed processing even when the number of pixels, the frame rate, the conversion bit width, and the like are increased.

  In order to solve the above problems, the inventors of the present application have made various studies, provided a latch in each A / D conversion circuit, and converted the clock signal or the clock signal into a gray code or a phase shift code in the latch. It was conceived that the lower bits of the A / D conversion value were expressed by holding the value of the A / D conversion value. As a result, the bit width of the A / D conversion value can be increased without increasing the maximum frequency of the clock signal and without changing the conversion time. Alternatively, when the bit width of the A / D conversion value is not increased, the maximum frequency of the clock signal can be lowered. In particular, when the value held in the latch is expressed as a Gray code expression or a phase shift code expression, the Hamming distance can always be set to the minimum 1, and even if there is a skew between bits, the influence of the sampling error is minimized. Can be suppressed. In addition, since the change in current consumption due to the count value is small, the generation of noise can be suppressed, and the power consumption can be reduced as compared with the case where binary code is used. In particular, if the phase shift code is used, the bit accuracy can be improved when the frequency of the clock signal is the same as the processing time.

  That is, the physical quantity detection device of the present invention is provided with a sensitive element array in which sensitive elements for detecting a physical quantity are arranged in a matrix, and one or more rows of the sensitive elements, and the sensitive elements in each row. A column A / D conversion circuit for converting a signal output from the digital signal into a digital signal, an output signal bus for transmitting a digital signal output from the column A / D conversion circuit in each column, and the column A / D A physical quantity detection device comprising a clock generation circuit that supplies a counter clock signal and a latch clock signal to a conversion circuit, and a D / A converter that outputs a triangular wave, wherein each column A / D conversion circuit includes: A comparator that compares the signal output from the sensitive element and the potential of the triangular wave during a predetermined period, and counts the pulses of the counter clock signal; A column counter that holds a count value at the time when the output of the comparator changes, and a latch clock signal that receives the latch clock signal and holds the value of the latch clock signal at the time when the output from the comparator changes 1 The digital signal having a size corresponding to an A / D conversion value expressed by combining a count value of the column counter and a value held by the latch is provided to the output signal bus. Output.

  With this configuration, a part of bits (particularly, lower bits) of the A / D conversion value can be held in the latch. Thereby, the maximum frequency of the counter clock signal supplied to the column counter can be reduced. Further, when the processing time is the same at the same frequency, the bit accuracy can be greatly improved as compared with the conventional physical quantity detection device. The latch clock signal held in the latch may be expressed by a binary code, a gray code, a phase shift code, or the like, but it is particularly preferable to use a gray code or a phase shift code. Among these, the use of a phase shift code is more preferable because it can greatly improve the bit accuracy of A / D conversion without changing the frequencies of the counter clock signal and the latch clock signal.

  Further, the driving method of the physical quantity detection device of the present invention is provided with a sensitive element array in which sensitive elements for detecting a physical quantity are arranged in a matrix, and for each of the sensitive elements, or for each of a plurality of lines, and each of them is compared. A column A / D conversion circuit for converting a signal output from the sensitive element of each column into a digital signal, and a column A / D conversion circuit having a counter, a column counter, and one or a plurality of latches; An output signal bus for transmitting a digital signal output from the column A / D conversion circuit, a clock generation circuit for supplying a counter clock signal and s latch clock signals to the column A / D conversion circuit, and a triangular wave A D / A converter that outputs a D / A converter, wherein the comparator has a signal potential read from the sensitive element and a potential of the triangular wave in a predetermined period. A comparison step (a), a step (b) in which the column counter counts pulses of the counter clock signal from the start of comparison by the comparator, and a step from the comparator after the step (b). The counter clock signal input to the column counter at the time when the output changes is masked, and the step (c) for holding the count value of the counter unit, and after the step (b), from the comparator The latch holds the potential of each of the s latch clock signals at the time when the output changes, and the value held by the latch in the step (d) is the lower m bits, Based on the value expressed in combination with the count value of the column counter held in step (c), a digital signal of a predetermined voltage is applied to the column. / D conversion circuit and a step (e) to be output to the output signal bus.

  According to this method, the count value held in the column counter and the value of the latch clock signal held in the latch (or the latch clock signal converted into a phase shift code, gray code, etc.) are combined to provide a sensitive element. Since the A / D conversion of the signal read from the A / D converter is performed, the frequency of the clock signal can be reduced while maintaining the bit accuracy of the A / D conversion. In addition, the bit accuracy can be improved while maintaining the frequency of the clock signal at a predetermined value.

  By providing a latch that holds the lower bits of A / D conversion in each of the column A / D conversion circuits of the ramp wave reference method, the same A / D conversion time can be obtained without increasing the frequency of the counter clock signal. It becomes possible to improve the resolution of A / D conversion.

  Thereby, even when the conversion bit width and the number of pixels are increased for improving the image quality, or when the frame rate is increased for increasing the speed, it is possible to suppress the occurrence of problems due to the waveform rounding of the counter clock signal.

  Hereinafter, a two-dimensional array type MOS sensor will be described as each embodiment of the present invention with reference to the drawings. However, this is merely an example, and the configuration or driving method according to the present invention includes a plurality of unit components that are sensitive to electromagnetic waves input from the outside, such as light and radiation, arranged in a line or a matrix. The present invention is widely applicable to semiconductor devices for physical quantity distribution detection.

  Hereinafter, in the solid-state imaging devices according to the first and second embodiments, a so-called CDS (correlated double sampling) operation in which the reset level read from the pixel is subtracted as an offset from the signal level read from the pixel as S / H ( Usually, it is performed in the analog region using a sample hold capacitor, etc., but since it is not directly related to the point of the present invention, it is omitted for the sake of simplicity.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a solid-state imaging device (MOS sensor) according to the first embodiment of the present invention.

  As shown in the figure, the MOS sensor of this embodiment includes a pixel array (sensitive element array) 102 in which pixels (sensitive elements) 101 are arranged in a matrix, and one column or a plurality of columns of pixels 101. A column A / D conversion circuit 106 that is provided and converts a signal output from the pixel 101 into a digital signal, and a column scanning unit that performs output control of the digital signal converted and held by the column A / D conversion circuit 106 (Not shown), output signal buses 126 and 127 for transmitting digital signals output from the column A / D conversion circuit 106, and a clock generation circuit for supplying clock signals (counter clock signal and latch clock signal) 120, a binary counter 104, a D / A conversion circuit (DAC; reference potential generation circuit) 105, and output signal buses 126, 127 at input portions. And an output buffer 109 connected. Here, a pixel includes at least a photosensitive element such as a photodiode or a photogate, and a device structure for reading a signal generated by photoelectric conversion and a structure that enables an initialization operation are provided as necessary. It is a unit element. FIG. 1 shows an example in which a column A / D conversion circuit 106 is provided for each column.

  Each column A / D conversion circuit 106 includes a comparator 107, a latch 308, and a column counter 208.

  The clock generation circuit 120 supplies the clock signal 121 to the binary counter 104, the column counter 208, and the latch 308. The binary counter 104 supplies a binary value to the DAC 105, and the DAC 105 generates an analog ramp voltage (triangular wave) 122 according to the input binary value. The analog ramp voltage 122 is input to the comparator 107 as a reference potential. A pixel signal read from the pixel 101 via the read signal line 103 is input to the other input of the comparator 107, and an output from the comparator 107 is input to the column counter 208 and the latch 308.

  The MOS sensor of this embodiment is the same as the MOS sensor shown in FIG. 17 in that a column counter 208 is provided in the column A / D conversion circuit 106. However, it receives a signal output from the comparator 107 and receives a digital signal. The mechanism for determining the value is different from the conventional MOS sensor in that a latch 308 is provided in addition to the column counter 208.

  Next, an A / D conversion operation in the MOS sensor of this embodiment will be described.

  First, the column counter 208 and the binary counter 104 in the column A / D conversion circuit 106 are initialized by an initialization signal (not shown), and the initial value of the analog ramp voltage 122 is supplied from the DAC 105 to one input unit of the comparator 107. Keep supplying. Next, a pixel signal is read from the pixels 101 in the selected row, and the pixel signal is supplied to the other input unit of the comparator 107. In this state, when the input of the clock signal 121 from the clock generation circuit 120 is started, the binary counter 104 starts counting from the initial value. Then, the DAC 105 also starts generating the analog ramp voltage 122 from its initial value according to the count value of the binary counter 104. At the same time, the column counter 208 in the column A / D conversion circuit 106 also starts counting the input clock signal (counter clock signal) 121.

  Next, when the magnitude relationship between the two signals input to the comparator 107 in a certain column is switched, the comparator output signal 123 is inverted. Then, the clock signal (counter clock signal) 121 input to the column counter 208 of the column is masked, and at the same time, the column counter 208 stops counting and the column counter 208 holds the count value. Similarly, by the inversion of the comparator output signal 123, the latch 308 holds the clock signal (latch clock signal) 121 as data at the same timing as the counting stop of the column counter 208. Since the analog ramp voltage 122 and the count value of the column counter 208 are synchronized by the clock signal 121, the value (the analog signal) read out from the pixel 101 is held in the column counter 208 and the latch 308 by the above operation ( A / D conversion into a digital signal). The A / D conversion operation described above is performed in parallel for all pixel signals except for the difference in inversion timing of the comparator output signal 123 for each column. After the binary counter 104 finishes counting a predetermined bit width, an output from the latch 308 and an output from the column counter 208 are simultaneously read for each column by a column scanning unit (not shown), and the output buffer 109 An A / D conversion value is output.

  Next, the effect obtained by adding the latch 308 in the column A / D conversion circuit 106 will be described with reference to FIG. FIG. 2A is a diagram showing operation waveforms in the column A / D conversion circuit of the MOS sensor according to the second conventional example, and FIG. 2B is a diagram in the A / D conversion circuit of the MOS sensor of this embodiment. It is a figure which shows an operation | movement waveform. Note that the comparators 107 and 1107 in each column simultaneously compare the pixel signals in the respective columns. In FIGS. 2A and 2B, for reference, the column counter in a specific column in which the comparator output signal is inverted. And the value held by the latch is shown as a solid line as it is, and the change of the value in the non-inverted column is shown as a broken line.

  In the following description, the bit width of the column counter 208 is k bits, the count value is Count [k-1: 0], and the value held and output by the latch 308 is expressed as Latch [0]. FIG. 2B also shows the waveforms of the clock signal 121 and the comparator output signal 123. As the column counter 208, for example, a configuration in which the value changes at the falling edge of the clock signal 121 is assumed. As for the comparator output signal 123, the signal before the magnitude relationship between the pixel signal and the analog ramp voltage 122 is inverted is H, and the signal after the inversion is L.

  As shown in FIG. 2A, in the MOS sensor according to the second conventional example, the count value of the column counter after the time when the comparator output signal is inverted represents the digital value of the A / D conversion result, It can be seen that Count [3: 0] has a binary result of “1010” (see the circled portion attached to FIG. 2A). Note that the upper bits of 5 bits (bit 4) or more from the bottom are not shown.

  On the other hand, as shown in FIG. 2B, also in the MOS sensor of this embodiment, the count value of the column counter 208 and the output value (holding value) of the latch 308 after the time when the comparator output signal 123 is inverted are A / Represents the digital value of the D conversion result. However, unlike the conventional MOS sensor, Latch [0] = 1 is obtained in addition to the same value of Count [3: 0]. When compared at the same frequency and the same time, the MOS sensor of this embodiment It can be seen that the accuracy on the lower bit side can be improved without increasing the clock frequency. Although the value of the least significant bit varies more rapidly than the most significant bit, the MOS sensor of this embodiment can improve the accuracy of the least significant bit, so even if the number of pixels or the frame rate is increased, the A / D conversion operation is defective. Does not occur and deterioration of image quality can be suppressed. When the least significant bit is expressed only by the output of the latch 308, the maximum frequency of the signal supplied to the column counter is half the maximum frequency in the MOS sensor of the second conventional example, and the bit width of the A / D conversion. Can be increased.

  In the first place, the maximum frequency of data that can be obtained as an A / D conversion result by the conventional column counter method is only half the frequency of the clock signal supplied to the column counter. However, according to the MOS sensor of this embodiment, the clock signal is handled as data as it is and supplied to the latch 308, so that the resolution can be improved without increasing the time required for A / D conversion.

  Here, let us consider a case where the count value of the column counter 208 changes at the rising edge of the clock signal 121.

  FIG. 3A is a diagram showing operation waveforms in the column A / D conversion circuit of the MOS sensor according to the second conventional example, and FIG. 3B is a column A / D conversion circuit of the MOS sensor of this embodiment. It is a figure which shows the operation | movement waveform in.

  In the MOS sensor according to the second conventional example, as can be seen from the comparison between FIG. 3A and FIG. 2A, the count value changes at the rising edge and the falling edge of the clock signal. In the case of changing, only the clock signal is inverted, and there is no influence on the A / D conversion result.

  On the other hand, in the MOS sensor of this embodiment, as can be seen from the comparison between FIG. 3B and FIG. 2B, the count value changes at the rising edge of the clock signal and the count value at the falling edge. Is changed, not only the clock signal is inverted, but also the data of Latch [0] is inverted. Therefore, when the column counter 208 changes at the rising edge of the clock signal 121, 1/0 of the least significant bit of the A / D conversion result is reversed from the previous case. Therefore, in this case, as shown in FIG. 4, the configuration of the MOS sensor of this embodiment may be changed.

  FIG. 4 is a diagram showing a modification of the MOS sensor of this embodiment. The MOS sensor of the present modification has the same configuration as the MOS sensor of the present embodiment shown in FIG. 1 except that the inverter 119 indicated by a broken line is inserted into one of the locations.

  As shown in FIG. 4, an inverter 119 may be provided between the clock generation circuit 120 and the latch 308 in order to prevent the value indicating the least significant bit from being inverted. As a result, a signal (inverted clock signal 141) obtained by inverting the clock signal 121 is input to the latch 308, so that the inversion of the least significant bit can be eliminated.

  Alternatively, even if the inverter 119 is inserted on the output signal bus 127 that is a signal reading path from the latch 308, the inversion of the least significant bit can be eliminated. Thus, since the clock signal supplied to the column counter 208 and the clock signal supplied to the latch can be shared, the number of signal lines for supplying the clock signal to the latch can be reduced. In either case, since only one inverter is added to all the columns, the increase in the area is small and the manufacture is easy.

  Since all the structures shown in FIG. 1 can be formed on the same semiconductor substrate, the number of components is reduced compared to a CCD sensor that performs A / D conversion outside the solid-state imaging device, and the imaging device ( The size of the camera set etc. can be reduced.

(Second Embodiment)
FIG. 5 is a diagram showing a configuration of a MOS sensor according to the second embodiment of the present invention. In the figure, the description of the circuits and members having the same functions and configurations as those of the MOS sensor of the first embodiment shown in FIG. 1 is omitted or simplified.

As shown in FIG. 5, the MOS sensor of this embodiment has the same connection from the pixel array 102 to the comparator 107 as the MOS sensor of the first embodiment. However, each column A / D conversion circuit 106 is different from the column A / D conversion circuit of the first embodiment in that it includes a 2 ^m−1 bit latch 408 in addition to the comparator 107 and the column counter 208. Is different. The column A / D conversion circuit 106 is provided for each column in the example shown in FIG.

In addition, the MOS sensor of the present embodiment has a π / 2 ^m−1 phase shift code generation circuit 112 that receives the clock signal 121 and an output signal bus 128 that transmits an output signal from the 2 ^m−1 bit latch 408. And a phase shift code / binary converter 113 provided. The π / 2 ^m-1 phase shift code generation circuit 112 outputs m clock signals (latch clock signals) whose phases are shifted by π / 2 ^m-1 .

The clock generation circuit 120 supplies the clock signal 121 to the binary counter 104 and also supplies it to the column counter 208 and the 2 ^m−1 bit latch 408 in the column A / D conversion circuit 106.

The binary value output from the binary counter 104 is input to the DAC 105, and the DAC 105 generates an analog ramp voltage (triangular wave) 122 according to the input binary value. The analog ramp voltage 122 is input to the input unit of the comparator 107 as a reference potential. A pixel signal read from the pixel 101 via the read signal line 103 is input to the other input unit of the comparator 107. The output from the comparator 107 is input to the column counter 208 and the 2 ^m−1 bit latch 408.

As described above, characteristics of the MOS sensor of this embodiment includes a 2 ^m-1 bit latch 408 converted value to the phase shift code is entered, the output signal from the 2 ^m-1 bit latches 408 And a phase shift code / binary converter 113 for returning to a binary value. In this specification, the “phase shift code” is a binary number in which only one bit changes when the value increases or decreases by one, and one bit from the lower bit to the upper bit as the value increases. It means a code that changes sequentially. That is, in the phase shift code when the bit width is P, “all bits zero” → “only the least significant bit is 1” → “only the lower 2 bits are 11”,. Then, only the least significant bit is 0, the lower 2 bits are 00, and 0 is sequentially increased. Therefore, a total of 2P distinctions can be made with the phase shift code. For example, the phase shift code expression when P = 4 is as follows.

0: 0000
1: 0001
2: 0011
3: 0111
4: 1111
5: 1110
6: 1100
7: 1000
8: 0000
FIG. 6 is a waveform diagram when the lower 4 bits of the A / D conversion value are replaced with the phase shift code in the MOS sensor according to the second embodiment. As can be seen from the figure, the π / 2 ^m−1 phase shift code generation circuit 112 has a frequency that is the same as that of the clock signal 121 and outputs a signal shifted in phase by π / 2 ^m−1 by 2 ^m−1 bits. Each is supplied to a latch 408. FIG. 6 shows an example in which the lower 4 bits are expressed by a shift code. In this case, the 2 ^m-1 bit latch 408 is composed of at least 2 ^4-1 = 8 latches.

  Next, the A / D conversion operation of the MOS sensor according to this embodiment will be described.

First, the column counter 208, the binary counter 104, and the π / 2 ^m-1 phase shift code generation circuit 112 in the column A / D conversion circuit 106 are initialized with an initialization signal (not shown) in advance, and the analog ramp is output from the DAC 105. An initial value of the voltage 122 is supplied to one input unit of the comparator 107. Next, a pixel signal is read from the pixels 101 in the selected row, and the pixel signal is supplied to the other input unit of the comparator 107. In this state, when the input of the clock signal 121 from the clock generation circuit 120 is started, the binary counter 104 starts counting from the initial value. Then, the DAC 105 also starts generating the analog ramp voltage 122 from the initial value according to the count value of the binary counter 104. At the same time as the supply of the clock signal (counter clock signal) 121 starts, the column counter 208 in the column A / D conversion circuit 106 also starts counting the clock signal 121. At the same time, the π / 2 ^m-1 phase shift code generation circuit 112 also starts generating a phase shift code.

Thereafter, when the magnitude relationship between the two input signals to the comparator 107 in a certain column is switched, the comparator output signal 123 of the comparator 107 is inverted. Then, the clock signal 121 to the column counter 208 of the column is masked, and at the same time, the column counter 208 stops counting and the column counter 208 holds the count value. Similarly, by the inversion of the comparator output signal 123, the 2 ^m−1 bit latch 408 holds the phase shift code 125 as data at the same timing as the counting of the column counter 208 is stopped. Since the analog ramp voltage 122, the column counter 208, and the count values of the π / 2 ^m-1 phase shift code generation circuit 112 and the like are synchronized with each other by the clock signal 121, the readout signal (analogue) from the pixel 101 is obtained by the above operation. Signal) is A / D converted into a value (digital signal) held in the column counter 208 and the 2 ^m−1 bit latch 408.

As shown in FIG. 6, the higher-order bits excluding the bits replaced with the phase shift code are counted by the column counter 208. The column counter 208 uses the output signal of the π / 2 ^m−1 phase shift code generation circuit 112 and It can be seen that driving with clock signals of the same frequency is sufficient. Therefore, according to the MOS sensor of this embodiment, the lower 2 ^m−1 bits are replaced with the shift code and held in the latch in the column A / D conversion circuit 106, so that the A / D conversion bit width can be reduced. When the same as that of the MOS sensor, the clock frequency can be ½ ^m−1 (1/16 in the example of FIG. 6). On the contrary, when the same clock frequency as that of the conventional MOS sensor is applied, the bit accuracy can be increased by 2 ^m−1 (4 bits in the example of FIG. 6).

  This is because, for example, a clock frequency of 800 MHz is necessary for the conventional MOS sensor, but 50 MHz is sufficient for the MOS sensor of this embodiment, and there is a problem due to rounding of the signal waveform in the column counter 208 arranged in an array. In addition to being greatly relaxed, a configuration in which the clock generation circuit 120 does not have a frequency multiplication function is possible. Further, when the digital memory 108 that is arranged in an array and stores the A / D conversion values of each column is provided, it is possible to suppress the occurrence of problems due to the rounding of the signal waveform. In the example of this embodiment, it is necessary to generate a signal in which the phase of the 50 MHz clock signal is shifted by 22.5 degrees. For this purpose, a DLL (Delay Locked Loop) circuit may be mounted.

  In addition, since the phase shift code always changes only 1 bit when the value changes by 1, the change in the output voltage from the column A / D conversion circuit 106 can be made uniform and the signal reading error can be reduced. can do. In addition, power consumption can be reduced as compared with the case of using binary code.

  In the MOS sensor of this embodiment, the A / D conversion value is returned from the shift code representation to the binary code representation using the phase shift code / binary converter 113. As a result, the number of signals input to the output buffer 109 can be reduced. In particular, when the number of bits expressed by the phase shift code is large, an effect such as reduction in circuit area can be obtained. In addition, arithmetic processing by a DSP or the like can be facilitated as compared to the case where the shift code is output to the outside of the MOS sensor.

  As described above, according to the MOS sensor of the present embodiment, when the conversion bit width and the number of pixels are increased for improving the image quality, and when the frame rate is increased for increasing the speed, the trouble due to the waveform rounding of the counter clock signal is caused. Can be suppressed.

A gray code generation circuit that outputs a gray code is provided in place of the π / 2 ^m-1 phase shift code generation circuit 112, and a lower bit is expressed by a gray code in a latch provided in the column A / D conversion circuit 106. Even in this case, the clock frequency can be reduced and the bit accuracy of A / D conversion can be improved as compared with the conventional MOS sensor.

(Third embodiment)
FIG. 7 is a diagram showing a configuration of a MOS sensor according to the third embodiment of the present invention.

  As shown in the figure, the MOS sensor of this embodiment has the same connection from the pixel array 102 to the comparator as the MOS sensor of the first embodiment. However, the MOS sensor of this embodiment has an Up / Down counter (hereinafter abbreviated as a U / D counter) 218 in a column A / D conversion circuit 106 provided for each column of the pixels 101. Features. In addition, the MOS sensor of this embodiment includes a sequencer 338.

  Each column A / D conversion circuit 106 includes a comparator 107, the above-described U / D counter 218, an Up count latch (hereinafter abbreviated as a U latch) 318, and a Down count latch (hereinafter referred to as a D latch). 328).

  The clock generation circuit 120 supplies the clock signal 121 to the binary counter 104 and also supplies it to the U / D counter 218, the U latch 318, and the D latch 328 of each column. The binary value output from the binary counter 104 is input to the DAC 105, and the DAC 105 generates an analog ramp voltage (triangular wave) 122 according to the input binary value. The analog ramp voltage is input to the input unit of the comparator 107 as a reference potential. A pixel signal read from the pixel 101 via the read signal line 103 is input to the other input of the comparator 107. The comparator output signal 123 is input to the U / D counter 218, the U latch 318, and the D latch 328.

  Next, the A / D conversion operation of the MOS sensor according to this embodiment will be described.

  The sequencer 338 is responsible for switching the operation mode of the MOS sensor (or imaging device). Here, the sequencer 338 includes a count mode switching signal 130 for controlling the count direction of the U / D counter 218, an Up latch selection signal 131 for switching between latches used at the Up count and the Down count, The down latch selection signal 132 is controlled.

  First, the U / D counter 218 and the binary counter 104 in the column A / D conversion circuit 106 are initialized by an initialization signal (not shown) in advance, and the initial value of the analog ramp voltage 122 is supplied from the DAC 105 to one of the comparators 107. To the input section. Also, assuming that the Down count is performed first, the D latch 328 is activated by the Down latch selection signal 132, and the U / D counter 218 is set to the down mode (D mode) by the count mode switching signal 130. Next, the reset level of the pixel 101 is read from the pixel 101 in the selected row, and this is supplied to the other input unit of the comparator 107. Then, by starting the input of the clock signal 121 generated by the clock generation circuit 120, the binary counter 104 starts counting from its initial value. The DAC 105 starts generating the analog ramp voltage 122 from the initial value according to the count value of the binary counter 104. Here, the counting direction of the binary counter 104 is always the same during down-counting and up-counting. In addition, when the supply of the clock signal 121 is started, the U / D counter 218 in the column A / D conversion circuit 106 also starts to count down the input clock signal 121.

  Thereafter, when the magnitude relationship between the two input signals to the comparator 107 in a certain column is switched, the comparator output signal 123 of the comparator 107 is inverted, and the clock signal 121 to the U / D counter 218 in that column is masked. At the same time, the U / D counter 218 stops counting and the U / D counter 218 holds the count value. Similarly, by the inversion of the comparator output signal 123, the D latch 328 holds the clock signal 121 as data at the same timing as the U / D counter 218 stops counting. Since the analog ramp voltage 122, the count value of the U / D counter 218, and the value of the D latch 328 are synchronized with each other by the clock signal 121, the reset level (analog signal) of the pixel 101 is set to U / That is, A / D conversion is performed to a value (digital signal) held in the D counter 218 or the D latch 328.

  Next, up-counting is performed according to the following procedure.

First, the U latch 318 is activated by the Up latch selection signal 131, and the U / D counter 218 is set to the up mode (U mode) by the count mode switching signal 130. At this time, the U / D counter 218 holds the value held in the D mode as it is. Next, a pixel signal is read from the pixels 101 in the selected row and supplied to the other input unit of the comparator 107. Then, by starting the input of the clock signal 121 generated by the clock generation circuit 120, the binary counter 104 starts counting from its initial value. The DAC 105 starts generating the analog ramp voltage 122 from the initial value according to the count value of the binary counter 104. In addition, when the supply of the clock signal 121 is started, the U / D counter 218 in the column A / D conversion circuit 106 starts to count up the input clock signal 121 from the held value. Thereafter, when the magnitude relationship between the two input signals to the comparator 107 in a certain column is switched, the comparator output signal 123 of the comparator 107 is inverted, and the clock signal 121 to the U / D counter 218 in that column is masked. At the same time, the U / D counter 218 stops counting and the U / D counter 218 holds the count value. The value held at this time is
(Up count in U mode)-(Down count in D mode)
It has become.

  Similarly, by the inversion of the comparator output signal 123, the U latch 318 holds the clock signal 121 as data at the same timing as the U / D counter 218 stops counting.

  Next, the k-bit data output from the U / D counter 218 and the 1-bit data output from the U latch 318 are bundled as k + 1 bit data on the output signal buses 126 and 227, and are sent to the subtractor 117. Entered. The data output from the D latch 328 is input to the subtractor 117 via the output signal buses 127 and 228. Next, the image signal output from the subtractor 117 is output to the outside of the MOS sensor via the output signal bus 230 and the output buffer 109. In this way, A / D conversion is performed by obtaining a difference between the A / D conversion value in the up-count period and the A / D conversion value in the down-count period and outputting a signal corresponding to the difference. .

  As described above, the use of the U / D counter 218 can eliminate the influence of offset noise from the pixels in each column to the column A / D conversion circuit, so that a good output image can be obtained. Become.

  Even in the case where the U / D counter 218 and 1-bit latch are provided in the column A / D conversion circuit 106 of each column as in the present embodiment, as in the MOS sensor of the first embodiment, By holding data representing bits, the frequency of the clock signal 121 can be halved. Alternatively, when the frequency of the clock signal 121 is not changed, the accuracy of A / D conversion can be improved by one bit compared to the case where no latch is provided.

  Similarly to the MOS sensor of the first embodiment, in the MOS sensor of this embodiment, when the signal input to the latch is also used as the clock signal for the U / D counter 218, it becomes the least significant bit. The data polarity of the power latch can be reversed. In this case, as shown in FIG. 9, the inverter 119 may be provided between the clock generation circuit 120 and the U latch 318 and the D latch 328. Alternatively, the inverter 119 may be inserted on the signal output bus 127. Alternatively, the connection relationship between 1-bit data output for U and D is switched, the counter output is bundled as D-data, and input to the + side of the subtractor, and the U-data is input to the − side of the subtractor. Also good. As a result, the number of signal lines for supplying a clock signal to the latch can be reduced.

Although not described in detail, as shown in FIG. 8, 2 ^m−1 Up latches and Down latches (U 2 ^m−1 bit latches 358, Even when a 2 ^m-1 bit latch 368 for D is provided and a phase shift code is applied, the same clock frequency reduction effect or A / D conversion accuracy improvement effect as in the second embodiment described above can be obtained. Obtainable. The MOS sensor according to the modification of the present embodiment shown in FIG. 8 is similar to the MOS sensor of the second embodiment shown in FIG. 5 and the π / 2 ^m−1 phase shift code generation circuit 112 and the input data Is provided with a phase shift code / binary converter 113 for converting the expression of the above into a binary code from a phase shift code. However, the phase shift code / binary converter 113 is provided on the output signal bus 227 for transmitting the U latch data and on the output signal bus 228 for transmitting the D latch data. The binary signal output from the phase shift code / binary converter 113 on the output signal bus 227 is input to the subtractor 117 via the output signal bus 327. The binary signal output from the phase shift code / binary converter 113 on the output signal bus 228 is input to the subtractor 117 via the output signal bus 348. The full-bit image signal output from the subtractor 117 is output from the output buffer 109 to the outside of the MOS sensor.

  As described above, the case has been described in which the phase shift code is used to express the lower 4 bits of the A / D conversion value using the latch clock signal. Similarly, the lower 5 bits or more of the image signal can be expressed using the latch clock signal, and the clock frequency can be greatly reduced. However, since the number of wirings for supplying the latch clock signal is doubled every 1 bit, the optimum number of bits according to the application is considered in consideration of the trade-off between the increase in layout area and the effect of reducing the clock frequency. Is preferably selected.

  In the column A / D conversion circuit 106 of each embodiment, the description is limited to a memory or latch for A / D conversion, such as a latch attached to a digital memory or a counter. In D conversion, reading and A / D conversion are often performed in parallel in a limited time of one horizontal scanning period (1H). That is, in many cases, a parallel operation of reading the data A / D converted one line before the outside of the chip and A / D conversion of the current line is performed. In this case, the column A / D conversion circuit 106 receives an output from a latch that holds lower-bit data and an output from a column counter (or U / D counter) and can output an A / D conversion value. An additional memory may be further provided.

FIG. 10 is a diagram showing a MOS sensor when an output memory is provided in the column A / D conversion circuit 106 of the MOS sensor according to the first embodiment. The output memory 250 copies k output latches for copying the upper k bits of data held in the column counter 208 and the lower m bits of data held in 2 ^m−1 latches. 2 ^m−1 ( ^{1 in} the example of FIG. 10) output latches. If the number of bits for A / D conversion is n bits, n = k + m. In this case, the A / D conversion value of each column held in r (r = k + 2 ^m−1 ) output latches at the end of A / D conversion for one row of pixel signals is controlled. The data is sequentially read out to the output data bus by the column scanning means (control unit) that drives the line 750. A / D conversion of the pixels in the next row is performed along with this readout operation. By sequentially performing this process, it is possible to quickly output a pixel signal for one screen after A / D conversion.

  In the above description, the counter clock signal is supplied to the column counter 208 or the U / D counter 218 until the voltage of the image signal output from the pixel 101 becomes equal to the potential of the analog ramp voltage 122. Means for masking the clock supply to the column counter 208 or the U / D counter 218 during the period after the time point when the voltage of the image signal output from is equal to the potential of the ramp wave is not clearly shown. However, as this masking means, a general masking method such as inserting an AND gate having the clock signal 121 and the comparator output signal 123 as inputs can be used.

  It should be noted that the MOS sensor of the first to third embodiments is omitted for easy understanding of the analog CDS operation generally performed as a part of the reading sequence from the pixel 101. However, an analog CDS operation may be performed in the MOS sensor of each embodiment. In this case, in the sequence of sequentially reading out pixels one by one, the number of items to be processed increases during the processing time (1H) for one row. However, if the MOS sensor of the present invention is used, the A / D conversion speed is increased. Therefore, the CDS operation can be performed without any trouble.

  In the above, the method of using the counter value to generate the analog ramp voltage 122 by the DAC 105 has been described. However, the DAC 105 is initialized by the reset signal without using the counter value, and is free-running by the input of the clock signal. It may be a D / A conversion circuit of the type.

  Further, when a method of generating an analog ramp wave by discharging with an RC time constant is applied to the A / D conversion method of the present invention, it is not necessary to input a clock signal, and the capacitance provided in the D / A conversion circuit 105 The A / D conversion can be performed simply by initializing the potential of the signal with the reset signal.

  Further, if the phase shift code is output as it is, the number of signals input to the output buffer 109 increases, so in FIG. 5, FIG. 8, etc., the data expressed by the phase shift code is converted into a binary code and output. As explained above, if the number of bits to which the phase shift code is applied is small, the increase in signal lines is less than when only the binary code is used, so the phase shift code data is output to the outside as it is. Also good.

  In the above description, the configuration including the phase shift code generation circuit and the shift code-to-binary code conversion circuit has been described. However, the MOS sensor includes a binary code-to-grey code conversion circuit, a gray code, and the like. A configuration including a conversion circuit from a binary code to a binary code may be used. Alternatively, even in a system that includes only a binary code to gray code conversion circuit and outputs an image signal in gray code, the clock frequency reduction effect and bit accuracy improvement effect of the present invention are not lost.

  In any of the embodiments, the two-input type comparator is shown as the comparator 107, but the effect of the present invention can be obtained even if a so-called chopper type comparator is used.

  Further, the connection relationship between the pixel and the comparator 107 by the readout signal line 103 has been described as a simple connection in consideration of easy understanding, but a circuit having an analog signal amplification function and a CDS function on the input side of the comparator 107. Even if it is the structure which mounts, the effect of this invention is not lost.

  The image processing circuit (DSP circuit) for processing the image signal output from the output buffer 109 may be formed on the same substrate as the pixel array 102 or may be formed on a different substrate. .

  Further, the sequencer 338 shown in FIGS. 8 and 9 may be provided in the MOS sensor according to the first and second embodiments.

(Other embodiments)
The specific configuration of the π / 2 ^m−1 phase shift code generation circuit 112 in the MOS sensor shown in FIGS. 5 and 8 will be described below.

-First configuration example of phase shift code generation circuit-
FIGS. 11A and 12A are circuit diagrams showing a phase shift code generation circuit according to a first configuration example using a Johnson counter. FIGS. 11B and 12B are It is a figure which shows the signal waveform in the phase shift code generation circuit which concerns on a 1st structural example, respectively. FIG. 11A shows the case where the number of bits 2 ^m−1 is 2, and FIG. 12A shows the case where the number of bits 2 ^m−1 is 4. Here, m means the number of bits when binary is used.

  The phase shift code generation circuit shown in FIG. 11A includes D-type flip-flops 901a and 901b that receive a clock signal CLK (latch clock signal), an inverter 902a that outputs J [0], and J [1]. And an inverter 902b. The output of the first-stage D-type flip-flop 901a is input to the second-stage D-type flip-flop 901b, and the inverted output of the D-type flip-flop 901b is input to the D-type flip-flop 901a. That is, the D flip-flops 901a and 901b constitute a loop as a whole. The inverted output of the D flip-flop 901a is input to the inverter 902a, and the inverted output of the D flip-flop 901b is input to the inverter 902b.

  With the above configuration, as shown in FIG. 11B, a phase shift code J [1: 0] having a phase different from the initial value all zero state by the period of CLK can be generated.

  In addition, as shown in FIG. 12A, four stages of D-type flip-flops 901a, 901b, 901c, and 901d are connected in series like a normal shift register, and the D-stage flip-flop 901d of the final stage is inverted. By inputting the output to the first-stage D-type flip-flop 901a, J [0], J [1], J [2] whose phases are shifted from the inverters 902a, 902b, 902c, and 902d by the period of CLK, respectively. , J [3] can be output. That is, according to the configuration shown in FIG. 12A, as shown in FIG. 12B, a phase shift code J [3: 0] having a phase different from the initial value all zero state by the period of CLK can be generated. .

  In the case of the Johnson counter according to the first configuration example, it is necessary to input a high-frequency clock signal (CLK in FIGS. 11 and 12 and clock signal 121 in FIG. 5) in order to drive the counter. However, since only one phase shift code generation circuit needs to be provided for the column A / D conversion circuits in all columns, even if a high frequency clock signal is supplied to the phase shift code generation circuit, Problems such as rounding do not occur. Therefore, according to the first configuration example, it is possible to generate the phase shift code without causing problems such as waveform rounding.

The phase shift code generation circuit shown in FIG. 12A is a case where the number of bits is 2 ^m−1 = 4, and when this is mounted on the MOS sensor described as the third embodiment, only binary is used. Compared to the case of / D conversion, the maximum frequency of the signal can be reduced to 1/8, and the frequency can be suppressed to a quarter of the frequency compared to the case of only the gray code. Or, when using a clock signal with the same frequency as the A / D converter circuit using only the Gray code, it is possible to improve the accuracy of 3 bits compared to the binary only, and improve the accuracy of 2 bits compared to the gray code only. It is.

  Although the configuration of the phase shift code generation circuit when the number of bits is 2 or 4 has been described, D-type flip-flops corresponding to the number of bits are connected in series, and the inverted output of the D-type flip-flop at the final stage is By inputting the signal to one stage of the D-type flip-flop, a phase shift code generation circuit corresponding to an arbitrary bit width can be configured.

-Second configuration example of phase shift code generation circuit-
When the frequency becomes very high, it becomes difficult to generate a high-speed clock due to limitations in device performance before the problem of rounding of the waveform when distributing the clock signal. On the other hand, by using a delay lock loop circuit (hereinafter referred to as DLL), the input clock frequency can be suppressed to the same frequency level as the phase shift code for generating the phase shift code generation circuit.

  FIGS. 13A to 13C are diagrams illustrating a phase shift code generation circuit according to a second configuration example using a DLL.

  First, the configuration example of the phase shift code generation circuit illustrated in FIG. 13A includes a phase comparator 802, a charge pump circuit 803, and a delay unit 801. In this configuration example, the clock signal RCLK (latch clock signal) input to the phase comparator 802 is delayed by the delay unit 801 and output as DCLK. Specifically, RCLK and DCLK are compared by the phase comparator 802 so that the delay amount is exactly one cycle, and an UP or DOWN signal is generated for the early / late difference, and the charge pump circuit 803 Receives a signal from the phase comparator 802 and generates a voltage signal VCON corresponding thereto.

  As shown in FIG. 13B, the delay unit 801 adds a capacitor 806 as a load via an NMOS transistor switch (hereinafter referred to as a MOS switch) 805 to an inverter chain formed by connecting inverters 804 in multiple stages. Circuit. VCON controls the gate potential of the MOS switch 805 connected to the capacitor 806. When this VCON is increased, the on-resistance of the MOS switch 805 is reduced, the capacity is increased as a load, and the delay is increased. Conversely, when the potential of VCON is lowered, the ON resistance of the MOS switch 805 is increased, the capacitance is reduced as a load, and the delay is reduced.

FIG. 14 is a diagram illustrating a configuration example of a phase shift code generation circuit that uses the DLL circuit configuration illustrated in FIGS. 13A and 13B and outputs a signal whose phase is shifted by π / 2 ^m−1 . is there.

  As shown in FIG. 14, a DLL that aligns the phases of the original clock signal (RCLK) and the delayed clock (DCLK) that has passed through 16 delay stages delays by 1/16 of one cycle per delay stage ( It is possible to obtain clock signals n [1], n [2],..., N [15], n [16] (= DCLK) with a phase delay π / 8). A circuit shown in FIG. 14 is obtained by extracting clock signals (for example, D [1] to D [8] in which n [1] to n [8] are buffered by the clock buffer 807) from eight adjacent nodes. Can be used as a phase shift code generation circuit. Although it is not necessary to extract the clock from the nodes n [9] to n [16], it is more desirable to buffer these nodes in order to increase the timing accuracy by equalizing the load in each delay stage.

  The phase shift code generation circuit of the second configuration example for generating the phase shift code having a specific bit width has been described above. However, by changing the number of shift register stages or the number of DLL delay stages in the phase shift code generation circuit. Thus, phase shift codes having different bit widths can be easily generated.

  Note that the phase shift code generation circuit shown in FIG. 14 has a bit width of m = 4, and when this is mounted on the MOS sensor described as the third embodiment, the maximum frequency of the signal is only binary. It can be suppressed to 1/16 compared to the case where A / D conversion is performed, and to 1/8 compared to the case where A / D conversion is performed using only the gray code. Alternatively, when signals having the same frequency are used, an accuracy improvement of 4 bits can be realized as compared with the case of binary only, and an accuracy improvement of 3 bits can be achieved as compared with the case of only Gray code.

  In another embodiment of the present invention, by mounting a phase shift code generation circuit using a Johnson counter, a clock signal distributed to a column A / D conversion circuit unit having a large RC load or a count value signal is inevitably generated. In addition, there is an effect that it is not necessary to request steep rise / fall characteristics.

  In addition, by mounting a phase shift generation circuit using DLL, not only the (clock) signal distributed to the column A / D conversion circuits of each column but also the clock signal generated by the clock generation circuit is GHz. The design specifications can be relaxed so that it is not necessary to generate a class clock signal. Therefore, there is an effect that it is not necessary to forcibly merge a high-speed CMOS process having characteristics that are not necessarily compatible with a high-quality process essential for an imaging element (solid-state imaging device). In addition, the system has an effect of reducing noise in the image sensor and reducing electromagnetic radiation.

FIGS. 15A and 15B are diagrams illustrating a configuration example of the 2 ^m−1 bit phase shift code / binary converter 113 illustrated in FIGS. 5 and 8. FIG. 15A shows the case where the bit width m = 2, and FIG. 15B shows the case where the bit width m = 3.

  As shown in FIG. 15A, when m = 2, both the phase shift code PS [0] and PS [1] input to the phase shift code / binary converter are input to the exclusive OR circuit 905. Then, the exclusive OR circuit 905 converts it into binary BIN [0]. Further, PS [1], which is the most significant bit of the phase shift code, is output as binary most significant bit BIN [1] as it is.

  Further, as shown in FIG. 15B, when m = 3, three exclusive OR circuits 905 are provided, and PS [0] and PS [2] are provided in the first exclusive OR circuit 905a. Similarly, PS [1] and PS [3] are input to the exclusive OR circuit 905b in the first stage. The outputs of the exclusive OR circuits 905a and 905b are input to the second-stage exclusive OR circuit 905c, and the binary least significant bit BIN [0] is output from the exclusive OR circuit 905c. The binary BIN [1] is outputted from the exclusive OR circuit 905b, and the most significant bit PS [3] of the phase shift code is outputted as it is as the most significant bit BIN [2] of the binary. As described above, the conversion from the phase shift code to the binary can be easily performed by combining the exclusive OR circuit.

  As described above, the solid-state imaging device and the driving method thereof according to the present invention are useful for an imaging device for detecting various physical quantity distributions such as light and radiation.

It is a figure which shows the structure of the solid-state imaging device (MOS sensor) which concerns on the 1st Embodiment of this invention. (A) is a figure which shows the operation waveform in the column A / D conversion circuit of the MOS sensor which concerns on a 2nd prior art example, (b) is the A / D conversion circuit of the MOS sensor which concerns on 1st Embodiment. It is a figure which shows the operation | movement waveform in. (A) is a figure which shows the operation | movement waveform in the column A / D conversion circuit of the MOS sensor which concerns on a 2nd prior art example, (b) is column A / D conversion of the MOS sensor which concerns on 1st Embodiment. It is a figure which shows the operation | movement waveform in a circuit. It is a figure which shows the modification of the MOS sensor which concerns on 1st Embodiment. It is a figure which shows the structure of the MOS sensor which concerns on the 2nd Embodiment of this invention. In the MOS sensor which concerns on 2nd Embodiment, it is a wave form diagram at the time of substituting the low-order 4 bits of A / D conversion value for the phase shift code. It is a figure which shows the structure of the MOS sensor which concerns on the 3rd Embodiment of this invention. It is a figure which shows the modification of the MOS sensor which concerns on 3rd Embodiment. It is a figure which shows the modification of the MOS sensor which concerns on 3rd Embodiment. It is a figure which shows a MOS sensor at the time of providing the memory for output in the column A / D conversion circuit of the MOS sensor which concerns on 1st Embodiment. (A) is a circuit diagram which shows the 2 ^m-1 bit phase shift code generation circuit which concerns on the 1st structural example using a Johnson counter, (b) is 2 ^m-1 which concerns on a 1st structural example. It is a figure which shows the signal waveform in a bit phase shift code generation circuit. (A) is a circuit diagram showing a 2 ^m-1 bit phase shift code generation circuit according to a ^first configuration example using a Johnson counter, and (b) is a 2 ^m-1 bit according to the first configuration example. It is a figure which shows the signal waveform in a phase shift code generation circuit. (A)-(c) is a figure which shows the 2 ^m-1 bit phase shift code generation circuit based on the 2nd structural example using DLL. The figure which shows the structural example of the ^2m-1 bit phase shift code generation circuit which outputs the signal which shifted the phase by (pi) / 2 ^m-1 using the circuit structure of DLL shown to Fig.13 (a), (b). It is. (A), (b) is a figure which shows the structural example of 2 ^m-1 bit phase shift code / binary converter 113 shown in FIG. 5, FIG. It is a figure which shows the structure of the MOS sensor which concerns on a 1st prior art example. It is a figure which shows the structure of the MOS sensor which concerns on a 2nd prior art example. (A) is a figure which shows roughly the relationship between the clock signal supplied to the digital memory of the MOS sensor of the same type as a 1st prior art example, and the position of a digital memory, (b) is a clock frequency f. Is a diagram showing clock waveforms at point A and point C in (a) in the case of (a), and (c) is a clock waveform at points A and C in (a) when the clock frequency is 2f. FIG.

Explanation of symbols

101 pixels
102 pixel array
103 Read signal line
104 Binary counter
105 DAC
106 Column A / D conversion circuit
107 comparator
108 Digital memory
109 Output buffer
112 π / 2 ^m−1 phase shift code generation circuit
113 Phase shift code / binary converter
117 Subtractor
119 inverter
120 clock generation circuit
121 clock signal
122 Analog lamp voltage
123 Comparator output signal
125 phase shift code
126, 127, 128, 228, 327, 348 Output signal bus
130 Count mode switching signal
131 Latch selection signal for Up
132 Down latch selection signal
141 Inverted clock signal
208 column counter
218 U / D counter
308 Latch
318 U latch
328 D latch
338 sequencer
358 U 2 ^m-1 bit latch
368 D 2 ^m-1 bit latch for D
408 2 ^m−1 bit latch 801 delay unit
802 Phase comparator
803 Charge pump circuit
804 inverter
805 MOS switch
806 capacity
807 clock buffer
901a, 901b, 901c, 901d D-type flip-flop
902a, 902b, 902c, 902d inverter
905, 905a, 905b exclusive OR circuit

Claims (15)

A sensitive element array in which sensitive elements for detecting physical quantities are arranged in a matrix;
A column A / D conversion circuit that is provided for each one or a plurality of rows of the sensitive elements, and converts a signal output from the sensitive elements of each row into a digital signal;
An output signal bus for transmitting a digital signal output from the column A / D conversion circuit of each column;
A clock generation circuit for supplying a counter clock signal and a latch clock signal to the column A / D conversion circuit;
A physical quantity detection device including a D / A converter that outputs a triangular wave,
Each of the column A / D conversion circuits is
A comparator that compares the signal output from the sensitive element with a potential of the triangular wave during a predetermined period;
A column counter that counts the pulses of the counter clock signal and holds a count value at the time when the output of the comparator changes;
Receiving one or more latches for receiving the latch clock signal and holding the value of the latch clock signal at the time when the output from the comparator changes, the count value of the column counter and the latch A physical quantity detection device that outputs the digital signal having a magnitude corresponding to an A / D conversion value expressed in combination with a value held by the output signal bus. The sensitive element is a pixel having a light receiving portion,
The sensitive element array is a pixel array;
The physical quantity detection device according to claim 1, wherein the physical quantity detection device is a solid-state imaging device. The latch clock signal includes a a frequency the same phase difference s number of signals,
A plurality of the latches are provided and hold the s clock signals, respectively.
The value held in the latch represents the lower m bits (m is a positive integer) of the A / D conversion value, and s = 2 ^(m-1). The physical quantity detection device described.   4. The physical quantity detection device according to claim 3, wherein the frequency of the counter clock signal is the same as that of the latch clock signal. Each of the column A / D conversion circuits is
An output memory for copying the count value held in the column counter and the value held in the latch;
The physical quantity detection device further comprises column selection means for sequentially selecting the A / D conversion values held in the output memory for each column and outputting the selected values to the output signal bus. The physical quantity detection device according to any one of 1 to 4.   A phase shift code generation circuit that generates s signals having a frequency of f and a phase shifted by π / s from the clock signal of frequency f output from the clock generation circuit and supplies the generated signals to the latch; The physical quantity detection device according to claim 3.   The physical quantity detection device according to claim 6, further comprising a phase shift code / binary converter that converts an output of the latch expressed in a phase shift code into a binary code representation. The clock signal is input to the phase shift code generation circuit,
8. The DLL circuit according to claim 6, wherein the phase shift code generation circuit includes a plurality of delay stages, and includes a DLL circuit that outputs s signals having the same frequency and a phase shifted by π / s. Physical quantity detector. A binary counter that receives the clock signal output from the clock generation circuit and outputs a binary value to the D / A converter;
The D / A converter, a physical quantity detecting device according to any one of claims 1-8, characterized by outputting the triangular wave in response to an input of the binary value. Count in the column counter, the physical quantity detecting device according to any one of claims 1-9, characterized in that changes on the rising or falling edge of the counter clock signal. The count value in the column counter changes at the rising edge of the counter clock signal,
The physical quantity detection device includes a first inverter interposed between the clock generation circuit and the latch of each column, or a second inverter that inverts an output signal from the latch of each column. physical quantity detecting apparatus according to any one of claims 1-10, characterized in that.   The physical quantity detection device according to claim 1, wherein the value held in the latch represents one bit or a plurality of bits on the least significant side of the A / D conversion value by a binary code. The column counter is an up / down counter that counts up the high-order bits of the signal output from the sensitive element and down-counts the high-order bits of the signal output from the sensitive element at the time of resetting.
The latch includes an up latch that holds a lower bit of a signal output from the sensitive element, and a down latch that holds a lower bit of a signal output from the sensitive element at the time of reset,
The output signal bus outputs the output of the up latch, the output of the down latch, and the difference between the count value at the time of counting up and the count value at the time of down counting in the column counter for each column. physical quantity detecting apparatus according to any one of claims 1 to 12, characterized. A sensing element array in which sensing elements for detecting a physical quantity are arranged in a matrix, and one or a plurality of columns of the sensing elements are provided, each including a comparator, a column counter, and one or a plurality of sensing elements. A column A / D conversion circuit for converting a signal output from the sensitive element in each column into a digital signal, and a digital signal output from the column A / D conversion circuit in each column. Physical quantity detection comprising: an output signal bus for transmission; a clock generation circuit for supplying a counter clock signal and s latch clock signals to the column A / D conversion circuit; and a D / A converter for outputting a triangular wave. A method for driving an apparatus, comprising:
The comparator compares the potential of the signal read from the sensitive element with the potential of the triangular wave for a predetermined period;
The column counter counting pulses of the counter clock signal from the start of comparison by the comparator;
After the step (b), the counter clock signal input to the column counter is masked when the output from the comparator changes, and the counter (c) holds the count value of the column counter ;
Step (d) in which the latch holds the potential of each of the s latch clock signals at the time when the output from the comparator changes after the step (b);
The value held by the latch in step (d) is the lower m bits, and based on the value expressed in combination with the count value of the column counter held in step (c), a predetermined voltage And a step (e) in which the column A / D conversion circuit outputs a digital signal to the output signal bus. The physical quantity detection device further includes an output memory provided in each column A / D conversion circuit, connected to an output unit of the column counter and an output unit of the latch, and a column selection unit.
In the step (e), after the steps (c) and (d) are completed for the signals read from the sensitive elements for all the columns, the signals for all the columns held by the column counter and the latch are stored. After copying the digital signal to the output memory, in parallel with the operation of the step (a) for the next selected row of the sensitive element array, the column selection means causes the digital of each column from the output memory. 15. The method of driving a physical quantity detection device according to claim 14 , wherein signals are sequentially read out to the output signal bus.

Images