JP5739040B2 - Time detection circuit, AD converter, and solid-state imaging device - Google Patents

Description

  The present invention relates to a time detection circuit, an AD converter using the time detection circuit, and a solid-state imaging device.

  As an example of a conventional time detection circuit, the configuration shown in FIG. 8 (see, for example, Patent Documents 1 and 2) is known. First, the configuration and operation of the time detection circuit in FIG. 8 will be described.

  FIG. 8 shows a configuration of a time detection circuit according to a conventional example. The time detection circuit shown in FIG. 8 includes a delay unit 30, a comparison unit 31, a latch unit 33, and a count unit. The delay unit 30 includes a plurality of delay units DU [0] to DU [7] that output an input signal with a delay. A start pulse (= StartP) is input to the first delay unit DU [0]. The comparison unit 31 receives the analog signal Signal to be time-detected and the ramp wave Ramp that decreases with the passage of time, and outputs a signal indicating the result of comparing the analog signal Signal and the ramp wave Ramp. Have The latch unit 33 includes latch circuits D_0 to D_7 that latch the logic states of the outputs CK0 to CK7 of the delay unit 30. The count unit 34 has a counter circuit that performs counting based on the output CK7 from the delay unit 30.

  In the comparison unit 31, a time interval (size in the time axis direction) corresponding to the amplitude of the analog signal Signal is generated. The buffer circuit is an inverting buffer circuit that inverts and outputs an input signal. Here, in order to facilitate understanding of the description in the present specification, an inverting buffer circuit is used.

  The latch circuits D_0 to D_7 constituting the latch unit 33 are enabled (valid) when the output Hold of the buffer circuit is High, and the outputs CK0 to CK7 of the delay units DU [0] to DU [7] are output as they are. To do. The latch circuits D_0 to D_7 are disabled (invalid) when the output Hold of the buffer circuit transits from High to Low, and the outputs CK0 to CK7 of the delay units DU [0] to DU [7] at that time The logic state corresponding to is latched.

  The control signal RST is a signal for performing a reset operation of the counter circuit constituting the count unit 34. Although the count latch circuit for latching the logical state of the count result of the count unit 34 is not clearly shown, the counter circuit also serves as the count latch circuit by using a counter circuit having a latch function.

  Next, the operation of the conventional example will be described. FIG. 9 shows the operation of the time detection circuit according to the conventional example.

  First, at a timing (first timing) related to the start of comparison in the comparison unit 31, a clock having a cycle substantially matching the delay time of the delay unit 30 is input to the delay unit 30 as a start pulse (= StartP). As a result, the delay unit 30 starts operating. The delay unit DU [0] constituting the delay unit 30 inverts and delays the start pulse (= StartP) and outputs it as an output CK0, and the delay units DU [1] to DU [7] constituting the delay unit 30 are The outputs of the preceding delay units are inverted and delayed, and output as outputs CK1 to CK7. Outputs CK0 to CK7 of the delay units DU [0] to DU [7] are input to the latch circuits D_0 to D_7 of the latch unit 33. Since the output Hold of the buffer circuit is High, the latch circuits D_0 to D_7 are enabled, and the outputs CK0 to CK7 of the delay units DU [0] to DU [7] are output as they are.

  The count unit 34 performs a count operation based on the output CK7 of the delay unit 30 output as the output Q7 of the latch circuit D_7 of the latch unit 33. In this count operation, the count value increases or decreases at the rise or fall of the output CK7. The output CO is inverted at the timing (second timing) at which the analog signal Signal and the ramp wave Ramp substantially coincide. After the output CO of the comparison unit 31 is buffered by the buffer circuit (third timing), the output Hold of the buffer circuit becomes Low.

  As a result, the latch circuits D_0 to D_7 are disabled. At this time, logic states corresponding to the outputs CK0 to CK7 of the delay units DU [0] to DU [7] are latched in the latch circuits D_0 to D_7. The count unit 34 latches the count value when the latch circuit D_7 stops its operation. Data corresponding to the analog signal Signal is obtained from the logic state latched by the latch unit 33 and the count value latched by the count unit 34.

  According to the time detection circuit according to the conventional example, data corresponding to the time interval can be obtained. That is, the time corresponding to the time interval can be detected. An AD converter that converts an analog signal into a digital signal can also be configured by using the time detection circuit.

JP 2009-38726 JP 2009-38781 A

  However, the conventional time detection circuit has the following problems. That is, when the latch circuits D_0 to D_6 constituting the latch unit 33 operate during the time interval, the current value consumed by the latch unit 33 increases, and it is difficult to reduce the current consumption of the time detection circuit. There are challenges.

  In the time detection circuit of the conventional example, the latch circuits D_0 to D_6 constituting the latch unit 33 always operate during the period from the first timing to the third timing. Since the outputs CK0 to CK7 of the delay unit 30 generally have a high frequency, the current consumed by the latch circuits D_0 to D_6 constituting the latch unit 33 makes it difficult to reduce the current consumption of the time detection circuit itself. Yes.

Here, as an example of a specific device using the conventional time detection circuit in the AD converter, consider an imager used in a digital still camera (DSC) or the like. Specifically, let us assume a spec with 20 million pixels and a frame rate of 60 frames / sec. Note that the AD converter is arranged for each pixel column. For ease of explanation, if the pixel arrangement of 20 million pixels is 4000 rows x 5000 columns vertically and horizontally, and there is no blanking period for simplification, the number of rows to read out pixel signals per second is It becomes as follows.
60frame / sec × 4000 lines / frame = 240Kline / sec

That is, the read rate for one row is 240 KHz. For example, if the 10-bit AD conversion is composed of the upper 7 bits (count value of the count unit 34) and the lower 3 bits (data of the latch circuits D_0 to D_7 constituting the latch unit 33), the read rate of one row The clocks CK0 to CK7 need to be output from the delay unit 30 at 128 (= 2 ⁷ ) times, that is, about 30 MHz. Assuming that the current consumption per latch circuit constituting the latch unit 33 is 1 uA / piece, the current consumption in the latch circuits D_0 to D_6 per column is
1uA / piece x 7 = 7uA
It becomes. Note that the output of the latch circuit D_7 is not included in the calculation because it is used as the count clock of the counter circuit constituting the count unit 34.

  That is, the current consumption value in 5000 rows is 35 mA. This calculation does not take into account a period in which comparison operation as AD conversion cannot be performed, such as a waiting period until the AD converter receives data from the pixel, and in addition to the above pixels, pixels from OB (Optical Black) pixels Since the signal reading period and the blanking period are excluded, it is considered that the frequency is actually higher than the estimated frequency of 30 MHz.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a time detection circuit, an AD converter, and a solid-state imaging device that can reduce current consumption.

  The present invention has been made to solve the above-described problem, and has a plurality of delay units that output an input signal with a delay, and starts an operation at a first timing related to the input of the first pulse. A delay unit, a latch unit that latches a logic state of the plurality of delay units, a count unit that counts based on a clock output from any of the plurality of delay units, and an input of a second pulse And a latch control unit that enables the latch unit at a second timing and causes the latch unit to execute a latch at a third timing after a predetermined time has elapsed from the second timing.

  In the time detection circuit of the present invention, the delay unit is an annular delay circuit in which the plurality of delay units are connected in an annular shape.

  The time detection circuit of the present invention receives a predetermined analog signal and a reference signal that increases or decreases as time passes, and compares the reference signal when a predetermined condition is satisfied with respect to the analog signal. A comparator that outputs a signal, the comparison signal is input to the latch control unit, the first timing is related to a timing at which the analog signal is input to the comparator, and the second timing is The comparison signal is related to the timing at which the comparison signal is input to the latch control unit.

  Further, the present invention provides a digital signal based on the time detection circuit, the reference signal generation unit that generates the reference signal, the logic state latched in the latch unit, and the count state in the count unit. An AD converter having a calculation unit to generate.

  In addition, the present invention provides an image pickup unit in which a plurality of pixels that output pixel signals according to the magnitude of incident electromagnetic waves are arranged in a matrix, and the analog signal corresponding to the pixel signals is input. An AD converter, wherein the comparison unit, the latch unit, the count unit, and the latch control unit are provided for each column or a plurality of columns of the pixels constituting the imaging unit. A solid-state imaging device.

  According to the present invention, by enabling the latch unit at the second timing related to the input of the second pulse, and causing the latch unit to execute the latch at the third timing after a predetermined time has elapsed from the second timing. Since the operation time of the latch portion is shortened, current consumption can be reduced.

FIG. 2 is a circuit diagram showing a configuration of a time detection circuit according to the first embodiment of the present invention. 3 is a timing chart showing the operation of the time detection circuit according to the first embodiment of the present invention. FIG. 5 is a circuit diagram showing a configuration of a time detection circuit according to a second embodiment of the present invention. 6 is a timing chart showing the operation of the time detection circuit according to the second embodiment of the present invention. FIG. 6 is a circuit diagram showing a configuration of a time detection circuit according to a third embodiment of the present invention. 6 is a timing chart showing the operation of the time detection circuit according to the third embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a solid-state imaging device according to a fourth embodiment of the present invention. It is a circuit diagram which shows the structure of the conventional time detection circuit. It is a timing chart which shows operation | movement of the conventional time detection circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows an example of the configuration of the time detection circuit according to the present embodiment. Hereinafter, the configuration of this example will be described. The time detection circuit shown in FIG. 1 includes a delay unit 30, a signal generation unit 32, a latch unit 33, and a count unit.

  The delay unit 30 includes a plurality of delay units DU [0] to DU [7] that output an input signal with a delay. A start pulse (= StartP) is input to the first delay unit DU [0].

  The signal generator 32 generates a control signal for controlling the operations of the latch unit 33 and the count unit 34. The signal generation unit 32 performs a logical product of an inverting delay circuit DLY that inverts and delays the analog signal Signal to be time-detected, an input LO (= Signal) of the inverting delay circuit DLY, and an output xLO_D of the inverting delay circuit DLY ( And an AND circuit that outputs a signal obtained by AND). Although details will be described later, with this configuration, the signal generation unit 32 enables the latch circuits D_0 to D_6 of the latch unit 33 at the second timing after the start pulse (= StartP) is input at the first timing ( A control signal for causing the latch circuits D_0 to D_6 and the count unit 34 to execute latching is generated at a third timing after a predetermined time has elapsed from the second timing.

  The latch unit 33 includes latch circuits D_0 to D_7 that latch the logic states of the outputs CK0 to CK7 of the delay unit 30. The latch unit 33 includes an AND circuit that outputs a signal Hold_C obtained by ANDing the output xLO_D of the inverting delay circuit DLY of the signal generation unit 32 and the control signal Enable to the latch circuit DU [7]. The count unit 34 has a counter circuit that performs counting based on the output CK7 from the delay unit 30.

  The latch circuits D_0 to D_6 constituting the latch unit 33 are enabled (valid) when the output Hold_L of the AND circuit of the signal generation unit 32 is High, and the output CK0 of the delay units DU [0] to DU [6] ~~ CK6 is output as it is. The latch circuits D_0 to D_6 are disabled (invalid) when the output Hold_L of the AND circuit of the signal generation unit 32 transits from High to Low, and the delay units DU [0] to DU [6] at that time The logic state according to the outputs CK0 to CK6 is latched.

  On the other hand, the latch circuit D_7 constituting the latch unit 33 is enabled (valid) when the output Hold_C of the AND circuit of the latch unit 33 is High, and outputs the output CK7 of the delay unit DU [7] as it is. Also, the latch circuit D_7 is disabled (invalid) when the output Hold_C of the AND circuit of the latch unit 33 transits from High to Low, and the logic state corresponding to the output CK7 of the delay unit DU [7] at that time Latch.

  The control signal Enable is a signal for controlling the AND circuit of the latch unit 33. The control signal RST is a signal for performing a reset operation of the counter circuit constituting the count unit 34. In this figure, the count latch circuit that latches the logical state of the count result of the count unit 34 is not clearly shown, but the counter circuit also serves as the count latch circuit by using a counter circuit having a latch function. In addition, this structure is an example to the last, and is not restricted to this.

  Next, the operation of this example will be described. FIG. 2 shows the operation of the time detection circuit according to the present embodiment.

  First, as a start pulse (= StartP), a clock having a period substantially matching the delay time of the delay unit 30 is input (first timing). As a result, the delay unit 30 starts operating. The delay unit DU [0] constituting the delay unit 30 inverts and delays the start pulse (= StartP) and outputs it as an output CK0, and the delay units DU [1] to DU [7] constituting the delay unit 30 are The outputs of the preceding delay units are inverted and delayed, and output as outputs CK1 to CK7. Outputs CK0 to CK7 of the delay units DU [0] to DU [7] are input to the latch circuits D_0 to D_7 of the latch unit 33. Since the input LO (= Signal) of the inverting delay circuit DLY is Low and the output Hold_L of the AND circuit of the signal generation unit 32 is Low, the latch circuits D_0 to D_6 are in a disabled state and have stopped operating. .

  On the other hand, since the output Hold_C of the AND circuit of the latch unit 33 is High, the latch circuit D_7 is in an enabled state and outputs the output CK7 of the delay unit DU [7] as it is. The count unit 34 performs a count operation based on the output CK7 of the delay unit 30 output as the output Q7 of the latch circuit D_7. In this count operation, the count value increases or decreases at the rise or fall of the output CK7.

  After the “detected time” to be detected has elapsed from the first timing, the input LO (= Signal) of the inversion delay circuit DLY of the signal generation unit 32 is inverted, so that the AND circuit of the signal generation unit 32 Output Hold_L becomes High. As a result, the latch circuits D_0 to D_6 are enabled. After a time corresponding to the delay time of the inverting delay circuit DLY of the signal generating unit 32 has elapsed from the second timing (third timing), the output xLO_D of the inverting delay circuit DLY of the signal generating unit 32 is inverted, and the signal The output Hold_L of the AND circuit of the generation unit 32 becomes Low. As a result, the latch circuits D_0 to D_6 are disabled. At this time, the logic states corresponding to the outputs CK0 to CK6 of the delay units DU [0] to DU [6] are latched in the latch circuits D_0 to D_6 of the latch unit 33.

  Further, since the output Hold_C of the AND circuit of the latch unit 33 becomes Low at the third timing, the latch circuit D_7 is disabled, and the logic state corresponding to the output CK7 of the delay unit DU [7] is changed to the latch unit 33. Is latched by the latch circuit D_7. The count unit 34 latches the count value when the latch circuit D_7 stops its operation. Data corresponding to “detected time” is obtained from the logic state latched by the latch unit 33 and the count value latched by the count unit 34. The latched data is output to, for example, a subsequent arithmetic unit (not shown), and processing such as binarization is performed.

  In the above operation, since the latch circuits D_0 to D_6 operate only during the period from the second timing to the third timing, current consumption in the latch unit 33 can be reduced. Therefore, the current consumption of the time detection circuit can be reduced.

  In this example, the power consumption is reduced by controlling the operations of the latch circuits D_0 to D_6 constituting the latch unit 33. However, for example, a configuration for controlling the latch circuits D_1 to D_5 may be used. . Moreover, it is not necessary to restrict to this.

(Second embodiment)
Next, a second embodiment of the present invention will be described. FIG. 3 shows an example of the configuration of the time detection circuit according to the present embodiment. The configuration diagram of this example will be described below. The configuration of the delay unit 30 is different from the configuration shown in FIG. In the present embodiment, an annular delay circuit is realized by connecting a plurality of delay units DU [*] (* is 0 to 7) constituting the delay unit 30 in a ring shape. Other than this, it is the same as FIG.

  Next, the operation of this example will be described. FIG. 4 shows the operation of the time detection circuit according to this embodiment. The difference from FIG. 2 is the start pulse (= StartP), and when the logic state of the start pulse (= StartP) changes from Low to High, the delay unit 30 starts operating, and the output CK7 from the delay unit 30 Based on the above, the counting operation of the counting unit 34 is performed. The rest is the same as in FIG.

  In the first embodiment, it is necessary to generate the start pulse (= StartP) as a clock having a period substantially matching the delay time of the delay unit 30, but in this embodiment, the generation of the start pulse (= StartP) Becomes easy. This facilitates control of the delay unit 30, that is, control of the time detection circuit.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 5 shows an example of the configuration of the time detection circuit according to the present embodiment. The configuration diagram of this example will be described below. In FIG. 5, the illustration of the delay unit 30 is omitted. The difference from the configuration shown in FIG. 3 is that a comparison unit 31 is added. The comparison unit 31 receives an analog signal Signal to be time-detected and a ramp wave Ramp that increases or decreases over time, and outputs a signal indicating a result of comparing the analog signal Signal and the ramp wave Ramp. Consists of a comparator. As a result, a time interval (corresponding to “detected time” in the description of FIG. 2) corresponding to the analog signal Signal is generated. Except this, it is the same as FIG.

  Next, the operation of this example will be described. First, the logic state of the start pulse (= StartP) changes from Low to High at the timing (first timing) related to the comparison start in the comparison unit 31. As a result, the delay unit 30 starts operating. The delay unit DU [0] constituting the delay unit 30 inverts and delays the start pulse (= StartP) and outputs it as an output CK0, and the delay units DU [1] to DU [7] constituting the delay unit 30 are The outputs of the preceding delay units are inverted and delayed, and output as outputs CK1 to CK7. Outputs CK0 to CK7 of the delay units DU [0] to DU [7] are input to the latch circuits D_0 to D_7 of the latch unit 33. Since the input CO of the inverting delay circuit DLY is Low and the output Hold_L of the AND circuit of the signal generation unit 32 is Low, the latch circuits D_0 to D_6 are in a disabled state and stop operating.

  On the other hand, since the output Hold_C of the AND circuit of the latch unit 33 is High, the latch circuit D_7 is in an enabled state and outputs the output CK7 of the delay unit DU [7] as it is. The count unit 34 performs a count operation based on the output CK7 of the delay unit 30 output as the output Q7 of the latch circuit D_7. In this count operation, the count value increases or decreases at the rise or fall of the output CK7.

  At the timing (second timing) when the analog signal Signal and the ramp wave Ramp substantially coincide with each other, the output CO of the comparison unit 31 is inverted and becomes High. As a result, the latch circuits D_0 to D_6 are enabled. After a time corresponding to the delay time of the inverting delay circuit DLY of the signal generating unit 32 has elapsed from the second timing (third timing), the output xCO_D of the inverting delay circuit DLY of the signal generating unit 32 is inverted, and the signal The output Hold_L of the AND circuit of the generation unit 32 becomes Low. As a result, the latch circuits D_0 to D_6 are disabled. At this time, the logic states corresponding to the outputs CK0 to CK6 of the delay units DU [0] to DU [6] are latched in the latch circuits D_0 to D_6 of the latch unit 33.

  Further, since the output Hold_C of the AND circuit of the latch unit 33 becomes Low at the third timing, the latch circuit D_7 is disabled, and the logic state corresponding to the output CK7 of the delay unit DU [7] is changed to the latch unit 33. Is latched by the latch circuit D_7. The count unit 34 latches the count value when the latch circuit D_7 stops its operation. Data corresponding to the time interval from the first timing to the second timing is obtained by the logic state latched by the latch unit 33 and the count value latched by the count unit 34. The latched data is output to, for example, a subsequent arithmetic unit (not shown), and processing such as binarization is performed.

  In the above operation, since the latch circuits D_0 to D_6 operate only during the period from the second timing to the third timing, current consumption in the latch unit 33 can be reduced. Therefore, the current consumption of the time detection circuit can be reduced.

  In this example, the power consumption is reduced by controlling the operations of the latch circuits D_0 to D_6 constituting the latch unit 33. However, for example, a configuration for controlling the latch circuits D_1 to D_5 may be used. . Moreover, it is not necessary to restrict to this.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. FIG. 7 shows an example of the configuration of the solid-state imaging device according to the present embodiment. The configuration diagram of this example will be described below. 7 includes an imaging unit 2, a vertical selection unit 12, a read current source unit 5, an analog unit 6, a delay unit 18, a ramp unit 19, a column processing unit 15, a horizontal selection unit 14, and a calculation unit 17. The control unit 20 is configured.

  In the imaging unit 2, a plurality of unit pixels 3 that generate and output a signal corresponding to the magnitude of incident electromagnetic waves are arranged in a matrix. The vertical selection unit 12 selects each row of the imaging unit 2. The read current source unit 5 reads the signal from the imaging unit 2 as a voltage signal. The analog unit 6 performs analog processing on the signal read from the imaging unit 2. The delay unit 18 corresponds to the delay unit 30 described in the second and third embodiments, and includes an annular delay circuit 8. The ramp unit 19 generates a ramp wave as a reference signal that increases or decreases over time. The column processing unit 15 is connected to the lamp unit 19 via a reference signal line 119. The horizontal selection unit 14 reads the data generated by the column processing unit 15 to the horizontal signal line 117. The arithmetic unit 17 is connected to the horizontal signal line 117. The control unit 20 controls each unit.

  In FIG. 7, for the sake of simplicity, the case of the imaging unit 2 composed of unit pixels 3 of 4 rows × 6 columns is described, but in reality, each row or each column of the imaging unit 2 has several tens of Tens of thousands of unit pixels 3 are arranged. Although not shown, the unit pixel 3 constituting the imaging unit 2 is configured by a photoelectric conversion element such as a photodiode / photogate / phototransistor and a transistor circuit.

  In this system configuration, peripheral drive systems and signal processing systems that drive and control each unit pixel 3 of the imaging unit 2, that is, a vertical selection unit 12, a horizontal selection unit 14, a column processing unit 15, a calculation unit 17, a delay unit 18, Peripheral circuits such as the lamp unit 19 and the control unit 20 are integrally formed with the imaging unit 2 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique.

  Below, a more detailed description of each part is given. In the imaging unit 2, unit pixels 3 are arranged two-dimensionally by 4 rows and 6 columns, and row control lines 11 are wired for each row with respect to the pixel array of 4 rows and 6 columns. Each one end of the row control line 11 is connected to each output end corresponding to each row of the vertical selection unit 12. The vertical selection unit 12 includes a shift register or a decoder, and controls the row address and row scanning of the imaging unit 2 via the row control line 11 when driving each unit pixel 3 of the imaging unit 2. A vertical signal line 13 is wired for each column with respect to the pixel array of the imaging unit 2.

  The read current source unit 5 is configured using, for example, an NMOS transistor. A vertical signal line 13 from the imaging unit 2 is connected to the drain terminal, a desired voltage is appropriately applied to the control terminal, and a source terminal is connected to GND. As a result, a signal from the unit pixel 3 is output as a voltage mode. Although the case where an NMOS transistor is used as the current source has been described, the present invention is not limited to this.

  Although the detailed description is omitted, the analog unit 6 is the difference between the signal level immediately after the pixel reset (reset level) and the true signal level with respect to the voltage mode pixel signal input via the vertical signal line 13. By performing the processing, noise components called FPN (= Fixed Pattern Noise) and reset noise, which are fixed variations for each pixel, are removed. An AGC (= Auto Gain Control) circuit having a signal amplification function may be provided as necessary.

  The column processing unit 15 includes, for example, an ADC unit 16 provided for each pixel column of the imaging unit 2, that is, for each vertical signal line 13, and passes through the vertical signal line 13 from each unit pixel 3 of the imaging unit 2 for each pixel column. The read analog pixel signal is converted into digital data. In this example, the ADC unit 16 is arranged with a one-to-one correspondence with the pixel column of the imaging unit 2, but this is only an example and is limited to this arrangement relationship. is not. For example, one ADC unit 16 may be arranged for a plurality of pixel columns, and the one ADC unit 16 may be used in a time-sharing manner between the plurality of pixel columns. The column processing unit 15, along with a ramp unit 19, a delay unit 18, and a calculation unit 17 which will be described later, converts an analog pixel signal read from the unit pixel 3 in the selected pixel row of the imaging unit 2 into digital pixel data. Make up the vessel.

  The delay unit 18 is not limited to a VCO (= Voltage Controlled Oscillator) circuit that is a symmetric oscillation circuit that is an annular delay circuit, but the annular delay circuit itself is composed of an odd number of delay units as in the symmetric oscillation circuit. A so-called asymmetric oscillation circuit whose output is equivalently even (especially a power of 2) may be used. Furthermore, the ring delay circuit itself is composed of an even number (especially a power of 2) delay units, and the output (terminal) of the lower logic state is an even number (especially a power of 2) RDL (= Ring Delay Line) ) The circuit or ring delay circuit itself is composed of an even number (especially a power of 2) delay units, and the output of the final stage of the fully differential inverting circuit constituting the delay unit is the inverse of the input of the first stage. A so-called fully differential oscillation circuit configured by being fed back to the side may be used. An annular delay circuit is suitable as the delay unit 18, but it is not necessary to be limited thereto.

  The ramp unit 19 is constituted by, for example, an integration circuit, generates a so-called ramp wave whose level changes in an inclined manner as time elapses according to the control by the control unit 20, and the voltage comparison unit 131 via the reference signal line 119. To one of the input terminals. The ramp unit 19 is not limited to the one using an integration circuit, and a DAC circuit may be used. However, in the case of adopting a configuration in which a ramp wave is generated digitally using a DAC circuit, it is necessary to make the step of the ramp wave fine or a configuration equivalent thereto.

  The horizontal selection unit 14 includes a shift register or a decoder, and controls the column address and column scanning of the ADC unit 16 of the column processing unit 15. Under the control of the horizontal selection unit 14, the digital data AD-converted by the ADC unit 16 is sequentially read out to the horizontal signal line 117.

  The arithmetic unit 17 performs code conversion such as binarization based on the digital data output to the horizontal signal line 117, and outputs binarized digital data. Further, the calculation unit 17 may incorporate signal processing functions such as black level adjustment, column variation correction, and color processing. Furthermore, n-bit parallel digital data may be converted into serial data and output.

  The control unit 20 is a TG (= Timing Generator: TG) that supplies a clock signal and a pulse signal of a predetermined timing necessary for the operation of each unit such as the ramp unit 19, the delay unit 18, the vertical selection unit 12, the horizontal selection unit 14, and the calculation unit 17. (Timing generator) functional block and a functional block for communicating with the TG. Note that the control unit 20 may be provided as a separate semiconductor integrated circuit independent of other functional elements such as the imaging unit 2, the vertical selection unit 12, and the horizontal selection unit 14. In that case, an imaging device which is an example of a semiconductor system is constructed by the imaging device including the imaging unit 2, the vertical selection unit 12, the horizontal selection unit 14, and the like and the control unit 20. This imaging device may be provided as an imaging module in which peripheral signal processing, a power supply circuit, and the like are also incorporated.

  Next, the configuration of the ADC unit 16 will be described. Each of the ADC units 16 compares the analog pixel signal read from each unit pixel 3 of the imaging unit 2 through the vertical signal line 13 with a ramp wave supplied from the ramp unit 19 for AD conversion, thereby obtaining a pixel signal. A time interval having a size (pulse width) in the time axis direction corresponding to the size of is generated. Then, AD conversion is performed by using data corresponding to the time interval as digital data corresponding to the magnitude of the pixel signal.

  Hereinafter, details of the configuration of the ADC unit 16 will be described. The ADC unit 16 is provided for each column. In FIG. 7, six ADC units 16 are provided. The ADC units 16 in each column have the same configuration. The ADC unit 16 includes a voltage comparison unit 131, a latch control unit 132, a latch unit 133, and a column counter 134.

  The voltage comparison unit 131, which is an example of a comparison unit, generates a signal voltage corresponding to an analog pixel signal output from the unit pixel 3 of the imaging unit 2 through the vertical signal line 13, and a ramp wave supplied from the ramp unit 19. By comparing, the magnitude of the pixel signal is converted into a time interval (pulse width) which is information in the time axis direction. The comparison output of the voltage comparison unit 131 becomes, for example, a low level when the lamp voltage is larger than the signal voltage, and becomes a high level when the lamp voltage is less than or equal to the signal voltage. Based on the comparison output of the voltage comparison unit 131, the latch control unit 132 generates a control signal for controlling the latch unit 133 and the column counter 134.

  The latch unit 133 includes latch circuits D_0 to D_6 and a latch circuit D_7. The latch circuits D_0 to D_6 constituting the latch unit 133 are enabled at a timing (second timing) when the comparison output of the voltage comparison unit 131 is received and the comparison output is inverted. After a predetermined time has elapsed from the second timing (third timing), each of the latch circuits D_0 to D_7 of the latch unit 133 is disabled, so that the logic state generated by the delay unit 18 is latched ( Hold / remember). The column counter 134 performs counting based on the output of the latch circuit D_7 of the latch unit 133. Here, the column counter 134 is assumed to be a counter circuit having a latch function for holding the logical state of the column counter 134.

  Here, the lower data signal indicated by the logic state of the latch unit 133 is, for example, 8-bit data. Further, the upper data signal indicated by the count result of the column counter 134 is, for example, 10-bit data. The 10 bits are merely an example, and the number of bits may be less than 10 bits (for example, 8 bits) or the number of bits may be more than 10 bits (for example, 12 bits).

  Next, the operation of this example will be described. Here, a description of a specific operation of the unit pixel 3 is omitted, but as is well known, the unit pixel 3 outputs a reset level and a signal level. The output reset level and signal level are output as a pixel output signal subjected to CDS processing in the analog unit 6.

  AD conversion is performed as follows. For example, a ramp wave that falls with a predetermined inclination is compared with a pixel output signal, and a point in time when the pixel output signal and the ramp voltage of the ramp wave coincide with each other from the time point (first timing) related to the start of this comparison process ( The period from the second timing) to the end of the predetermined time (third timing) is the output from the annular delay circuit (for example, CK7, that is, the output of the latch circuit D_7 of the latch unit 33 shown in FIG. 5) And a logical state of a multi-phase clock (CK0 to CK7, that is, corresponding to the output Q of the latch circuit D_0 to D_7 of the latch unit 33 shown in FIG. 5) having a constant phase difference, By using and measuring, digital data corresponding to the pixel output signal is obtained. The reset level including the noise of the pixel signal is read out from each unit pixel 3 in the selected row of the imaging unit 2 in the first reading operation, and then AD conversion is performed. Then, the signal level is read out in the second reading operation to perform AD conversion. Digital data corresponding to the pixel output signal may be obtained by performing the CDS operation after conversion. Moreover, it is not necessary to restrict to this.

  After the pixel output signal output from the unit pixel 3 of the arbitrary pixel row to the vertical signal line 13 is stabilized, the control unit 20 supplies the ramp unit 19 with control data for ramp wave generation. In response to this, the ramp unit 19 outputs a ramp wave that changes in a ramp shape over time as a comparison voltage applied to one input terminal of the voltage comparison unit 131 as a whole. The voltage comparison unit 131 starts comparison between the ramp wave and the pixel output signal (first timing). Further, the control unit 20 changes the start pulse output to the annular delay circuit 8 from Low to High at the first timing.

  The voltage comparison unit 131 compares the ramp wave supplied from the ramp unit 19 with the pixel output signal, and outputs a comparison output when both voltages substantially match (second timing). The comparison output is further inverted or delayed (third timing). At the second timing, the latch circuits D_0 to D_6 of the latch unit 133 are enabled based on the comparison output of the voltage comparison unit 131, and at the third timing, the latch circuits D_0 to D_7 of the latch unit 133 are disabled. The logic state corresponding to the output from the delay unit 18 is latched. The column counter 134 latches the count value when the latch circuit D_7 of the latch unit 133 is stopped. Thereby, digital data (data signal) corresponding to the pixel output signal is obtained. The control unit 20 stops the supply of control data to the ramp unit 19 and the output from the delay unit 18 when a predetermined period has elapsed. As a result, the ramp unit 19 stops generating the ramp wave.

  Thereafter, the digital data is output by the horizontal selection unit 14 via the horizontal signal line 117 and transferred to the calculation unit 17. In the arithmetic unit 17, binary data is obtained by performing binarization processing. Note that the calculation unit 17 may be built in the column processing unit 15.

  In the above operation, since the latch circuits D_0 to D_6 operate only during the period from the second timing to the third timing, current consumption in the latch unit 33 can be reduced. Therefore, the consumption current of the AD converter, and hence the consumption current of the solid-state imaging device can be reduced.

  In this example, the power consumption is reduced by controlling the operations of the latch circuits D_0 to D_6 constituting the latch unit 133. However, for example, a configuration for controlling the latch circuits D_1 to D_5 may be used. . Moreover, it is not necessary to restrict to this.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  2 ... Imaging unit, 5 ... Read current source unit, 6 ... Analog unit, 8 ... Circular delay circuit, 12 ... Vertical selection unit, 14 ... Horizontal selection unit, 15 ..Column processing section, 16 ... ADC section, 17 ... calculation section, 18, 30 ... delay section, 19 ... ramp section (reference signal generation section), 20 ... control section, 31 ... Comparison part, 32 ... Signal generation part (latch control part), 33,133 ... Latch part, 34 ... Count part (count latch part), 131 ... Voltage comparison part (comparison part) ), 132... Latch control section, 134... Column counter (count latch section)

Claims (5)

A delay unit having a plurality of delay units for delaying and outputting an input signal, and starting an operation at a first timing related to the input of the first pulse;
A latch unit for latching a logic state of the plurality of delay units;
A counting unit that counts based on a clock output from any of the plurality of delay units;
A latch control unit that enables the latch unit at a second timing related to the input of the second pulse, and causes the latch unit to execute a latch at a third timing after a predetermined time has elapsed from the second timing;
A time detection circuit.   2. The time detection circuit according to claim 1, wherein the delay unit is an annular delay circuit in which the plurality of delay units are connected in an annular shape. A comparator that outputs a predetermined analog signal and a reference signal that increases or decreases with the passage of time and outputs a comparison signal when the reference signal satisfies a predetermined condition with respect to the analog signal;
The comparison signal is input to the latch control unit,
The first timing relates to a timing at which the analog signal is input to the comparison unit,
The second timing relates to a timing at which the comparison signal is input to the latch control unit.
The time detection circuit according to claim 1 or claim 2, wherein A time detection circuit according to claim 3;
A reference signal generator for generating the reference signal;
An arithmetic unit that generates a digital signal based on the logic state latched in the latch unit and the count state in the count unit;
AD converter with An imaging unit in which a plurality of pixels that output pixel signals according to the magnitude of incident electromagnetic waves are arranged in a matrix,
The AD converter according to claim 4, wherein the analog signal corresponding to the pixel signal is input;
Have
The comparison unit, the latch unit, the count unit, and the latch control unit are provided for each column or a plurality of columns of the pixels constituting the imaging unit.

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