JP2013102381A - Ad converter circuit and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AD converter circuit and an imaging apparatus capable of improving the resolution of digital data obtained by AD conversion, without regard to the frequency of a count clock.SOLUTION: A latch unit 108 allows clock signals from a clock generator 18 to pass therethrough during comparison processing is performed by a comparator 109 and latches the clock signals with the timing of the completion of the comparison processing. A column count unit 103 counts the clock signals from the clock generator 18 and furthermore counts counting signals generated on the basis of the logical state of the clock signals latched by the latch unit 108.

Description

  The present invention relates to an AD conversion circuit and an imaging device including the AD conversion circuit.

  As an example using a conventional AD conversion circuit, configurations described in Patent Document 1 and Non-Patent Document 1 are known. First, the configuration and operation of an AD converter circuit according to a conventional example will be described. FIG. 18 shows a configuration of a (C) MOS imaging device using an AD converter circuit according to a conventional example. 18 includes an imaging unit 1002, a vertical selection unit 1012, a read current source unit 1005, an analog unit 1006, a clock generation unit 1018, a ramp unit 1019, a column processing unit 1015, a horizontal selection unit 1014, and an output unit 1017. The control unit 1020 is configured.

  The control unit 1020 controls each unit such as the vertical selection unit 1012, the read current source unit 1005, the analog unit 1006, the clock generation unit 1018, the ramp unit 1019, the column processing unit 1015, the horizontal selection unit 1014, and the output unit 1017. The imaging unit 1002 is configured by unit pixels 1003 having photoelectric conversion elements arranged in a matrix, generates a pixel signal corresponding to the magnitude of incident electromagnetic waves, and outputs to a vertical signal line 1013 provided for each column. Output.

  The vertical selection unit 1012 controls the row address and row scanning of the imaging unit 1002 via the row control line 1011 when driving each unit pixel 1003 of the imaging unit 1002. The horizontal selection unit 1014 controls the column address and column scanning of the column AD conversion unit 1016 of the column processing unit 1015. The read current source unit 1005 is a current source for reading a pixel signal from the imaging unit 1002 as a voltage signal. The analog unit 1006 performs amplification or the like as necessary.

  The column processing unit 1015 includes a column AD conversion unit 1016 including a comparison unit 1109 and a column count unit 1103 for each column of the unit pixels 1003. The column AD conversion unit 1016 converts an analog signal that is a pixel signal output for each column from each unit pixel 1003 of the imaging unit 1002 into digital data and outputs the digital data. The clock generation unit 1018 generates and outputs a clock signal having a predetermined frequency.

  The ramp unit 1019 generates a ramp wave whose level changes in an inclined manner with the passage of time, and outputs this ramp wave to one of the input terminals of the comparison unit 1109 as a reference signal. The clock signal from the clock generation unit 1018 is output to the column count unit 1103 of each column. A pixel signal is input from the unit pixel 1003 through the vertical signal line 1013 to the other input terminal of the comparison unit 1109 in each column AD conversion unit 1016 as an analog signal to be subjected to AD conversion. The unit pixel 1003 outputs a reset level and a signal level as pixel signals.

  The horizontal selection unit 1014 controls the column address and column scanning of each column AD conversion unit 1016 in the column processing unit 1015. Thus, the AD converted digital data is sequentially output to the output unit 1017 via the horizontal signal line.

  Next, the AD conversion operation according to the conventional example will be described. First, at the same time as the column count unit 1103 starts counting the clock signal output from the clock generation unit 1018, the ramp unit 1019 starts generating the ramp wave. Then, a pixel signal read from the unit pixel 1003 of each column and a common ramp wave whose level changes in synchronization with the count value of the column count unit 1103 are input to the comparison unit 1109 of each column.

  When the magnitude relationship between the two input signals to the comparison unit 1109 of a certain column is switched, the comparison output of the comparison unit 1109 is inverted, and the column count unit 1103 of that column holds the count value. Through the above operation, the pixel signal read from the pixel is AD-converted to a value (digital value) held in the column count unit 1103.

  The AD conversion method used in the above description is a type called a ramp type AD conversion (Ramp Run-up ADC), and according to a general AD conversion method classification, a counting ADC (counting type AD conversion) It is of a kind called. Using a ramp wave (lamp voltage) as a reference signal is equivalent to converting the voltage of an analog signal from a pixel into a time length, and further measuring the length of time using a clock signal with a fixed frequency. This name is used to realize AD conversion.

  In addition, in order to realize high-speed AD conversion, a clock generator that generates a clock signal having a higher frequency than the master clock is provided, and the high-speed clock signal generated by this clock generator is used as the count clock of the column count unit. As a result, the processing speed of the AD conversion process is not limited by the speed of the master clock.

JP 2005-347931 A

Takayuki Toyama et al., “A 17.7 Mpixel 120fps CMOS Image Sensor with 34.8Gb / s Readout,” Sony, Kanagawa, Japan ISSCC2011 / SESSION23 / IMAGE SENSORS / 23.11

The processing speed of the above-described AD conversion processing is limited by the count clock, and it is necessary to prepare a higher-speed clock signal in order to realize higher-speed AD conversion. Here, a problem will be described by taking as an example a case where the number of pixels is 8 million pixels and the frame rate is 15 fps (frame / second) as a solid-state imaging device. For ease of explanation, if the pixel array of 8 million pixels is 2000 rows x 4000 columns vertically and horizontally, and there is no blanking period for further simplification, the number of rows from which pixel signals are read per second is It becomes as follows.
15 frames / second x 2000 lines / frame = 30K lines / second

  That is, the reading rate for one row is 30 KHz. Actually, when reading from an OB (= Optical Black) pixel or the like is considered, the reading rate of one row is considered to be about 50 KHz. When applying the ramp type AD conversion to the AD conversion process in which the pixel signal is read out at this readout rate, if the resolution is 10-bit AD conversion, it is necessary to compare 1024 times. It is necessary to change the count value of the counter at a frequency of about 50 MHz, which is a thousand times. If the resolution of AD conversion is 12 bits, the frequency necessary for the change in the counter count value is 200 MHz, which is four times that when the resolution is 10 bits. When the frame rate is 60 fps, the frequency of 800 MHz, which is four times higher, is required.

Currently, the frequency of a count clock of a solid-state imaging device using a lamp type AD conversion is generally about 300 to 400 MHz. If a count clock close to the GHz order is required, specifically, the following problems may occur.
(1) Even within a chip, it is difficult to generate a count clock close to the GHz order.
(2) Even if a count clock close to the GHz order can be generated, the column count units for the number of columns become a load, and the pixel columns arranged farther from the clock generation unit have longer wiring and longer time constants. Therefore, it is difficult to perform an accurate operation with the counter circuit.

  The present invention has been made in view of the above-described problems, and provides an AD conversion circuit and an imaging apparatus that can improve the resolution of digital data obtained by AD conversion regardless of the frequency of the count clock. With the goal.

  The present invention has been made to solve the above-described problem, and includes a reference signal generation unit that generates a reference signal that increases or decreases over time, an analog signal that is an object of AD conversion, and the reference signal. Comparing, a comparison unit that ends the comparison process at a timing when the reference signal satisfies a predetermined condition with respect to the analog signal, a clock generation unit that outputs a clock signal of a predetermined frequency, and during the comparison process, A latch unit that passes the clock signal output from the clock generation unit and latches the clock signal at a timing related to the end of the comparison process; and a counter circuit of k (k is a natural number of 3 or more) bits The first count signal based on the clock signal output from the latch unit is input to the jth (j is a natural number of j <k) bit of the counter circuit, and the latch A second count signal, which is a pulse signal generated based on the logic state of the clock signal latched in the unit, is input to the i (i is a natural number of i <j) bit of the counter circuit, and A counting unit that counts the count signal of 1 and the second count signal, and the latch unit latches the clock signal at a timing related to the end of the comparison process according to the first analog signal Thereafter, the clock signal is latched at a timing related to the end of the comparison process according to a second analog signal, and the count unit performs a first count process according to the first analog signal, and After inverting each bit constituting the count value obtained by the counting process of 1, the second analog signal and the second analog signal are subjected to the second counting process according to the second analog signal. Difference from analog signal It is an AD conversion circuit that outputs digital data according to minutes.

  Further, the present invention compares a reference signal generation unit that generates a reference signal that increases or decreases with time, an analog signal to be subjected to AD conversion, and the reference signal, and the reference signal is converted into the analog signal. A comparison unit that ends the comparison process at a timing that satisfies a predetermined condition, a clock generation unit that outputs a clock signal having a predetermined frequency, and the clock signal that is output from the clock generation unit during the comparison process The clock signal output from the latch unit, and a latch unit that latches the clock signal at a timing related to the end of the comparison process, and a counter circuit of k (k is a natural number of 3 or more) bits Is input to the jth bit (j is a natural number of j <k) of the counter circuit, and the logic of the clock signal latched in the latch unit is input. The second count signal, which is a pulse signal generated based on the logical state, is input to the i (i is a natural number of i <j) bit of the counter circuit, and the first count signal and the second count signal A counting unit that counts the counting signal, and the latch unit latches the clock signal at a timing related to the end of the comparison processing according to the first analog signal and then responds to the second analog signal. The clock signal is latched at a timing related to the end of the comparison process, and the counting unit performs a first counting process according to the first analog signal in either the down-count mode or the up-count mode. And performing the second counting process according to the second analog signal in one of the down-count mode and the up-count mode, so that the first analog signal Is an AD conversion circuit that outputs digital data corresponding to the difference between said second analog signal.

  Further, in the present invention, a plurality of pixels having photoelectric conversion elements are arranged, and the plurality of pixels output a signal corresponding to a reset level as a first pixel signal, and according to the magnitude of incident electromagnetic waves. An image pickup unit that outputs a signal as a second pixel signal, and the AD conversion circuit described above, and an analog signal corresponding to the first pixel signal is the first analog signal, and the second pixel signal The image pickup apparatus is characterized in that an analog signal corresponding to the second analog signal is used as the second analog signal.

  According to the present invention, in addition to counting the first count signal based on the clock signal output from the latch unit, the pulse signal generated based on the logic state of the clock signal latched in the latch unit By counting the second count signal, the resolution of digital data obtained by AD conversion can be improved regardless of the frequency of the count clock.

1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a column AD conversion unit in the first embodiment of the present invention. 5 is a timing chart showing the operation of the column AD conversion unit in the first embodiment of the present invention. 5 is a timing chart showing the operation of the column AD conversion unit in the first embodiment of the present invention. 5 is a timing chart showing the operation of the column AD conversion unit in the first embodiment of the present invention. 5 is a timing chart showing the operation of the column AD conversion unit in the first embodiment of the present invention. 1 is a circuit diagram showing a configuration of a binary counter circuit in a first embodiment of the present invention. 3 is a timing chart showing the operation of the binary counter circuit in the first embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a column AD conversion unit in a second embodiment of the present invention. 10 is a timing chart showing the operation of the column AD conversion unit in the second embodiment of the present invention. 10 is a timing chart showing the operation of the column AD conversion unit in the second embodiment of the present invention. 10 is a timing chart showing the operation of the column AD conversion unit in the second embodiment of the present invention. 10 is a timing chart showing the operation of the column AD conversion unit in the second embodiment of the present invention. 10 is a timing chart showing the operation of the column AD conversion unit in the third embodiment of the present invention. 10 is a timing chart showing the operation of the column AD conversion unit in the third embodiment of the present invention. 10 is a timing chart showing the operation of the column AD conversion unit in the third embodiment of the present invention. 10 is a timing chart showing the operation of the column AD conversion unit in the third embodiment of the present invention. It is a block diagram which shows the structure of the conventional imaging device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows an example of the configuration of the (C) MOS imaging device according to the present embodiment. 1 includes an imaging unit 2, a vertical selection unit 12, a read current source unit 5, a clock generation unit 18, a ramp unit 19 (reference signal generation unit), a column processing unit 15, a horizontal selection unit 14, and an output The unit 17 and the control unit 20 are configured.

  In the imaging unit 2, a plurality of unit pixels 3 that generate and output a signal corresponding to the magnitude of incident electromagnetic waves are arranged in a matrix. The vertical selection unit 12 selects each row of the imaging unit 2. The read current source unit 5 reads the signal from the imaging unit 2 as a voltage signal. Although not described in detail, the analog unit 6 includes an AGC (= Auto Gain Control) circuit having a signal amplification function as necessary. The clock generator 18 generates and outputs a clock signal having a predetermined frequency. The ramp unit 19 generates a reference signal (ramp wave) that increases or decreases over time. The column processing unit 15 is connected to the lamp unit 19 via a reference signal line. The horizontal selection unit 14 reads the AD-converted data to the horizontal signal line. The output unit 17 is connected to the horizontal signal line. The control unit 20 controls each unit.

  In FIG. 1, for the sake of simplicity, the case of the imaging unit 2 composed of 4 rows × 6 columns of unit pixels 3 is described, but in reality, each row and each column of the imaging unit 2 has several tens of Tens of thousands of unit pixels 3 are arranged. Although not shown, the unit pixel 3 constituting the imaging unit 2 is configured by a photoelectric conversion element such as a photodiode / photogate / phototransistor and a transistor circuit.

  Below, a more detailed description of each part is given. In the imaging unit 2, unit pixels 3 are arranged two-dimensionally by 4 rows and 6 columns, and row control lines 11 are wired for each row with respect to the pixel array of 4 rows and 6 columns. Each one end of the row control line 11 is connected to each output end corresponding to each row of the vertical selection unit 12. The vertical selection unit 12 includes a shift register or a decoder, and controls the row address and row scanning of the imaging unit 2 via the row control line 11 when driving each unit pixel 3 of the imaging unit 2. A vertical signal line 13 is wired for each column with respect to the pixel array of the imaging unit 2.

  The column processing unit 15 includes, for example, a column AD conversion unit 16 provided for each pixel column of the imaging unit 2, that is, for each vertical signal line 13, and the vertical signal line for each pixel column from each unit pixel 3 of the imaging unit 2. The analog pixel signal read out via 13 is converted into digital data. In this example, the column AD conversion unit 16 is arranged with a one-to-one correspondence with the pixel columns of the imaging unit 2, but this is only an example and is limited to this arrangement relationship. It is not something. For example, one column AD conversion unit 16 may be arranged for a plurality of pixel columns, and the one column AD conversion unit 16 may be used in a time-sharing manner between the plurality of pixel columns. The column processing unit 15 includes an analog-to-digital conversion unit that converts an analog pixel signal read from the unit pixel 3 in the selected pixel row of the imaging unit 2 into digital pixel data together with a ramp unit 19 and a clock generation unit 18 to be described later. It is composed. Details of the column processing unit 15, particularly the column AD conversion unit 16, will be described later.

  The ramp unit 19 is configured by, for example, an integration circuit, and generates a so-called ramp wave whose level changes in an inclined manner as time elapses according to control by the control unit 20, and is input to the comparison unit 109 via a reference signal line. Supply to one of the terminals. The ramp unit 19 is not limited to the one using an integration circuit, and a DAC circuit may be used. However, in the case of adopting a configuration in which a ramp wave is generated digitally using a DAC circuit, it is necessary to make the step of the ramp wave fine or a configuration equivalent thereto.

  The horizontal selection unit 14 includes a shift register or a decoder, and controls the column address and column scanning of the column AD conversion unit 16 of the column processing unit 15. In accordance with the control by the horizontal selection unit 14, the AD data converted by the column AD conversion unit 16 is sequentially read out to the horizontal signal line.

  The output unit 17 outputs binarized digital data. In addition to the buffering function, the output unit 17 may include a signal processing function such as black level adjustment, column variation correction, and color processing. Furthermore, n-bit parallel digital data may be converted into serial data and output.

  The control unit 20 is a TG (= Timing Generator) that supplies a clock required for the operation of each unit such as the ramp unit 19, the clock generation unit 18, the vertical selection unit 12, the horizontal selection unit 14, and the output unit 17, and a pulse signal at a predetermined timing. : Timing generator) and a functional block for communicating with the TG.

  Next, the configuration of the column AD conversion unit 16 will be described. Each of the column AD conversion units 16 compares an analog pixel signal read from each unit pixel 3 of the imaging unit 2 via the vertical signal line 13 with a ramp wave for AD conversion given from the ramp unit 19. Thus, a pulse signal having a magnitude (pulse width) in the time axis direction corresponding to each magnitude of the reset level (reference level) and the signal level is generated. Then, AD conversion is performed by using data corresponding to the pulse width period of the pulse signal as digital data corresponding to the magnitude of the pixel signal.

  Details of the configuration of the column AD conversion unit 16 will be described below. The column AD conversion unit 16 is provided for each column, and in FIG. 1, six column AD conversion units 16 are provided. The column AD conversion unit 16 of each column has the same configuration. The column AD conversion unit 16 includes a comparison unit 109, a latch unit 108, and a column count unit 103 (count unit). Here, the column count unit 103 is assumed to be a binary counter circuit having a latch function.

  The comparison unit 109 compares the signal voltage corresponding to the analog pixel signal output from the unit pixel 3 of the imaging unit 2 via the vertical signal line 13 with the ramp voltage of the ramp wave supplied from the ramp unit 19. Thus, the magnitude of the pixel signal is converted into information in the time axis direction (pulse width of the pulse signal). The comparison output of the comparison unit 109 becomes, for example, a high level (H level) when the lamp voltage is higher than the signal voltage, and becomes a low level (L level) when the lamp voltage is equal to or lower than the signal voltage.

  The latch unit 108 passes the clock signal output from the clock generation unit 18 as it is, receives the comparison output of the comparison unit 109, and outputs the clock signal output from the clock generation unit 18 at the timing when the comparison output is inverted. Latch (hold / store). The column count unit 103 performs counting processing (counting) based on the clock signal output via the latch unit 108, and further performs counting processing (counting) based on the logic state of the clock signal latched by the latch unit 108. Do. Here, the column count unit 103 is configured by a counter circuit of 3 bits or more, for example, an 8-bit counter circuit. These are merely examples, and need not be limited to these.

  Next, the operation of this example will be described. Here, a description of a specific operation of the unit pixel 3 is omitted, but as is well known, the unit pixel 3 outputs a reset level and a signal level.

  AD conversion is performed as follows. For example, a ramp wave that falls at a predetermined inclination is compared with a reset level or each signal level voltage that is a pixel signal from the unit pixel 3, and the reset level or The clock signal output through the latch unit 108 is counted until each voltage at the signal level matches the ramp wave (ramp voltage), and further based on the logic state of the clock signal latched in the latch unit 108. By counting the count signal, digital data corresponding to each magnitude of the reset level or the signal level is obtained.

  Here, from each unit pixel 3 in the selected row of the imaging unit 2, the reset level including the noise of the pixel signal is read out as an analog pixel signal in the first reading operation, and then in the second reading operation. The signal level is read out. Then, the reset level and the signal level are input to the column AD conversion unit 16 through the vertical signal line 13 in time series. Note that the signal level may be read by the first read operation, and the reset level may be read by the second read operation thereafter. Hereinafter, details of the first and second read operations and the subsequent subtraction (CDS process) will be described. Here, it is assumed that the count mode of the column count unit 103 is the down-count mode, and the column count unit 103 performs counting at the timing of the falling edge of the count clock.

<First reading>
After the first reading from the unit pixel 3 in the arbitrary pixel row to the vertical signal line 13 is stabilized, the control unit 20 supplies the ramp unit 19 with control data for ramp wave generation. In response to this, the ramp unit 19 outputs a ramp wave whose waveform changes in a ramp shape over time as a comparison voltage applied to one input terminal of the comparison unit 109. The comparison unit 109 compares this ramp wave with the reset level. During this time, the column count unit 103 performs counting using the clock signal output from the clock generation unit 18 output via the latch unit 108 as a count clock. It is preferable that the counting operation start timing in the column count unit 103 and the ramp wave output start timing are substantially the same, but the present invention is not limited to this.

  The comparison unit 109 compares the ramp wave supplied from the ramp unit 19 with the reset level, and inverts the comparison output when both voltages substantially match (first timing). At the first timing, the latch unit 108 holds the clock signal output from the clock generation unit 18 as the first clock signal. The control unit 20 stops the supply of control data to the ramp unit 19 and the output of the clock signal from the clock generation unit 18 when a predetermined period elapses. As a result, the ramp unit 19 stops generating the ramp wave.

  Subsequently, the column count unit 103 generates a count signal composed of a predetermined number of pulse signals according to the logic state of the first clock signal held in the latch unit 108, and uses the generated count signal as a count clock. Count. Thereafter, the value of each bit held by the column count unit 103 is inverted. Thereby, the initial value of the column count unit 103 in the second reading is set.

<Second reading>
Subsequently, at the time of the second reading, a signal level corresponding to the amount of incident light for each unit pixel 3 is read, and the same operation as the first reading is performed. After the second reading from the unit pixel 3 of the arbitrary pixel row to the vertical signal line 13 is stabilized, the control unit 20 supplies the ramp unit 19 with control data for ramp wave generation. In response to this, the ramp unit 19 outputs a ramp wave whose waveform changes in a ramp shape over time as a comparison voltage applied to one input terminal of the comparison unit 109. The comparison unit 109 compares the ramp wave with the signal level. During this time, the column count unit 103 performs counting using the clock signal output from the clock generation unit 18 output via the latch unit 108 as a count clock. It is preferable that the counting operation start timing in the column count unit 103 and the ramp wave output start timing are substantially the same, but the present invention is not limited to this.

  The comparison unit 109 compares the ramp wave supplied from the ramp unit 19 with the signal level, and inverts the comparison output when the two voltages substantially match (second timing). At the second timing, the latch unit 108 holds the clock signal output from the clock generation unit 18 as the second clock signal. The control unit 20 stops the supply of control data to the ramp unit 19 and the output of the clock signal from the clock generation unit 18 when a predetermined period elapses. As a result, the ramp unit 19 stops generating the ramp wave.

  Subsequently, the column count unit 103 generates a count signal composed of a predetermined number of pulse signals according to the logic state of the second clock signal held in the latch unit 108, and uses the generated count signal as a count clock. Count. Thereby, subtraction (CDS processing) between the reset level and the signal level is performed.

  As described above, digital data corresponding to the difference between the reset level and the signal level is obtained. Finally, the value of each bit constituting the digital data held by the column count unit 103 is inverted, and the inverted digital data is transferred by the horizontal selection unit 14 to the output unit 17 via the horizontal signal line. .

  As described above, the column count unit 103 uses the clock signal (first count signal) output from the clock generation unit 18 output via the latch unit 108 at the time of the first read and the second read as the count clock. After counting, the count signal (second count signal) generated according to the logic state of the clock signal held in the latch unit 108 is used as a count clock. In the prior art, digital data was obtained by counting based on the first count signal, but in the present embodiment, digital data is obtained by counting based on the second count signal in addition to counting based on the first count signal. It has gained. By performing counting based on the second count signal, the resolution of the digital data can be improved.

  Next, details of each component of the column AD conversion unit 16 will be described. FIG. 2 shows an example of a detailed configuration for further explaining the column AD conversion unit 16 of FIG. Hereinafter, the configuration shown in FIG. 2 will be described. 2 correspond to the respective components in the column AD conversion unit 16 shown in FIG. 1, and the latch circuit D_0 that constitutes the latch unit 108, the switching unit MUX, and the counter that constitutes the column count unit 103. Circuits C_0 to C_7 are provided. The ramp unit 19 and the clock generation unit 18 in FIG. 1 and the column AD conversion unit 16 shown in FIG. 2 are examples of the AD conversion circuit of the present invention.

  The latch circuit D_0 outputs the clock signal CLK output from the clock generation unit 18 as it is, and latches the clock signal CLK based on the comparison output CO of the comparison unit 109. The counter circuits C_0 to C_7 perform counting based on the count clock input from the previous stage. The count value of the counter circuit C_0 constitutes the least significant bit (first bit) of the digital data, the counter circuits C_1 to C_6 constitute the second bit to the seventh bit of the digital data, respectively, and the count value of the counter circuit C_7 Configures the most significant bit (8th bit) of digital data. The switching unit MUX switches a signal input as a count clock to the counter circuit C_1 between the output of the latch circuit D_0 and the output of the counter circuit C_0.

  Control signals CNTEN_0 to CNTEN_7, control signals CMODE_0 to CMODE_7, and a control signal REV are input to the counter circuits C_0 to C_7. The control signals CNTEN_0 to CNTEN_7 are signals for controlling validity / invalidity of the count clock input from the previous stage. The control signals CMODE_0 to CMODE_7 are signals for switching the operation mode of the counter circuits C_0 to C_7 between a count mode for counting and a data protection mode for stopping the count and protecting the count value. The control signal REV is a signal that toggles the bit values of the counter circuits C_0 to C_7. In this example, the column counter 103 may be provided with a flag counter circuit for determining positive / negative. Details of the counter circuits C_0 to C_7 will be described later with reference to FIG.

  A control signal SEL is input to the switching unit MUX. The control signal SEL is a signal for switching the signal input to the counter circuit C_1. When the control signal SEL is set to the L state, a signal from the latch circuit D_0 is input to the counter circuit C_1, and when the control signal SEL is set to the H state, the counter circuit C_1 includes the counter circuit C_0 to Signal is input.

  Next, the operation of the configuration shown in FIG. 2 will be described using a specific example. In this description, a case where an 8-bit down counter circuit is used as the column count unit 103 will be described. When counting in the down count mode, for example, if the count is 0, the count value is 8'b0000_0000 (corresponding to 0), and for example, if the count is 7, the count value is 8'b1111_1001 (corresponding to -7).

  The notation of the count value will be described. “8′b” indicates that the count value is an 8-bit binary number. “0000_0000” indicates the output of the column count unit 103 (counter circuits C_0 to C_7).

  Hereinafter, an example in which subtraction (CDS processing) between the first pixel signal and the subsequent second pixel signal will be described. In this example, binary subtraction using 2's complement is performed. When the digital value obtained by AD converting the first pixel signal is A and the digital value obtained by AD converting the second pixel signal is B, the subtraction result to be obtained is B−A.

  In this example, since the column count unit 103 performs counting in the down-count mode, the column count unit 103 performs counting based on the first pixel signal at the first reading, and the count value after further inversion is digital. Corresponds to the value A. However, since 2's complement is used, it is necessary to add 1 to the count value. Subsequently, the column count unit 103 performs counting based on the second pixel signal at the time of the second reading, and the count value after further inversion corresponds to the digital value B-A. However, since 2's complement is used, it is necessary to add 1 to the count value. Since the change in value due to the 1 addition necessary after the inversion at the first reading and the 1 addition necessary after the inversion at the second reading is canceled, the 1 addition after the inversion is not performed.

  3 to 6 show waveforms of signals related to the operation of this example. 3 and 4 show the waveforms of the signals at the time of the first reading, and FIGS. 5 and 6 show the waveforms of the signals at the time of the second reading. In addition, clk indicates a master clock input to the control unit 20, clken indicates an enable signal of the clock generation unit 18, and CLK indicates a clock signal output from the clock generation unit 18. D represents the output of the latch circuit D_0, Q [0] to Q [7] represent the outputs of the counter circuits C_0 to C_7, and OUT [7: 0] represents the digital data.

  The operation of this example includes a first readout period in which the first pixel signal is read and AD converted, a second readout period in which the second pixel signal is read and AD converted, and a transfer period in which digital data is transferred. It consists of the operation of each period. The first readout period includes a reset period for resetting the latch circuit D_0 and the counter circuits C_0 to C_7, a signal readout period for reading the first pixel signal, and the counter circuits C_0 to C_7 receiving the clock signal from the clock generator 18. It includes a counting period for counting and an initial value setting period for setting an initial value at the second reading. In the initial value setting period, the latch data count for counting the clock signal based on the value held in the latch circuit D_0 by the counter circuits C_0 to C_7 and the data inversion for inverting the count value of the counter circuits C_0 to C_7 are performed.

  The second readout period includes a reset period for resetting the latch circuit D_0, a signal readout period for reading the second pixel signal, and a counting period for the counter circuits C_0 to C_7 to count the clock signal from the clock generator 18. Including. After the counting period at the time of the second reading, latch data count is performed in which the counter circuits C_0 to C_7 count the clock signal based on the value held in the latch circuit D_0.

  Here, the count value when the first pixel signal is counted is 31, the count value when the second pixel signal is counted is 42, and the first pixel signal is subtracted from the second pixel signal (CDS processing). A case where the calculated value 11 is obtained will be described.

<< First reading >>
The control signal SEL is set to the L state, the control signals CNTEN_0 to CNTEN_7 are set to the L state, and the control signals CMODE_0 to CMODE_7 are set to the L state. In the reset period, the control signals CMODE_0 to CMODE_7 are in the H state, and the latch circuit D_0 and the counter circuits C_0 to C_7 are reset. Further, after the control signals CNTEN_1 to CNTEN_7 are in the H state, the control signals CMODE_0 to CMODE_7 are in the L state.

  Since the control signal SEL is set to the L state, the count clock of the counter circuit C_1 is set to the output of the latch circuit D_0. Therefore, until the end of the comparison process, the clock signal from the clock generation unit 18 is input to the counter circuit C_1, and the counter circuit C_1 performs counting using the clock signal from the clock generation unit 18 as a count clock. The value held by the column count unit 103 at the start of the comparison process in the counting period subsequent to the signal reading period is 8'b0000_0000.

  In the counting period, the comparison output CO is inverted at the first timing that satisfies a predetermined condition (in the above-described operation, the first timing related to the comparison between the ramp wave supplied from the ramp unit 19 and the reset level), The logic state of the clock signal from the clock generation unit 18 at that time is held (first clock signal). At the same time, the counter circuits C_1 to C_7 stop counting. At this time, the value held by the latch circuit D_0 is 1'b1 (H state), and the value held by the column count unit 103 is 8'b1110_0010 (corresponding to -30).

  Subsequently, in the initial value setting period, the counter circuit C_1 performs counting based on the first clock signal held in the latch circuit D_0. After the control signals CMODE_0 to CMODE_7 change from the L state to the H state, the control signal SEL changes from the L state to the H state, and the control signals CMODE_0 to CMODE_7 change from the H state to the L state. Subsequently, the control signal CNTEN_0 changes from the L state to the H state, and further changes to the L state. Since the control signal SEL is set to the H state, the count clock of the counter circuit C_1 is set to the output of the counter circuit C_0. As a result, a count signal corresponding to the logic state of the first clock signal held in the latch circuit D_0 is generated, and a count value obtained by counting the generated count signal is held in the column count unit 103. In the case of this example, the value held by the latch circuit D_0 is 1'b1 (H state), and a one-pulse count signal is generated. At this time, the value held by the column count unit 103 is 8′b1110_0001 (corresponding to −31). Thereafter, the value held by the column count unit 103 is inverted. At this time, the value held by the column count unit 103 is 8'b0001_1110 (corresponding to 30).

<< Second reading >>
The control signal SEL is set to the L state, the control signals CNTEN_0 to CNTEN_7 are set to the L state, and the control signals CMODE_0 to CMODE_7 are set to the L state. In the reset period, the control signals CMODE_0 to CMODE_7 are in the H state, and the latch circuit D_0 is reset. Further, after the control signals CNTEN_1 to CNTEN_7 are in the H state, the control signals CMODE_0 to CMODE_7 are in the L state. Note that the counter circuits C_0 to C_7 are not reset.

  Since the control signal SEL is set to the L state, the count clock of the counter circuit C_1 is set to the output of the latch circuit D_0. Therefore, until the end of the comparison process, the clock signal from the clock generation unit 18 is input to the counter circuit C_1, and the counter circuit C_1 performs counting using the clock signal from the clock generation unit 18 as a count clock. The value held by the column count unit 103 at the start of the comparison process in the counting period subsequent to the signal reading period is 8'b0001_1110 (corresponding to 30).

  In the counting period, the comparison output CO is inverted at the second timing that satisfies a predetermined condition (in the above-described operation, the second timing related to the comparison between the ramp wave applied from the ramp unit 19 and the reset level), The logic state of the clock signal from the clock generation unit 18 at that time is held (second clock signal). At the same time, the counter circuits C_1 to C_7 stop counting. At this time, the value held by the latch circuit D_0 is 1'b0 (L state), and the value held by the column count unit 103 is 8'b1111_0100 (corresponding to -12).

  Subsequently, the counter circuit C_1 performs counting based on the second clock signal held in the latch circuit D_0. After the control signals CMODE_0 to CMODE_7 change from the L state to the H state, the control signal SEL changes from the L state to the H state, and the control signals CMODE_0 to CMODE_7 change from the H state to the L state. Subsequently, the control signal CNTEN_0 changes from the L state to the H state, and further changes to the L state. Since the control signal SEL is set to the H state, the count clock of the counter circuit C_1 is set to the output of the counter circuit C_0. As a result, a count signal corresponding to the second clock signal held in the latch circuit D_0 is generated, and a count value obtained by counting the generated count signal is held in the column count unit 103. In the case of this example, the value held by the latch circuit D_0 is 1'b0 (L state), and no count signal is generated. At this time, the value held by the column count unit 103 is 8′b1111_0100 (corresponding to −12).

  Finally, the count value of the column count unit 103 is inverted (omitted in FIGS. 5 and 6). At this time, the value held by the column count unit 103 is 8′b0000 — 1011 (corresponding to 11). In binary subtraction, it is necessary to add 1 after inverting the value, but since the value is also inverted at the first reading, the change in value caused by adding 1 after each inversion is canceled out. The Therefore, in this example, 1 is not added after inverting the value.

  In the transfer period, the digital data obtained by subtraction (CDS processing) is transferred to the output unit 17 by the horizontal selection unit 14 via the horizontal signal line. The inversion of the digital data at the second reading may be performed after the digital data is transferred to the output unit 17. By the above operation, binary data corresponding to the difference between the first pixel signal and the second pixel signal is obtained.

  In the above description, the column count unit 103 performs counting in the down-count mode, but may perform counting in the up-count mode. When the digital value obtained by AD converting the first pixel signal is A and the digital value obtained by AD converting the second pixel signal is B, the subtraction result to be obtained is B−A.

  When the column count unit 103 performs counting in the up-count mode, the column count unit 103 performs counting based on the first pixel signal at the time of the first reading, and the count value after further inversion is a digital value -A Correspond. However, since 2's complement is used, it is necessary to add 1 to the count value. Subsequently, the count value after the column count unit 103 performs counting based on the second pixel signal at the time of the second reading corresponds to the digital value B-A. Even when the column count unit 103 performs counting in the up-count mode, subtraction (CDS processing) between the first pixel signal and the second pixel signal can be performed as described above.

  Next, details of the binary counter circuit used in the column count unit 103 will be described. FIG. 7 shows an example of the configuration of a 1-bit counter circuit C_ * (*: 0 to 7) constituting the column count unit 103. The counter circuit C_ * shown in FIG. 7 includes a flip-flop DFF, an AND circuit AND1, an OR circuit OR1, and a changeover switch SW.

  The flip-flop circuit DFF is composed of a D flip-flop. The AND circuit AND1 outputs a pulse for validating / invalidating the count clock by performing an AND operation on the output signal CK [*-1] of the counter circuit C_ * in the preceding stage and the control signal CNTEN_ *. The OR circuit OR1 generates a pulse for inverting a bit by performing an OR operation on the output signal of the AND circuit AND1 and the control signal REV. In order to protect the bit value, the changeover switch SW is connected to the input terminal D and the output terminal Q based on the control signal CMODE_ * (corresponding to the control signal CMODE_ * in FIGS. 2 to 6), and the input terminal Switches between the state where D and the inverted output terminal QB are connected. When n counter circuits C_ * are connected, an n-bit counter circuit is configured. In addition, this structure is an example and is not restricted to this.

  Next, the operation of the counter circuit C_ *, particularly the bit inversion operation will be described. The timing chart of FIG. 8 shows the waveform of each signal related to the operation of the counter circuit C_ *, particularly the waveform of each signal related to the operation centered on the bit inversion operation. During the count operation, the control signal CMODE_ * is in the L state, the control signal CNTEN_ * is in the H state, and the control signal REV is in the L state.

  After the count operation, the control signal CMODE_ * becomes the H state. Thus, since the output terminal Q and the input terminal D of the counter circuit C_ * are connected, the output of the counter circuit C_ * is kept unchanged and each bit value is protected. Subsequently, the control signal CNTEN_ * becomes the L state. As a result, the count clock input is invalidated.

  Subsequently, the control signal CMODE_ * becomes the L state, and the inverted output terminal QB and the input terminal D of the counter circuit C_ * are connected. As a result, the state of the signal input to the input terminal D is inverted. Thereafter, the control signal REV changes from the L state to the H state, and further changes to the L state. When the control signal REV changes from the H state to the L state, the flip-flop circuit DFF holds the signal input to the input terminal D and outputs it from the output terminal Q. As described above, since the state of the signal input to the input terminal D is inverted when the control signal CMODE_ * becomes the L state, the control signal REV changes from the H state to the L state, so that the counter The output of the circuit C_ *, that is, each bit value is inverted.

  Thereafter, the control signal CMODE_ * becomes the H state. Thus, since the output terminal Q and the input terminal D of the counter circuit C_ * are connected, the output of the counter circuit C_ * is kept unchanged and each bit value is protected. Subsequently, the control signal CNTEN_ * becomes the H state. Thereby, the input of the count clock becomes valid. Finally, the control signal CMODE_ * is in the L state, and the inverted output terminal QB and the input terminal D of the counter circuit C_ * are connected. By the above operation, it is possible to perform the counting operation again with the value obtained by inverting each bit value as an initial value.

  As described above, according to the present embodiment, in addition to counting the clock signal from the clock generation unit 18, the column count unit 103 generates based on the logic state of the clock signal latched in the latch circuit D_0. The counted signal is counted. As described above, the value obtained by counting the logic state of the clock signal latched in the latch circuit D_0 is set to the value of the least significant bit of the column count unit 103, thereby increasing the count clock frequency without performing an AD conversion. The resolution of the obtained digital data can be improved by 1 bit. Further, by applying the AD conversion circuit of the present embodiment to an imaging device, a high-quality image can be obtained.

(Second embodiment)
Next, a second embodiment of the present invention will be described. The configuration of the (C) MOS imaging device according to the present embodiment is substantially the same as that of the first embodiment, but the configuration of the column count unit 103 of the column AD conversion unit 16 is different. The rest is substantially the same as in the first embodiment, and a description thereof will be omitted.

  Next, details of each component of the column AD conversion unit 16 will be described. FIG. 9 shows an example of a detailed configuration for further explaining the column AD conversion unit 16. Hereinafter, the configuration shown in FIG. 9 will be described. Each configuration shown in FIG. 9 corresponds to each configuration in the column AD conversion unit 16, and includes a latch circuit D_0 that constitutes the latch unit 108, a switching unit MUX, and counter circuits C_0 to C_8 that constitute the column count unit 103. Is provided. The ramp unit 19, the clock generation unit 18, and the column AD conversion unit 16 shown in FIG. 9 are examples of the AD conversion circuit of the present invention.

  In FIG. 9, the number of counter circuits and the arrangement position of the switching unit MUX are different from those in FIG. In FIG. 2, eight counter circuits are provided, but in FIG. 9, nine counter circuits are provided. Of the count values held by the counter circuits C_0 to C_8, digital data composed of the count values held by the counter circuits C_1 to C_8 corresponding to the upper 8 bits is the result of subtraction (CDS processing). The switching unit MUX switches the signal input as the count clock to the counter circuit C_2 between the output of the latch circuit D_0 and the output of the counter circuit C_1. When the control signal SEL is set to the L state, the signal from the latch circuit D_0 is input to the counter circuit C_2, and when the control signal SEL is set to the H state, the counter circuit C_2 includes the counter circuit C_1 to Signal is input. Other than the above, the configuration is substantially the same as that of FIG.

  Next, the operation of the configuration shown in FIG. 9 will be described using a specific example. In this description, a case where a 9-bit down counter circuit is used as the column count unit 103 will be described. When counting in the downcount mode, for example, if the count is 0, the count value is 9'b0_0000_0000 (corresponding to 0), and for example, if the count is 7, the count value is 9'b1_1111_1001 (corresponding to -7).

  The notation of the count value will be described. “9′b” indicates that the count value is a 9-bit binary number. “0_0000_0000” indicates the output of the column count unit 103 (counter circuits C_0 to C_8).

  Hereinafter, an example in which subtraction (CDS processing) between the first pixel signal and the subsequent second pixel signal will be described. 10 to 13 show the waveforms of the signals related to the operation of this example. FIGS. 10 and 11 show the waveforms of the signals during the first reading, and FIGS. 12 and 13 show the waveforms of the signals during the second reading. In addition, clk indicates a master clock input to the control unit 20, clken indicates an enable signal of the clock generation unit 18, and CLK indicates a clock signal output from the clock generation unit 18. D represents the output of the latch circuit D_0, Q [0] to Q [8] represent the outputs of the counter circuits C_0 to C_8, and OUT [8: 1] represents the digital data (upper 8 bits).

  The operation of this example includes a first readout period in which the first pixel signal is read and AD converted, a second readout period in which the second pixel signal is read and AD converted, and a transfer period in which digital data is transferred. It consists of the operation of each period. The first readout period includes a reset period for resetting the latch circuit D_0 and the counter circuits C_0 to C_8, a signal readout period for reading the first pixel signal, and the counter circuits C_0 to C_8 receiving the clock signal from the clock generator 18. It includes a counting period for counting and an initial value setting period for setting an initial value at the second reading. In the initial value setting period, the latch data count for counting the clock signal based on the value held in the latch circuit D_0 by the counter circuits C_0 to C_8 and the data inversion for inverting the count value of the counter circuits C_0 to C_8 are performed.

  The second readout period includes a reset period for resetting the latch circuit D_0, a signal readout period for reading the second pixel signal, and a counting period for the counter circuits C_0 to C_8 to count the clock signal from the clock generator 18. Including. After the counting period at the time of the second reading, latch data count is performed in which the counter circuits C_0 to C_8 count the clock signal based on the value held in the latch circuit D_0.

  Here, the count value when the first pixel signal is counted is 31, the count value when the second pixel signal is counted is 42, and the first pixel signal is subtracted from the second pixel signal (CDS processing). A case where the calculated value 11 is obtained will be described.

<< First reading >>
The control signal SEL is set to the L state, the control signals CNTEN_0 to CNTEN_8 are set to the L state, and the control signals CMODE_0 to CMODE_8 are set to the L state. In the reset period, the control signals CMODE_0 to CMODE_8 are in the H state, and the latch circuit D_0 and the counter circuits C_0 to C_8 are reset. Further, after the control signals CNTEN_1 to CNTEN_8 are in the H state, the control signals CMODE_0 to CMODE_8 are in the L state.

  Since the control signal SEL is set to the L state, the count clock of the counter circuit C_2 is set to the output of the latch circuit D_0. Therefore, until the end of the comparison process, the clock signal from the clock generation unit 18 is input to the counter circuit C_2, and the counter circuit C_2 performs counting using the clock signal from the clock generation unit 18 as a count clock. The value held by the column count unit 103 at the start of the comparison process in the counting period subsequent to the signal reading period is 9'b0_0000_0000.

  In the counting period, the comparison output CO is inverted at the first timing that satisfies a predetermined condition (in the above-described operation, the first timing related to the comparison between the ramp wave supplied from the ramp unit 19 and the reset level), The logic state of the clock signal from the clock generation unit 18 at that time is held (first clock signal). At the same time, the counter circuits C_2 to C_8 stop counting. At this time, the value held by the latch circuit D_0 is 1'b1 (H state), the value held by the column count unit 103 is 9'b1_1100_0100 (the value consisting of the upper 8 bits is equivalent to -30) is there.

  Subsequently, in the initial value setting period, the counter circuit C_2 performs counting based on the first clock signal held in the latch circuit D_0. After the control signals CMODE_0 to CMODE_8 change from the L state to the H state, the control signal SEL changes from the L state to the H state, and the control signals CMODE_0 to CMODE_8 change from the H state to the L state. Subsequently, the operation in which the control signal CNTEN_0 is changed from the L state to the H state and further changed to the L state is repeated twice. Since the control signal SEL is set to the H state, the count clock of the counter circuit C_2 is set to the output of the counter circuit C_1. As a result, a count signal corresponding to the logic state of the first clock signal held in the latch circuit D_0 is generated, and a count value obtained by counting the generated count signal is held in the column count unit 103. In this example, the value held by the latch circuit D_0 is 1'b1 (H state), and a 2-pulse count signal is generated. At this time, the value held by the column count unit 103 is 9'b1_1100_0010 (a value composed of the upper 8 bits is equivalent to -31). Thereafter, the value held by the column count unit 103 is inverted. At this time, the value held by the column count unit 103 is 9'b0_0011_1101 (the value composed of the upper 8 bits is equivalent to 30).

<< Second reading >>
The control signal SEL is set to the L state, the control signals CNTEN_0 to CNTEN_8 are set to the L state, and the control signals CMODE_0 to CMODE_8 are set to the L state. In the reset period, the control signals CMODE_0 to CMODE_8 are in the H state, and the latch circuit D_0 is reset. Further, after the control signals CNTEN_1 to CNTEN_8 are in the H state, the control signals CMODE_0 to CMODE_8 are in the L state. Note that the counter circuits C_0 to C_8 are not reset.

  Since the control signal SEL is set to the L state, the count clock of the counter circuit C_2 is set to the output of the latch circuit D_0. Therefore, until the end of the comparison process, the clock signal from the clock generation unit 18 is input to the counter circuit C_2, and the counter circuit C_2 performs counting using the clock signal from the clock generation unit 18 as a count clock. At the start of the comparison process in the counting period following the signal reading period, the value held by the column count unit 103 is 9'b0_0011_1101 (a value composed of the upper 8 bits is equivalent to 30).

  In the counting period, the comparison output CO is inverted at the second timing that satisfies a predetermined condition (in the above-described operation, the second timing related to the comparison between the ramp wave applied from the ramp unit 19 and the reset level), The logic state of the clock signal from the clock generation unit 18 at that time is held (second clock signal). At the same time, the counter circuits C_2 to C_8 stop counting. At this time, the value held by the latch circuit D_0 is 1'b0 (L state), the value held by the column count unit 103 is 9'b1_1110_1001 (the value consisting of the upper 8 bits is equivalent to -12) is there.

  Subsequently, the counter circuit C_2 performs counting based on the second clock signal held in the latch circuit D_0. After the control signals CMODE_0 to CMODE_8 change from the L state to the H state, the control signal SEL changes from the L state to the H state, and the control signals CMODE_0 to CMODE_8 change from the H state to the L state. Subsequently, the operation in which the control signal CNTEN_0 is changed from the L state to the H state and further changed to the L state is repeated twice. Since the control signal SEL is set to the H state, the count clock of the counter circuit C_2 is set to the output of the counter circuit C_1. As a result, a count signal corresponding to the second clock signal held in the latch circuit D_0 is generated, and a count value obtained by counting the generated count signal is held in the column count unit 103. In the case of this example, the value held by the latch circuit D_0 is 1'b0 (L state), and no count signal is generated. At this time, the value held by the column count unit 103 is 9'b1_1110_1001 (the value consisting of the upper 8 bits is equivalent to -12).

  Finally, the count value of the column count unit 103 is inverted (omitted in FIGS. 12 and 13). At this time, the value held by the column count unit 103 is 9′b0_0001 — 0110 (the value composed of the upper 8 bits corresponds to 11). In binary subtraction, it is necessary to add 1 after inverting the value, but since the value is also inverted at the first reading, the change in value caused by adding 1 after each inversion is canceled out. The Therefore, in this example, 1 is not added after inverting the value.

  In the transfer period, the digital data obtained by subtraction (CDS processing) is transferred to the output unit 17 by the horizontal selection unit 14 via the horizontal signal line. At this time, of the count values held by the counter circuits C_0 to C_8, digital data consisting of the count values held by the upper 8-bit counter circuits C_1 to C_8 may be transferred, or the counter circuits C_0 to C_8 May transfer digital data consisting of the count value held by the counter, and the bit data corresponding to the count value held by the upper 8-bit counter circuits C_1 to C_8 may be taken out by a subsequent circuit. The inversion of the digital data at the second reading may be performed after the digital data is transferred to the output unit 17. By the above operation, binary data corresponding to the difference between the first pixel signal and the second pixel signal is obtained.

  As described above, according to the present embodiment, in addition to counting the clock signal from the clock generation unit 18, the column count unit 103 generates based on the logic state of the clock signal latched in the latch circuit D_0. The counted signal is counted. As described above, by counting the logic state of the clock signal latched in the latch circuit D_0, the resolution of digital data obtained by AD conversion can be improved by 1 bit without increasing the frequency of the count clock. .

In this embodiment, the first to second bit counter circuits C_0 to C_1 hold values based on the logic state of the clock signal latched by the latch circuit D_0. However, other configurations are possible. is there. When the counter circuit C_0 to C_n of the 1st to (n + 1) th bits holds the value based on the logic state of the clock signal latched by the latch circuit D_0, the switching unit MUX counts to the counter circuit C_n + 1. A signal input as a clock is switched between the output of the latch circuit D_0 and the output of the counter circuit C_n. When the value held by the latch circuit D_0 is 1′b1 (H state), a count signal composed of 2 ⁿ⁻¹ pulses is generated, and the value held by the latch circuit D_0 is 1′b0. In the case of (L state), no counting signal is generated.

(Third embodiment)
Next, a third embodiment of the present invention will be described. The configuration of the (C) MOS imaging device according to the present embodiment is substantially the same as that of the first embodiment, but the configuration of the column count unit 103 of the column AD conversion unit 16 is different. The column count unit 103 includes an up / down counter circuit having an up count mode and a down count mode as a count mode. The rest is substantially the same as the first embodiment.

  Next, the operation of this example will be described. In the following, the details of the first and second read operations and the subsequent subtraction (CDS process) will be described with a focus on operations different from those of the first embodiment. Here, it is assumed that the count mode of the column count unit 103 is the down-count mode in the first reading and the up-count mode in the second reading, and the column counting unit 103 performs counting at the falling edge timing of the count clock. Shall.

<First reading>
After the first reading from the unit pixel 3 of the arbitrary pixel row to the vertical signal line 13 is stabilized, the ramp unit 19 outputs a ramp wave. The comparison unit 109 compares this ramp wave with the reset level. During this time, the column count unit 103 performs counting in the down-count mode using the clock signal from the clock generation unit 18 output via the latch unit 108 as a count clock.

  The comparison unit 109 compares the ramp wave supplied from the ramp unit 19 with the reset level, and inverts the comparison output when both voltages substantially match (first timing). At the first timing, the latch unit 108 holds the clock signal output from the clock generation unit 18 as the first clock signal. When the predetermined period has elapsed, the ramp unit 19 stops generating the ramp wave.

  Subsequently, the column count unit 103 generates a count signal composed of a predetermined number of pulse signals according to the logic state of the first clock signal held in the latch unit 108, and uses the generated count signal as a count clock. Count. Thereby, the initial value of the column count unit 103 in the second reading is set.

<Second reading>
Subsequently, at the time of the second reading, a signal level corresponding to the amount of incident light for each unit pixel 3 is read, and the same operation as the first reading is performed. After the second reading from the unit pixel 3 of the arbitrary pixel row to the vertical signal line 13 is stabilized, the ramp unit 19 outputs a ramp wave. The comparison unit 109 compares the ramp wave with the signal level. During this time, the column count unit 103 performs counting in the up-count mode using the clock signal from the clock generation unit 18 output via the latch unit 108 as a count clock.

  The comparison unit 109 compares the ramp wave supplied from the ramp unit 19 with the signal level, and inverts the comparison output when the two voltages substantially match (second timing). At the second timing, the latch unit 108 holds the clock signal output from the clock generation unit 18 as the second clock signal. When the predetermined period has elapsed, the ramp unit 19 stops generating the ramp wave.

  Subsequently, the column count unit 103 generates a count signal composed of a predetermined number of pulse signals according to the logic state of the second clock signal held in the latch unit 108, and uses the generated count signal as a count clock. Count. Thereby, subtraction (CDS processing) between the reset level and the signal level is performed.

  As described above, digital data corresponding to the difference between the reset level and the signal level is obtained. Finally, the value of each bit constituting the digital data held by the column count unit 103 is inverted, and the inverted digital data is transferred by the horizontal selection unit 14 to the output unit 17 via the horizontal signal line. .

  Next, the operation of this example will be described using a specific example. In this description, a case where an 8-bit up / down counter circuit is used as the column count unit 103 will be described. When counting in the down count mode, for example, if the count is 0, the count value is 8'b0000_0000 (corresponding to 0), and for example, if the count is 7, the count value is 8'b1111_1001 (corresponding to -7). When counting in the up-count mode, for example, if the count is 0, the count value is 8'b0000_0000 (corresponding to 0), and for example, if the count is 7, the count value is 8'b0000_0111 (corresponding to 7).

  Hereinafter, an example in which subtraction (CDS processing) between the first pixel signal and the subsequent second pixel signal will be described. In this example, binary subtraction using 2's complement is performed. When the digital value obtained by AD converting the first pixel signal is A and the digital value obtained by AD converting the second pixel signal is B, the subtraction result to be obtained is B−A.

  In this example, since the column count unit 103 performs counting in the down-count mode at the first reading, the count value after the column counting unit 103 performs counting based on the first pixel signal at the first reading is digital. Corresponds to the value -A. Subsequently, since the column count unit 103 performs counting in the up-count mode at the second reading, the count value after the column counting unit 103 performs the counting based on the second pixel signal at the second reading is a digital value. Corresponds to BA.

  14 to 17 show the waveform of each signal related to the operation of this example. 14 and 15 show the waveforms of the signals at the time of the first reading, and FIGS. 16 and 17 show the waveforms of the signals at the time of the second reading. In addition, clk indicates a master clock input to the control unit 20, clken indicates an enable signal of the clock generation unit 18, and CLK indicates a clock signal output from the clock generation unit 18. D represents the output of the latch circuit D_0, Q [0] to Q [7] represent the outputs of the counter circuits C_0 to C_7, and OUT [7: 0] represents the digital data.

  The operation of this example includes a first readout period in which the first pixel signal is read and AD converted, a second readout period in which the second pixel signal is read and AD converted, and a transfer period in which digital data is transferred. It consists of the operation of each period. The first readout period includes a reset period for resetting the latch circuit D_0 and the counter circuits C_0 to C_7, a signal readout period for reading the first pixel signal, and the counter circuits C_0 to C_7 receiving the clock signal from the clock generator 18. It includes a counting period for counting and an initial value setting period for setting an initial value at the second reading. In the initial value setting period, latch data count is performed in which the counter circuits C_0 to C_7 count the clock signal based on the value held in the latch circuit D_0.

  The second readout period includes a reset period for resetting the latch circuit D_0, a signal readout period for reading the second pixel signal, and a counting period for the counter circuits C_0 to C_7 to count the clock signal from the clock generator 18. Including. After the counting period at the time of the second reading, latch data count is performed in which the counter circuits C_0 to C_7 count the clock signal based on the value held in the latch circuit D_0.

  Here, the count value when counting the first pixel signal is 32, the count value when counting the second pixel signal is 43, and the first pixel signal is subtracted from the second pixel signal (CDS processing) A case where the calculated value 11 is obtained will be described.

<< First reading >>
The control signal SEL is set to the L state, the control signals CNTEN_0 to CNTEN_7 are set to the L state, and the control signals CMODE_0 to CMODE_7 are set to the L state. In the reset period, the control signals CMODE_0 to CMODE_7 are in the H state, and the latch circuit D_0 and the counter circuits C_0 to C_7 are reset. Further, after the control signals CNTEN_1 to CNTEN_7 are in the H state, the control signals CMODE_0 to CMODE_7 are in the L state.

  Since the control signal SEL is set to the L state, the count clock of the counter circuit C_1 is set to the output of the latch circuit D_0. Therefore, until the end of the comparison process, the clock signal from the clock generation unit 18 is input to the counter circuit C_1, and the counter circuit C_1 performs counting using the clock signal from the clock generation unit 18 as a count clock. The value held by the column count unit 103 at the start of the comparison process in the counting period subsequent to the signal reading period is 8'b0000_0000.

  In the counting period, the comparison output CO is inverted at the first timing that satisfies a predetermined condition (in the above-described operation, the first timing related to the comparison between the ramp wave supplied from the ramp unit 19 and the reset level), The logic state of the clock signal from the clock generation unit 18 at that time is held (first clock signal). At the same time, the counter circuits C_1 to C_7 stop counting. At this time, the value held by the latch circuit D_0 is 1'b0 (L state), and the value held by the column count unit 103 is 8'b1110_0000 (corresponding to -32).

  Subsequently, in the initial value setting period, the counter circuit C_1 performs counting based on the first clock signal held in the latch circuit D_0. After the control signals CMODE_0 to CMODE_7 change from the L state to the H state, the control signal SEL changes from the L state to the H state, and the control signals CMODE_0 to CMODE_7 change from the H state to the L state. Subsequently, the control signal CNTEN_0 changes from the L state to the H state, and further changes to the L state. Since the control signal SEL is set to the H state, the count clock of the counter circuit C_1 is set to the output of the counter circuit C_0. As a result, a count signal corresponding to the logic state of the first clock signal held in the latch circuit D_0 is generated, and a count value obtained by counting the generated count signal is held in the column count unit 103. In this example, the value held by the latch circuit D_0 is 1'b0 (L state), and there is no generated count signal. At this time, the value held by the column count unit 103 is 8′b1110_0000 (corresponding to −32).

<< Second reading >>
The control signal SEL is set to the L state, the control signals CNTEN_0 to CNTEN_7 are set to the L state, and the control signals CMODE_0 to CMODE_7 are set to the L state. In the reset period, the control signals CMODE_0 to CMODE_7 are in the H state, and the latch circuit D_0 is reset. Further, after the control signals CNTEN_1 to CNTEN_7 are in the H state, the control signals CMODE_0 to CMODE_7 are in the L state. Note that the counter circuits C_0 to C_7 are not reset.

  Since the control signal SEL is set to the L state, the count clock of the counter circuit C_1 is set to the output of the latch circuit D_0. Therefore, until the end of the comparison process, the clock signal from the clock generation unit 18 is input to the counter circuit C_1, and the counter circuit C_1 performs counting using the clock signal from the clock generation unit 18 as a count clock. The value held by the column count unit 103 at the start of the comparison process in the counting period subsequent to the signal reading period is 8'b1110_0000 (corresponding to -32).

  In the counting period, the comparison output CO is inverted at the second timing that satisfies a predetermined condition (in the above-described operation, the second timing related to the comparison between the ramp wave applied from the ramp unit 19 and the reset level), The logic state of the clock signal from the clock generation unit 18 at that time is held (second clock signal). At the same time, the counter circuits C_1 to C_7 stop counting. At this time, the value held by the latch circuit D_0 is 1'b1 (H state), and the value held by the column count unit 103 is 8'b0000_1010 (corresponding to 10).

  Subsequently, the counter circuit C_1 performs counting based on the second clock signal held in the latch circuit D_0. After the control signals CMODE_0 to CMODE_7 change from the L state to the H state, the control signal SEL changes from the L state to the H state, and the control signals CMODE_0 to CMODE_7 change from the H state to the L state. Subsequently, the control signal CNTEN_0 changes from the L state to the H state, and further changes to the L state. Since the control signal SEL is set to the H state, the count clock of the counter circuit C_1 is set to the output of the counter circuit C_0. As a result, a count signal corresponding to the second clock signal held in the latch circuit D_0 is generated, and a count value obtained by counting the generated count signal is held in the column count unit 103. In the case of this example, the value held by the latch circuit D_0 is 1'b1 (H state), and a one-pulse count signal is generated. At this time, the value held by the column count unit 103 is 8′b0000 — 1011 (corresponding to 11).

  In the transfer period, the digital data obtained by subtraction (CDS processing) is transferred to the output unit 17 by the horizontal selection unit 14 via the horizontal signal line. By the above operation, binary data corresponding to the difference between the first pixel signal and the second pixel signal is obtained.

  As described above, according to the present embodiment, in addition to counting the clock signal from the clock generation unit 18, the column count unit 103 generates based on the logic state of the clock signal latched in the latch circuit D_0. The counted signal is counted. As described above, by counting the logic state of the clock signal latched in the latch circuit D_0, the resolution of digital data obtained by AD conversion can be improved by 1 bit without increasing the frequency of the count clock. .

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  2, 1002 ... Imaging unit, 5, 1005 ... Read current source unit, 12, 1012 ... Vertical selection unit, 14, 1014 ... Horizontal selection unit, 15, 1015 ... Column processing unit, 16, 1016 ... column AD conversion unit, 17, 1017 ... output unit, 18, 1018 ... clock generation unit, 19, 1019 ... ramp unit, 20, 1020 ... control unit, 103, 1103: Column count unit, 108, 1108 ... Latch unit, 109, 1109 ... Comparison unit

Claims (3)

A reference signal generator that generates a reference signal that increases or decreases over time;
A comparison unit that compares the analog signal to be subjected to AD conversion and the reference signal, and ends the comparison process at a timing when the reference signal satisfies a predetermined condition with respect to the analog signal;
A clock generator for outputting a clock signal of a predetermined frequency;
A latch unit that passes the clock signal output from the clock generation unit during the comparison process and latches the clock signal at a timing related to the end of the comparison process;
a counter circuit of k (k is a natural number equal to or greater than 3) bits, and the first count signal based on the clock signal output from the latch unit is j (j is a natural number of j <k) of the counter circuit The second count signal, which is a pulse signal generated based on the logic state of the clock signal input to the bit and latched in the latch unit, is i (i is a natural number of i <j) of the counter circuit. A count unit that inputs to the bit, and counts the first count signal and the second count signal;
With
The latch unit latches the clock signal at a timing related to the end of the comparison process according to a first analog signal, and then latches the clock signal at a timing related to the end of the comparison process according to a second analog signal. Latch and
The counting unit performs a first counting process according to the first analog signal, inverts each bit constituting a count value obtained by the first counting process, and then converts the bit into the second analog signal. An AD conversion circuit that outputs digital data corresponding to a difference between the first analog signal and the second analog signal by performing a second counting process in response. A reference signal generator that generates a reference signal that increases or decreases over time;
A comparison unit that compares the analog signal to be subjected to AD conversion and the reference signal, and ends the comparison process at a timing when the reference signal satisfies a predetermined condition with respect to the analog signal;
A clock generator for outputting a clock signal of a predetermined frequency;
A latch unit that passes the clock signal output from the clock generation unit during the comparison process and latches the clock signal at a timing related to the end of the comparison process;
a counter circuit of k (k is a natural number equal to or greater than 3) bits, and the first count signal based on the clock signal output from the latch unit is j (j is a natural number of j <k) of the counter circuit The second count signal, which is a pulse signal generated based on the logic state of the clock signal input to the bit and latched in the latch unit, is i (i is a natural number of i <j) of the counter circuit. A count unit that inputs to the bit, and counts the first count signal and the second count signal;
With
The latch unit latches the clock signal at a timing related to the end of the comparison process according to a first analog signal, and then latches the clock signal at a timing related to the end of the comparison process according to a second analog signal. Latch and
The counting unit performs a first counting process according to the first analog signal in one of a down-count mode and an up-count mode, and in either one of the down-count mode and the up-count mode. An AD conversion circuit that outputs digital data according to a difference between the first analog signal and the second analog signal by performing a second counting process according to the second analog signal. A plurality of pixels having photoelectric conversion elements are arranged, the plurality of pixels output a signal corresponding to a reset level as a first pixel signal, and a signal corresponding to the magnitude of incident electromagnetic waves is a second pixel An imaging unit that outputs a signal;
AD conversion circuit according to claim 1 or claim 2,
With
An imaging apparatus comprising: an analog signal corresponding to the first pixel signal as the first analog signal; and an analog signal corresponding to the second pixel signal as the second analog signal.

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