JP6662137B2 - Photoelectric conversion element, image reading device, and image forming device - Google Patents

Description

  The present invention relates to a photoelectric conversion element, an image reading device, and an image forming device.

  In a batch exposure type photoelectric conversion element (imaging device), the reset level of each pixel is collectively held in a capacitor, and the signal level of each pixel is collectively held in a capacitor. It is known to read sequentially and perform correlated double sampling (CDS).

  Also, in Patent Document 1, each pixel amplifies and outputs a signal input to the gate from the photoelectric conversion unit, a reset transistor that resets the gate voltage of the first amplifying transistor, A plurality of capacitors for holding signals output from the first amplifying transistor to the first signal line; and a plurality of capacitors provided between the first signal line and the plurality of capacitors corresponding to the plurality of capacitors, respectively. A plurality of capacitance switches each of which performs input / output control between one signal line and a plurality of capacitances, and a second signal by amplifying a signal input to the gate from the first signal line; An amplification type solid-state imaging device including a second amplification transistor that outputs a signal to a line, and an initialization transistor that is connected to the first signal line and outputs a predetermined first voltage to the first signal line is disclosed. Have been.

  However, in the conventional pixel data read control, the influence of switching noise generated when various switch transistors are turned on / off differs between the case where the reset voltage is read and the case where the signal voltage is read. There has been a problem that noise cannot be sufficiently removed even by performing double sampling.

  The present invention has been made in view of the above, and an object of the present invention is to provide a photoelectric conversion element, an image reading device, and an image forming device that can accurately remove noise by correlated double sampling.

In order to solve the above-described problem and achieve the object, the present invention provides a plurality of pixel units that perform photoelectric conversion according to the amount of received light, and a plurality of first units that hold a reset voltage indicating a reset level of the pixel unit. A capacitor and a plurality of second capacitors that hold a signal voltage indicating a signal level output by the pixel unit after photoelectric conversion, and a reset voltage that is turned on from the pixel unit to the first capacitor via a signal line; And a plurality of first transistors that transfer a signal voltage from the pixel portion to the second capacitor via the signal line, and a plurality of second transistors that connect the first capacitor to the signal line when turned on. A transistor; a plurality of third transistors which connect the second capacitor to the signal line when turned on; a reset voltage held by the first capacitor; and a signal held by the second capacitor. A plurality of fourth transistors for sequentially transferring a voltage to a subsequent stage via the signal line by turning on a voltage; and a plurality of fifth transistors for initializing a potential transferred via the signal line when turned on. A plurality of processing units for performing a process of calculating a difference between a reset voltage and a signal voltage transferred by the fourth transistor, wherein the processing unit determines a timing at which the fifth transistor is turned off and a timing at which the second transistor is turned off. for the first time difference is a time difference between the timing at which the transistor is turned on, the second time difference wherein the fifth transistor and the timing of the off-third transistor is a time difference between the timing of the on is the same Then, a difference between the reset voltage held by the first capacitor and the signal voltage held by the second capacitor is calculated.

  According to the present invention, there is an effect that noise can be accurately removed by correlated double sampling.

FIG. 1 is a block diagram illustrating a configuration example of a photoelectric conversion element according to an embodiment. FIG. 2 is a diagram exemplifying a plurality of pixel units arranged in a line in the conversion processing unit and the periphery thereof. FIG. 3 is a diagram illustrating a configuration example of a pixel unit. FIG. 4 is a timing chart showing the operation of the photoelectric conversion element as a comparative example. FIG. 5 is a timing chart showing the behavior of a signal line as a comparative example. FIG. 6 is a timing chart illustrating the behavior of the signal line in the first example of the operation of the photoelectric conversion element according to the embodiment. FIG. 7 is a timing chart illustrating the behavior of a signal line when each pixel unit of the photoelectric conversion element according to the embodiment operates for each color received. FIG. 8 is a timing chart illustrating the behavior of the signal line when the fifth transistor is delayed as a comparative example. FIG. 9 is a timing chart illustrating the behavior of the signal line in the second example of the operation of the photoelectric conversion element according to the embodiment. FIG. 10 is a timing chart illustrating an operation example of another configuration example of the photoelectric conversion element. FIG. 11 is a timing chart illustrating an operation example of the photoelectric conversion element when the processing unit has a high load as a comparative example. FIG. 12 is a diagram illustrating a modified example of a plurality of pixel units arranged in a line in the conversion processing unit and the periphery thereof. FIG. 13 is a timing chart illustrating the operation of the electric conversion element having the modification shown in FIG. FIG. 14 is a diagram illustrating an outline of an image forming apparatus including an image reading device having a photoelectric conversion element.

  Hereinafter, a photoelectric conversion element according to an embodiment will be described with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating a configuration example of a photoelectric conversion element 10 according to the embodiment. The photoelectric conversion element 10 is, for example, a CMOS color linear sensor of a collective exposure method, and includes a conversion processing unit 12, a timing control unit (Timing Generator: TG) 14, a parallel-serial conversion unit (PS) 16, and an LVDS 18.

  The conversion processing unit 12 includes a plurality of pixel units 120 (described later with reference to FIGS. 2 and 3) arranged in one direction (for example, a main scanning direction of a document) for each color of the received RGB light. Photoelectric conversion is performed for each color, and image data for each color is output in parallel as digital data in the main scanning direction.

  The timing control unit 14 is a control unit that controls operation timings of the conversion processing unit 12 and the parallel-serial conversion unit 16. The parallel-serial conversion unit 16 converts the digital data output in parallel by the conversion processing unit 12 into serial data, and outputs the serial data to the LVDS 18. The LVDS 18 converts the serial data input from the parallel-to-serial conversion unit 16 into a low-voltage differential serial signal, and outputs it to a subsequent stage.

  FIG. 2 is a diagram illustrating a plurality of pixel units 120 arranged in a line in the conversion processing unit 12 and the periphery thereof. The output of each pixel unit 120 is connected to a signal line (common read line) Vsig1 via a first transistor (write transistor SL) 121. The first capacitor (CwR) 122 holds a reset voltage indicating a reset level of the pixel unit 120. The second capacitor (CwS) 123 holds a signal voltage indicating a signal level output by the pixel unit 120 after photoelectric conversion. When the first transistor 121 is turned on, the reset voltage is transferred from the pixel portion 120 to the first capacitor 122 via the signal line Vsig1 and the signal voltage is transferred from the pixel portion 120 to the second capacitor 123 via the signal line Vsig1. Forward.

  When turned on, the second transistor (SwR) 124 connects the first capacitor 122 to the signal line Vsig1. The third transistor (SwS) 125 connects the second capacitor 123 to the signal line Vsig1 when turned on.

  The fourth transistor (read transistor SW) 126 sequentially turns on the reset voltage held by the first capacitor 122 and the signal voltage held by the second capacitor 123 via the signal line Vsig1. Transfer to the subsequent stage. The fifth transistor (IT) 127 initializes a potential (signal) transferred via the signal line Vsig1 to a voltage V0 when turned on.

  The amplification transistor (source follower SF2) 128 amplifies the potential (signal) transferred via the signal line Vsig1, and outputs the amplified potential (signal) to the processing unit 129. The processing unit 129 performs a predetermined process including a process of calculating a difference between the reset voltage transferred by the fourth transistor 126 and the signal voltage (double correlation sampling: CDS).

  More specifically, the processing unit 129 sets the timing at which the fifth transistor 127 turns off with respect to the first time difference that is the time difference between the timing at which the fifth transistor 127 turns off and the timing at which the second transistor 124 turns on. A difference between the reset voltage held by the first capacitor 122 and the signal voltage held by the second capacitor 123 is calculated after the second time difference, which is the time difference between the second transistor 123 and the timing at which the third transistor 125 is turned on, is made substantially the same. Thus, double correlation sampling is performed.

  In the conversion processing unit 12, a plurality of pixel units 120 are arranged in one row for each color of the received RGB light, for example. Then, the conversion processing unit 12 supplies the first transistor 121, the first capacitor 122, the second capacitor 123, the second transistor 124, the third transistor 125, the fourth transistor 126, the fifth transistor 127, and the amplification for each of the RGB colors. A transistor 128 is provided, and for example, six pixel units 120 that receive, for example, RGB light are connected to a common processing unit 129.

  FIG. 3 is a diagram illustrating a configuration example of the pixel unit 120. The light receiving element (photodiode: PD) generates and accumulates electric charge according to the amount of light received within the accumulation time. The transfer transistor TX transfers the charge generated by the PD to the floating diffusion region FD for charge-voltage conversion (charge detection). The reset transistor RT resets the FD to the power supply voltage Vdd, which is the drain voltage of the RT, before the charge is transferred from the PD. The transfer transistor TX and the reset transistor RT operate when a control signal is input to the gate from the timing control unit 14.

  The amplification transistor SF1 has a drain connected to the power supply voltage Vdd, and a source connected to the first capacitor 122 or the second capacitor 123 via the first transistor 121 (FIG. 2) and the second transistor 124 or the third transistor 125. Have been.

  Here, the operation of the photoelectric conversion element 10 as a comparative example will be described first. FIG. 4 is a timing chart showing the operation of the photoelectric conversion element 10 as a comparative example. At time t1, before the signal charge is transferred from each PD at time t1, each timing resets the power supply voltage Vdd, which is the drain voltage of each RT, by each RT. Each FD may be configured to be reset to the source voltage of each RT.

  Thereafter, the timing control unit 14 turns on each second transistor 124 at time t2. As a result, the first capacitors 122 for all the pixel units 120 simultaneously hold the reset voltage of the FD at the time of reset.

  At time t3, the timing control unit 14 simultaneously turns off the second transistors 124 and turns on the transfer transistors TX. Thereby, the signal charges from each PD are respectively transferred to the FDs after the reset charge transfer.

  At time t4, the timing control unit 14 turns off each TX and simultaneously turns on each third transistor 125 to cause the second capacitor 123 to hold the signal voltage. Next, the timing control unit 14 turns off the third transistors 125 and the first transistors 121 all at once, and ends the batch writing to the first capacitors 122 and the second capacitors 123.

  At time t5, the timing control unit 14 turns on the fifth transistor 127 and initializes the signal line Vsig1 before reading the voltages of the first capacitors 122 and the second capacitors 123.

  At time t6, the timing control unit 14 turns on the fourth transistor 126 and simultaneously turns on the second transistor 124. As a result, the reset voltage held in the first capacitor 122 is transferred to Vsig1.

  At time t7, the timing control unit 14 turns on the fifth transistor 127, and initializes the voltage of the first capacitor 122 to the voltage V0. After the capacitance initialization, the timing control unit 14 turns off the second transistor 124 and the fifth transistor 127 at time t8, and similarly turns on the third transistor 125, and the second capacitor 123 holds the same. The current signal voltage is transferred to the signal line Vsig1.

  At time t9, the timing control unit 14 turns on the fifth transistor 127, and initializes the voltage of the second capacitor 123 to the voltage V0. After the capacitance initialization, the timing control unit 14 turns off the third transistor 125 and the fifth transistor 127 at time t10, and ends the reading process.

  Note that the photoelectric conversion element 10 sequentially performs the read processing (t6 to t9) in synchronization with each of the RGB colors.

  Note that the switch transistors such as the second transistor 124, the third transistor 125, the fourth transistor 126, and the fifth transistor 127 are semiconductors such as nMOSs, and generate noise due to various factors at the time of on / off.

  For example, charge injection is a phenomenon in which charge (electrons or holes) forming a channel when a transistor (switching element) is on moves to the source or drain of the transistor when the transistor is turned off. That is, an offset variation occurs in the voltage of the signal line after turning off. Further, even when the transistor is turned on, the charge on the signal line is charged to form a channel, so that the voltage of the signal line has an offset variation with a polarity opposite to that when the transistor is turned off.

  In addition, the clock feedthrough affects the potential due to an electrostatic effect caused by a parasitic capacitance between the gate and the drain or between the gate and the source as the gate potential changes from on (off) to off (on). The effect is Therefore, these switching noises occur in the direction of voltage rise when the transistor is turned on, and in the direction of voltage decrease when the transistor is turned off (offset fluctuation).

  Considering these noises, the behavior of the signal line Vsig1 at each timing will be described. FIG. 5 is a timing chart showing the behavior of the signal line Vsig1 as a comparative example. First, at time t5, the switching noise is generated in the direction in which the voltage is increased by turning on the fifth transistor 127. However, when the fifth transistor 127 is turned on, the potential of the signal line Vsig1 converges to V0 because it is connected to V0.

  At t6, since the second transistor 124 and the fourth transistor 126 are turned on at the same time as the fifth transistor 127 is turned off, the offset fluctuation in the direction of increasing voltage is larger, and the initial voltage shift by ΔVr at the start of reset voltage reading. Occurs.

  After reading the reset voltage, at t7, as in t5, the fifth transistor 127 is turned on, so that switching noise occurs in the direction in which the voltage increases. However, since the fifth transistor 127 is on, the potential of the signal line Vsig1 converges to V0.

  At t7a, the second transistor 124 and the fifth transistor 127 are turned off at the same time, so that two switching noises occur, and an offset fluctuation occurs in a direction in which the voltage decreases. At t7a, since the fifth transistor 127 is off, it does not converge to V0 and the offset fluctuation is maintained.

  At t8, when the third transistor 125 is turned on, the signal line Vsig1 causes an offset fluctuation in a direction in which the voltage increases, but cannot return to V0 due to one switching noise, and ΔVs is different from ΔVr as ΔVs. An initial voltage shift occurs. Therefore, in the example shown in FIG. 5, since the initial voltage at the start of the transfer is different in reading the reset voltage and the signal voltage, | Vr−Vs | cannot be obtained even if the processing unit 129 performs the CDS in the subsequent stage. , | (Vr + ΔVr) − (Vs−ΔVs) |, ΔVr + ΔVs remains as an error.

  When reading the reset voltage, the photoelectric conversion element 10 turns off the second transistor 124 and turns off the fifth transistor 127, thereby canceling the offset fluctuation. In the example shown in FIG. 5, when the signal voltage is read from the photoelectric conversion element 10, the offset fluctuation occurs as shown at t7a, and the initial voltage shift occurs.

  In addition, in the example shown in FIG. 5, the photoelectric conversion element 10 sequentially executes the processing from t6 to t9a for each color. Therefore, for example, when reading is performed in the order of R → G → B, R and G Thus, the initial voltage before reset voltage reading is different (t5 and t9a in FIG. 5). In this case, even if the RGB uniform light is photoelectrically converted, the RGB output is biased and the color reproducibility is deteriorated.

  Next, an example of the operation of the photoelectric conversion element 10 will be described. FIG. 6 is a timing chart illustrating the behavior of the signal line Vsig1 in the first example of the operation of the photoelectric conversion element 10 according to the embodiment. The photoelectric conversion element 10 sets the off timing of the fifth transistor 127 to the second transistor 124 (third transistor 125) as shown in FIG. 6 in order to make the offset fluctuation due to the switching noise uniform between the time of reading the reset voltage and the time of reading the signal voltage. (T7a, t9a).

  The time to be shifted by the timing control unit 14 may be any time required to secure the time required from the occurrence of the switching noise to the convergence to V0. Further, the timing control unit 14 sets the on-timing of the fourth transistor 126 to be the same as the on-timing of the fifth transistor 127 (t5). First, at t5, when the fifth transistor 127 and the fourth transistor 126 are turned on, two switching noises are generated in the direction in which the voltage increases. However, since the fifth transistor 127 is on, the potential of the signal line Vsig1 converges to V0.

  At t6, since only the second transistor 124 is turned on at the same time as the fifth transistor 127 is turned off, the charge released from the turned off fifth transistor 127 is charged to the turned on second transistor 124 as a channel charge. The fluctuation is canceled, and there is no shift in the initial voltage at the start of the reset voltage reading, and the operation is started as V0. After reading the reset voltage, at t7, the switching noise is generated in the direction in which the voltage increases by turning on the fifth transistor 127 as in FIG. However, since the fifth transistor 127 is on, the potential of the signal line Vsig1 converges to V0.

  At t7a, the second transistor 124 is turned off, but since the fifth transistor 127 is on, the potential of the signal line Vsig1 converges to V0. At t8, only the third transistor 125 is turned on at the same time as the fifth transistor 127 is turned off, so that the charge released from the turned off fifth transistor 127 is charged as channel charge to the turned on third transistor 125. , The offset fluctuation is canceled, and even when the signal voltage reading is started, there is no deviation of the initial voltage, and the signal voltage is started as V0.

  Therefore, in the example shown in FIG. 6, in the reading of the reset voltage and the signal voltage, both of the initial voltages at the start of the transfer are the initialization voltage V0. Therefore, if the processing unit 129 performs the CDS in the subsequent stage, | Vr −Vs | can be obtained. As described above, in the first embodiment of the operation of the photoelectric conversion element 10, the influence of the switching noise can be removed, and a good signal output can be obtained.

  FIG. 7 is a timing chart illustrating the behavior of the signal line Vsig1 when each pixel unit 120 of the photoelectric conversion element 10 according to the embodiment operates for each color received. As described above, the photoelectric conversion element 10 reads out a signal for each color of light received by the plurality of pixel units 120. Here, the switch transistors of the readout circuit for each color are distinguished as SW_ *, SwR_ *, and SwS_ * (*: R, G, B), respectively. Further, the storage capacities are distinguished as CwR_ * and CwS_ * (*: R, G, B).

  When reading is performed in the order of R → G → B, the photoelectric conversion element 10 reads a reset voltage and a signal voltage from CwR_R and CwS_R of R, respectively, and after initialization (t9), the fifth transistor 127 remains on. , SW_R are turned off, and the reading of R ends. Next, at time t10, the photoelectric conversion element 10 turns on SW_G and starts reading G. Therefore, at t10 to t14 (t15 to t19), the operation is the same as that at t6 to t9, no error occurs between colors, and a good signal output excluding the influence of switching noise can be obtained.

  FIG. 8 is a timing chart showing the behavior of the signal line Vsig1 when the fifth transistor 127 as a comparative example is delayed. Due to the circuit configuration of the photoelectric conversion element 10, a circuit delay occurs from the timing control unit 14 to the conversion processing unit 12, and the on / off timing of each transistor may be shifted due to the variation in the circuit delay. FIG. 8 illustrates a case where the off-timing of the fifth transistor 127 varies and is delayed by different times from the on-timings of the second transistor 124 and the third transistor 125, respectively.

  When the second transistor 124 (third transistor 125) is turned on, the signal line Vsig1 is connected to the initialization potential V0, and thus tends to converge on the initialization potential V0 even if an offset variation occurs once due to switching noise. . After that, since the fifth transistor 127 is turned off, switching noise is generated in the direction of decreasing the voltage. In this case, the offset fluctuation when the second transistor 124 (the third transistor 125) is turned on converges to V0 and is smaller in absolute value than the offset fluctuation when the fifth transistor 127 is turned off.

  Therefore, in the reading of the reset voltage and the signal voltage, the offset fluctuation due to the switching noise of each switch transistor is not canceled, and the off-timing of the fifth transistor 127 between the reset voltage reading and the signal voltage reading (t5a, t7b). ), The second transistor 124 (the third transistor 125) is on, and the voltage that fluctuates while trying to converge during the period in which the fifth transistor 127 is on also causes a difference. As a result, a difference occurs between ΔVr and ΔVs, the CDS output becomes | (Vr−ΔVr) − (Vs−ΔVs) |, and ΔVs−ΔVr remains as an offset error.

  FIG. 9 is a timing chart illustrating the behavior of the signal line Vsig1 in the second example of the operation of the photoelectric conversion element 10 according to the embodiment. As shown in FIG. 9, in the second embodiment of the operation, the photoelectric conversion element 10 performs the operation even after the off-timing of the fifth transistor 127 is different from the on-timing of the second transistor 124 (the third transistor 125). To prevent this, the interval between t5a and t7b is provided so that the second transistor 124 (the third transistor 125) is turned on after the fifth transistor 127 is turned off.

  When the timing at which the fifth transistor 127 is turned off is earlier than the timing at which the second transistor 124 (the third transistor 125) is turned on, after the offset variation due to the turning off of the fifth transistor 127 occurs, the second transistor 127 is turned off. An offset fluctuation occurs due to the turning on of 124 (third transistor 125). Therefore, even if a circuit delay as shown in FIG. 8 occurs, the initial voltage becomes V0, and the initial states of the reset voltage and the signal voltage are aligned.

  FIG. 10 is a timing chart illustrating an operation example of another configuration example of the photoelectric conversion element 10. Generally, switching noise Vnoise (error voltage) such as clock feedthrough depends on the transistor size and the gate voltage as in the following equation 1.

  Here, ΔVg indicates a change in the gate voltage, indicates a parasitic capacitance between the gate and the source (or between the gate and the drain) of the Cov transistor, W indicates a gate width of the transistor, and Csig1 indicates a wiring capacitance of the signal line Vsig1. Is shown.

  Therefore, the photoelectric conversion element 10 sets the transistor size (gate width) and the gate voltage of the third transistor 125 so that ΔVs finally becomes the same value as ΔVr at t8, so that the subsequent processing unit 129 is set. However, the error voltage can be accurately removed by the CDS. That is, the transistor size of the third transistor 125 (or the second transistor 124) is set to generate an error voltage large enough to offset the error voltage generated by the operation of the second transistor 124 (or the third transistor 125). Is set.

  Specifically, the gate width Ws of the third transistor 125 that causes the switching noise to be tripled is expressed by the following equation (2).

  In T9a, on the contrary, the offset fluctuation due to the switching noise at the time of OFF becomes enormous, but since it converges to V0 by the next ON of the fifth transistor 127, there is no problem.

  Similarly, even if the transistor size is the same, the switching noise is tripled by setting the gate voltage of only the third transistor 125 to triple. Also in this case, ΔVs = ΔVr, and the processing unit 129 at the subsequent stage can accurately remove the error voltage by the CDS. For example, the third transistor 125 (or the second transistor 124) has a gate voltage that generates an error voltage that is large enough to offset the error voltage generated by the operation of the second transistor 124 (or the third transistor 125). Is set.

  Specifically, the gate voltage ΔVgs of the third transistor 125, which becomes the triple switching noise, is expressed by the following equation (3).

  At T9a, on the contrary, the offset fluctuation due to the switching noise at the time of OFF increases, but it does not pose a problem because it converges to V0 by the next ON of the fifth transistor 127. Further, in the pixel portion 120 having different colors of light to be received, the offset between colors is set by setting the transistor size and the gate voltage of the third transistor 125 (or the second transistor 124) according to the order of reading colors and the like. Variation differences are removed.

  FIG. 11 is a timing chart showing an operation example of the photoelectric conversion element 10 when the processing unit 129 as a comparative example has a high load. Here, the responsiveness of the input CDSIN to the processing unit 129 having a high load is shown. When the processing unit 129 has a high load, the response of the input CDSIN is slower than that of the signal line Vsig1.

  First, at t5, when the fifth transistor 127 and the fourth transistor 126 are turned on, two switching noises are generated in the direction in which the voltage increases. Here, since the fifth transistor 127 is on, the potential of the signal line Vsig1 converges to V0. However, the voltage of the input CDSIN has a slow response and does not completely converge on the reference voltage V0 of the processing unit 129.

  At t5a, the fifth transistor 127 is turned off, and switching noise in a direction in which the voltage decreases is generated, but the change is also slow at the input CDSIN. At this time, since the signal line Vsig1 serving as the gate signal of SF2 after the offset variation is in a high impedance state as shown by the circled dotted line in FIG. 11, the input CDSIN is connected to the input CDSIN via the parasitic capacitance of SF2. The potential once rises to absorb the potential difference. CDSIN also follows the rise of the signal line Vsig1 with a delay, so that the potential increases.

  At t6, there is also an offset fluctuation due to the switching noise of the second transistor 124, and the initial voltage shifts by ΔVr for the signal line Vsig1 and ΔVrc for the CDSIN.

  After reading the reset voltage, at t7, as in t5, the fifth transistor 127 is turned on, so that switching noise occurs in the direction in which the voltage increases. Here, since the fifth transistor 127 is on, the potential of the signal line Vsig1 converges to V0. However, the voltage of the input CDSIN has a slow response and does not completely converge on the reference voltage V0 of the processing unit 129.

  At t7a, the second transistor 124 turns off, but since the fifth transistor 127 turns on, the potential of the signal line Vsig1 converges to V0. However, the voltage of the input CDSIN has a slow response and does not completely converge on the reference voltage V0 of the processing unit 129.

  At t7b, the fifth transistor 127 is turned off, and switching noise in the direction in which the voltage decreases is generated, but the change is slow at the input CDSIN. Further, as indicated by the dotted line in a circle, after this offset fluctuation, the potential of the signal line Vsig1 once rises according to the same principle as t5a. CDSIN also follows the rise of the signal line Vsig1 with a delay, so that the potential increases.

  However, the start voltage at t7b has a larger potential difference than t5a because t7 is a convergence from the reset voltage. Therefore, in order to absorb the potential difference, the rising voltage is higher than t5a. At t8, since the third transistor 125 is turned on, there is also an offset variation due to switching noise of the third transistor 125, and the initial voltage shifts by ΔVs on the signal line Vsig1 and ΔVsc on the input CDSIN.

  Therefore, due to the above-described voltage change, ΔVr ≠ ΔVs, ΔVrc ≠ ΔVsc, and an error voltage ΔVsc−ΔVrc that cannot be removed even when the processing unit 129 executes the CDS occurs. Note that each settling time may be lengthened so that the voltage fluctuation converges even at the input CDSIN, but the operation speed is hindered. In particular, in the case of a color linear sensor, signals for each color are sequentially read while reading one line, and the effect is increased by the number of color channels.

  FIG. 12 is a diagram illustrating a modification example of a plurality of pixel units 120 arranged in a line in the conversion processing unit 12 and the periphery thereof. In the modification shown in FIG. 12, a sixth transistor (connection transistor PXO) 130 is added between the amplifying transistor 128 and the processing unit 129 in the configuration shown in FIG.

  The timing control unit 14 controls the on / off timing of the sixth transistor 130 so as to prevent unnecessary change of the signal line Vsig1 from being transmitted to the processing unit 129. That is, in the modification shown in FIG. 12, even if the processing unit 129 has a high load, the influence shown in FIG. 11 can be prevented.

  FIG. 13 is a timing chart illustrating the operation of the photoelectric conversion element 10 having the modification shown in FIG. First, the timing control unit 14 turns off the sixth transistor 130 at t5, and disconnects the connection between the amplification transistor 128 and the processing unit 129. When the sixth transistor 130 is turned off and there is no input, the processing unit 129 is connected to the reference voltage V0 so that the input converges to V0.

  Note that the change of the signal line Vsig1 from t5 to t5a is not transmitted to the input CDSIN because the sixth transistor 130 is off. Therefore, there is no sudden voltage fluctuation due to the potential difference absorption between the signal line Vsig1 and the input CDSIN, and the reading of the reset voltage can be started at the initial voltages ΔVr and ΔVrc at t6.

  At times t7 to t7b after reading the reset voltage, the change of the signal line Vsig1 converges to V0c without transmitting to the CDSIN because the change of the signal line Vsig1 is PXO: OFF, similarly to the times t5 to t5a. At t8, signal voltage reading is started with the initial voltages ΔVs and ΔVsc. That is, both the signal line Vsig1 and the input CDSIN have the same initial voltage when reading the reset voltage and when reading the signal voltage, so that the output after the processing unit 129 executes the CDS is | Vr-Vs |.

  As described above, the provision of the sixth transistor 130 enables the photoelectric conversion element 10 to obtain an error-free output even when the processing unit 129 has a high load.

  Next, an image forming apparatus including the image reading device according to the embodiment will be described. FIG. 14 is a diagram schematically illustrating an image forming apparatus 50 including an image reading device 60 having the photoelectric conversion element 10. The image forming apparatus 50 is, for example, a copying machine or an MFP (Multifunction Peripheral) having the image reading device 60 and the image forming unit 70.

  The image reading device 60 includes, for example, the photoelectric conversion element 10, an LED driver (LED_DRV) 600, and an LED 602. The LED driver 600 drives the LED 602 in synchronization with a line synchronization signal or the like output from the timing control unit (TG) 14. The LED 602 irradiates the document with light. The photoelectric conversion element 10 receives reflected light from the document in synchronization with a line synchronization signal or the like, and a plurality of PDs generate electric charges to start accumulation. Then, the photoelectric conversion element 10 outputs image data to the image forming unit 70 after performing parallel-serial conversion or the like.

  The image forming unit 70 has a device processing unit 80 and a printer engine 82, and the device processing unit 80 and the printer engine 82 are connected via an interface (I / F) 84.

  The device processing unit 80 includes an LVDS 800, an image processing unit 802, and a CPU 804. The CPU 804 controls each unit configuring the image forming apparatus 50 such as the photoelectric conversion element 10. Further, the CPU 804 (or the timing control unit 14) controls each PD to start generating electric charges in accordance with the amount of received light substantially simultaneously.

  The photoelectric conversion element 10 outputs to the LVDS 800, for example, image data of an image read by the image reading device 60, a line synchronization signal, a transmission clock, and the like. The LVDS 800 converts received image data, a line synchronization signal, a transmission clock, and the like into parallel 10-bit data. The image processing unit 802 performs image processing using the converted 10-bit data, and outputs image data and the like to the printer engine 82. The printer engine 82 performs printing using the received image data.

Reference Signs List 10 photoelectric conversion element 12 conversion processing unit 14 timing control unit (control unit)
16 Parallel-serial conversion unit 50 Image forming device 60 Image reading device 70 Image forming unit 120 Pixel unit 121 First transistor 122 First capacitor 123 Second capacitor 124 Second transistor 125 Third transistor 126 Fourth transistor 127 Fifth transistor 128 Amplification Transistor 129 Processing unit 130 Sixth transistor

Japanese Patent No. 4846076

Claims (11)

A plurality of pixel units that perform photoelectric conversion according to the amount of received light,
A plurality of first capacitors for holding a reset voltage indicating a reset level of the pixel unit;
A plurality of second capacitors that hold a signal voltage indicating a signal level output by the pixel unit after photoelectric conversion;
A plurality of first transistors that transfer a reset voltage from the pixel unit to the first capacitor via a signal line and transfer a signal voltage from the pixel unit to the second capacitor via the signal line when turned on; When,
A plurality of second transistors that connect the first capacitor to the signal line when turned on;
A plurality of third transistors that connect the second capacitor to the signal line when turned on;
A plurality of fourth transistors that sequentially transfer a reset voltage held by the first capacitor and a signal voltage held by the second capacitor to a subsequent stage via the signal line by turning on;
A plurality of fifth transistors that, when turned on, initialize a potential transferred through the signal line;
A plurality of processing units for calculating a difference between the reset voltage and the signal voltage transferred by the fourth transistor;
Has,
The processing unit includes:
For a first time difference, which is a time difference between the timing at which the fifth transistor is turned off and the timing at which the second transistor is turned on, the timing at which the fifth transistor is turned off and the timing at which the third transistor is turned on of after the second time difference is the same as the time difference, the photoelectric conversion elements and calculates the difference between the signal voltage the reset voltage and the first capacitor is held second capacity is retained. The plurality of pixel units include:
It is arranged in one direction for each color of light received,
The plurality of first transistors, the plurality of second transistors, the plurality of third transistors, the plurality of fourth transistors, and the plurality of fifth transistors are:
The photoelectric conversion element according to claim 1, wherein the plurality of pixel units operate in synchronization with each other for each color of light received. The plurality of first capacities are:
Sequentially holding reset voltages of the plurality of pixel units that respectively receive light of different colors,
The plurality of second capacities are:
Sequentially holding signal voltages of the plurality of pixel units that respectively receive light of different colors,
The fifth transistor includes:
The photoelectric conversion element according to claim 2, wherein the transistor is on when the second transistor is turned off and when the third transistor is turned off. The first time difference and the second time difference are
The photoelectric conversion device according to any one of claims 1 to 3, characterized in that it respectively is zero. The fifth transistor includes:
4. The photoelectric conversion element according to claim 1, wherein the transistor is turned off before the second transistor is turned on, and is turned off before the third transistor is turned on. 5. The third transistor includes:
The transistor size is set so as to generate an error voltage large enough to cancel an error voltage generated by the operation of the second transistor. Photoelectric conversion element. The third transistor includes:
The gate voltage is set so as to generate an error voltage having a magnitude that cancels out an error voltage generated by the operation of the second transistor. The method according to claim 1, wherein: Photoelectric conversion element. A plurality of sixth transistors that respectively connect the signal line and the processing unit by being turned on,
The plurality of sixth transistors include:
8. The signal line and the processing unit are cut off by turning off the plurality of fifth transistors during a period in which the plurality of fifth transistors are turned on, 8. Photoelectric conversion element. There is further provided a control unit that controls a timing at which at least a plurality of the first transistors, a plurality of the second transistors, a plurality of the third transistors, a plurality of the fourth transistors, and a plurality of the fifth transistors are turned on or off. The photoelectric conversion device according to any one of claims 1 to 8, wherein: An image reading apparatus comprising the photoelectric conversion element according to claim 1. An image reading device according to claim 10,
An image forming unit that forms an image based on an output of the image reading device.

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