JP2006245631A - Pulse generating circuit, image pickup device and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse generating circuit capable of keeping a phase relation between a periodic pulse and a non-periodic pulse which are pulses for driving a solid-state image pickup device in a constant state without influenced by a change or variation in temperature, power supply voltage or element characteristic, and to provide an image pickup device and a camera. <P>SOLUTION: A phase control circuit 3 performs phase control of a second clock signal so that it becomes a phase corresponding to the phase of a clock signal CLKI_1. A first timing signal generating circuit 2 generates a pulse of a periodic waveform on the basis of the second clock signal phase-controlled by the circuit 3. A second timing signal generating circuit 4 generates a non-periodic pulses synchronized with clock signals CLKI_2-4. A clock distributing circuit 1 distributes clock signals CLKI_1-4 to the first timing signal generating circuit 2 and the second timing signal geneating circuit 4 without relative delay difference on the basis of the inputted clock signal CLK. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pulse generation circuit that generates a pulse for driving a solid-state imaging device, and an imaging apparatus and camera including the pulse generation circuit.

  In recent years, video cameras and digital still cameras using solid-state imaging devices have been improved in image quality and price. Inevitably, it is desirable that the components used in them also have high performance and low price.

  The pulse generation circuit is an important part that generates a large number of drive pulses used to drive a solid-state image sensor. To improve the image quality, the drive pulses require high-precision timing adjustment. It is desirable that the relative timing of each drive pulse to be generated is always constant even when there are fluctuations in the operating environmental temperature, fluctuations in the power supply voltage, and fluctuations in the element characteristics of the pulse generation circuit itself. On the other hand, there is a strong demand for lower prices, and there are demands for smaller circuits and lower prices.

  For example, a pulse generation method is disclosed in which even when the environmental temperature and power supply voltage of a pulse generation circuit fluctuate, the temperature and voltage are detected and the delay of the pulse is adjusted so that a highly accurate timing adjustment is always possible. (For example, refer to Patent Document 1).

  In addition, for example, a pulse generation circuit is disclosed in which the phase relationship between an input clock and an output pulse is kept constant regardless of changes in temperature, element characteristics, power supply voltage, etc., so that highly accurate timing adjustment is possible at all times. (For example, refer to Patent Document 2).

JP 2001-54027 A JP-A-8-186488

  A pulse generation circuit used in a solid-state imaging device such as a video camera or a digital still camera has a plurality of drive pulses for driving the solid-state imaging device and an AD converter that converts an image signal output from the solid-state imaging device into a digital signal AD clock etc. are generated. The relative timing of these multiple pulses does not depend on the temperature, power supply voltage, and element characteristics of the pulse generation circuit, and must always be constant. In addition, high-precision timing adjustment is required for high image quality. Necessary.

  According to the technique disclosed in Patent Document 1, the temperature detection unit of the pulse generation circuit and the drive voltage detection unit of the pulse generation circuit include the temperature detected by the temperature detection unit, and the voltage detection unit. By providing delay means for delaying and outputting the drive signal according to the detected voltage, there is a possibility that highly accurate timing adjustment can be performed even when the environmental temperature and the drive voltage fluctuate. However, a temperature detection circuit and a voltage detection circuit, and a storage circuit for storing a delay value corresponding to the detected temperature and voltage are necessary, and there is a problem that the circuit scale increases and the cost increases. In addition, there is a problem that timing accuracy cannot be maintained against fluctuations in the manufacturing conditions of the pulse generation circuit.

  Phase adjustment circuits such as a PLL (Phase Locked Loop) circuit and a DLL (Delay Locked Loop) circuit have been conventionally used as means for highly accurate timing adjustment regardless of changes in temperature, power supply voltage, element characteristics, etc. Yes. However, there is a problem that it is difficult to keep the phase relationship between the clock input to the phase adjustment circuit and the output of another circuit constant regardless of changes in temperature or the like. According to the technique disclosed in Patent Document 2, in a PLL circuit and another circuit that receives an output of the PLL circuit as an input, a frequency dividing circuit input in the PLL circuit is used as an output of the other circuit. The phase relationship between the clock input to the other circuit and the output of another circuit can be kept constant regardless of changes in temperature or the like. However, when a pulse other than a pulse having the same periodic waveform as the output of the PLL circuit (aperiodic pulse) is required, the phase relationship between the periodic pulse and the aperiodic pulse is constant regardless of changes in temperature, etc. There is a problem that it is difficult to keep it.

  Specifically, a pulse generation circuit capable of generating a drive pulse having a periodic waveform and a drive pulse having an aperiodic waveform will be described. FIG. 8 is a diagram showing a conventional pulse generation circuit. As shown in FIG. 8, the pulse generation circuit includes a PLL circuit 100, a periodic waveform pulse generation circuit 110, and an aperiodic waveform 120. FIG. 9 is a timing chart showing the operation of the pulse generation circuit of FIG.

  The PLL circuit 100 includes a phase comparator 101, a VCO 102, a frequency divider 103, an LPF (not shown), and the like. The frequency division 103 is a 1/2 frequency divider, and a doubled clock is output from the PLL circuit 100. The periodic waveform pulse generation circuit 110 includes a buffer 111, a NOR gate 112, a NAND gate 113, and the like. As shown in FIG. 8, the periodic waveform pulse generation circuit 110 generates two systems of periodic pulses. The output of the buffer 111 is used as the feedback of the PLL circuit 100 and the input clock CLKi of the aperiodic waveform pulse generation circuit 120.

  As shown in FIG. 9, the CLK waveform and the CLKi waveform are phase-adjusted by the PLL circuit 100, and the phase difference between the rising edges is canceled out. On the other hand, the non-periodic waveform pulse generation circuit 120 receives the clock CLKi fed back to the PLL circuit 100 and receives the clock distribution means 121 for distributing the clock CLKi, the counter 122 driven by the clock CLKi, the combinational circuit 123, the clock CLKi. Flip-flop 124 driven by As shown in FIG. 8, the aperiodic waveform pulse generation circuit 120 generates two systems of aperiodic pulses.

  The clock distribution means 121 is a circuit for distributing the clock to all the clock synchronization circuits such as flip-flops in the non-periodic waveform pulse generation circuit 120 without delay difference, and a plurality of buffers configured in a tree shape is used. It is done. However, since CLKi passes through a plurality of buffers before reaching the clock input terminal of the flip-flop 124, a delay Td1 is generated with respect to CLK as shown in FIG. The pulse output from PO3, including the delay of the flip-flop 124 itself, is delayed by a delay Td2 with respect to CLK. Further, this delay varies greatly depending on temperature, power supply voltage, and element characteristics of the circuit itself. As a result, there arises a problem that it is difficult to keep the phase relationship between the periodic pulse and the aperiodic pulse constant regardless of changes in temperature or the like.

  The present invention has been made in consideration of the above-described circumstances. The phase relationship between a periodic pulse and a non-periodic pulse, which are pulses for driving a solid-state imaging device, is changed or varied in temperature, power supply voltage, element characteristics, and the like. An object of the present invention is to provide a pulse generation circuit, an imaging device, and a camera that can be kept constant without being influenced by the above.

  The present invention has been made to solve the above-described problems, and in the imaging apparatus according to the present invention, the phase control for controlling the phase of the second clock signal so as to have a phase corresponding to the phase of the first clock signal. Means, a first timing signal generating means for generating a periodic waveform pulse based on the second clock signal phase-controlled by the phase control means, a periodic pulse synchronized with the first clock signal, and Based on the second timing signal generating means for generating a non-periodic pulse and the inputted third clock signal, the first timing signal generating means and the second timing signal generating means, Clock distribution means for distributing the first clock signal without relative delay difference.

  An imaging device according to the present invention includes an imaging device and the pulse generation circuit according to any one of claims 1 to 5, and the pulse generation circuit drives a driving pulse for driving the imaging device. Is generated.

  According to another aspect of the present invention, there is provided a camera comprising: the imaging apparatus according to claim 6; and an optical system that focuses light onto the imaging apparatus.

  The pulse generation circuit, the imaging apparatus, and the camera according to the present invention change the phase relationship between a periodic waveform pulse and a non-periodic waveform pulse that drive a solid-state imaging device, such as temperature, power supply voltage, and element characteristics. And can be kept constant without being affected by variations.

The preferred embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a drive circuit (pulse generation circuit) for driving the solid-state imaging device according to the first embodiment of the present invention. As shown in FIG. 1, the drive circuit in the present embodiment includes a clock distribution circuit 1, a first timing signal generation circuit 2, and a second timing signal generation circuit 4. The clock distribution circuit 1 distributes the clock signal CLK input to the clock input terminal CLK to the first timing signal generation circuit 2 and the second timing signal generation circuit 4 as the clock signal CLKI without a relative delay difference. Is possible. The first timing signal generation circuit 2 includes a phase control circuit 3 and can adjust the phase of the input clock signal CKLI to generate a pulse having a periodic waveform (hereinafter referred to as a periodic pulse). The second timing signal generation circuit 4 can generate an aperiodic waveform pulse (hereinafter referred to as an aperiodic pulse) and a periodic pulse synchronized with the clock signal CLKI.

  FIG. 2 is a block diagram showing a detailed configuration example of the drive circuit shown in FIG. In FIG. 2, the same reference numerals as in FIG. 1 denote the same components, 1 is a clock distribution circuit, 2 is a first timing signal generation circuit, 3 is a phase control circuit, and 4 is a second timing signal generation. The circuit is shown.

  As shown in FIG. 2, the clock distribution circuit 1 is configured by connecting the clock root buffer 401 and the clock branch buffer 402 in a tree shape, and similarly connecting the clock branch buffer 402 and the clock leaf buffer 403 in a tree shape. The In FIG. 2, the clock branch buffer 402 is composed of one stage, but the clock branch buffer 402 may be composed of a plurality of stages. The clock leaf buffer 403 is connected to the clock input terminal of the first timing signal generation circuit 2 and the clock input terminals of clock synchronization circuits such as all flip-flops included in the second timing signal generation circuit 4. . Each clock leaf buffer 403 is connected to each circuit and the number of clock synchronization circuits to be connected is equal to a load obtained by equally dividing the entire load when inputting a clock signal to the clock input terminal of each circuit. It has been adjusted. The number of clock leaf buffers 403 connected to each clock branch buffer 402 is similarly adjusted.

  By configuring the clock distribution circuit 1 as described above, the clock distribution circuit 1 outputs the clock signals CLKI_1 to CLKI_4 having the same delay with respect to the clock signal CLK input from the clock input terminal CLK. Since the delays of the clock signal CLK and the clock signals CLKI_1 to CLKI_4 all change uniformly due to changes in temperature, power supply voltage, and element characteristics, each clock synchronization circuit even if the temperature, power supply voltage, and element characteristics change. There is no relative delay difference in the rising timing of the clock signals CLKI_1 to CLKI_4 at the clock input terminals. Specifically, for example, when the clock signal CLKI_1 is delayed by 3 ns (nanoseconds) due to some variation, it can be said that the clock signals CLKI_2 to CLKI_4 are similarly configured to be delayed by 3 ns.

  The first timing signal generation circuit 2 includes a selector 421 and a phase control circuit 3. The phase control circuit 3 includes a tapped delay circuit 431, a control signal generation circuit 432 that controls each delay of the tapped delay circuit 431, an internal clock signal CLKI_1 input from the clock distribution circuit 1, and a tapped delay circuit 431. A phase comparison circuit 433 that compares the phase of the clock signal that has been fed back is a so-called DLL circuit.

  The delay circuit 431 with taps is provided with taps at predetermined positions of a plurality of delay stages connected in cascade, and outputs a plurality of tap outputs given different delay amounts to the input clock signal CLKI_1. The selector 421 selects from the plurality of tap outputs output from the tapped delay circuit 431 and outputs the selected output to the output terminals PO 1 and PO 2 of the first timing signal generation circuit 2. Further, the output of the final stage delay of the tapped delay circuit 431 is fed back to the phase comparison circuit 433. The phase comparison circuit 433 compares the phase of the input clock signal CLKI_1 with the clock signal output from the tapped delay circuit 431 to be fed back. If the phases do not match, the control signal generation circuit 432 is UP (up) or DN. Send a (down) signal. The control signal generation circuit 432 generates a signal for controlling the delay amount of each delay stage of the tapped delay circuit 431 in accordance with the UP or DN signal. By repeating the above processing, the phase control circuit 3 operates so as to match the phase of the final stage output clock signal of the tapped delay circuit 431 and the input clock signal CLKI_1.

  Thus, the first timing signal generation circuit 2 can generate and output a periodic pulse that can finely adjust the rising timing and the falling timing in the same cycle as the input clock signal CLKI_1.

  The second timing signal generation circuit 4 also synchronizes the synchronization counter 122 that operates with the clock signal CLKI_2, the combinational circuit 123 that decodes the counter value, and the outputs of the combinational circuit 123 with the clock signals CLKI_3 and CLKI_4. And a flip-flop 124. Thereby, the second timing signal generation circuit 4 can generate and output a periodic pulse synchronized with the clock signal CLKI and an aperiodic pulse.

  Next, a response to changes in temperature and power supply voltage of the drive circuit shown in FIGS. 1 and 2 will be described. FIG. 3 is a diagram illustrating a correspondence example with respect to changes in temperature and power supply voltage of the drive circuit illustrated in FIGS. 1 and 2. Compared with the upper timing chart of FIG. 3, the lower timing chart shows a case where the temperature and power supply voltage of the drive circuit change.

  As shown in the upper part of FIG. 3, the clock signals CLKI_1 to 4 output from the clock distribution circuit 1 have the same delay Td_clki with respect to the clock signal CLK. The output signals of the output terminals PO1 and PO2 of the first timing signal generation circuit 2 are output by the phase control circuit 3 as pulses having the same cycle as that of the clock signal CLKI_1. The phase relationship between the clock signal CLKI_1 and the output signals of the output terminals PO1 and PO2 is always constant.

  Further, the output signal of the output terminal PO3 of the second timing signal generation circuit 4 is output in synchronization with the clock signal CLKI_3, and the timing of the signal change depends on the output delay of the flip-flop 124 with respect to the rising timing of CLKI_3. Delay Td_po3.

  When the temperature and the power supply voltage fluctuate from the upper stage in FIG. 3, the delay Td_clki from CLKI_1 to CLKI_1 fluctuates from the input clock CLK as shown in the lower stage in FIG. However, when compared in the clock signals CLKI_1 to 4, the rising timing is always the same. Since the output signals of the output terminals PO1 and PO2 of the first timing signal generation circuit 2 are fixed in phase according to the clock signal CLKI_1, the phase relationship with respect to the clock signal CLKI_1 even if the temperature, the power supply voltage, etc. fluctuate. Is constant. On the other hand, since the output signal of the output terminal PO3 of the second timing signal generation circuit 4 is synchronized with the clock signal CLKI_3, the signal change timing is the output of the flip-flop 124 with respect to the rising timing of the clock signal CLKI_3. It is delayed by the delay Td_po3 corresponding to the delay, and the rate of change when the temperature and the power supply voltage fluctuate is very small compared to the rate of change of Td_clki.

  Although FIG. 3 illustrates an example of changes in temperature and power supply voltage, the drive circuit of the present embodiment is similarly applied to any change in temperature, power supply voltage, element characteristics, or a combination thereof. Is available.

  As described above, the drive circuit according to the first embodiment affects, for example, the phase relationship between the periodic pulse and the aperiodic pulse that drive the solid-state imaging device, and changes in temperature, power supply voltage, and device characteristics. Can be kept constant without being done. Further, the first timing signal generation circuit 2 can generate and output a pulse whose rising edge and falling edge can be finely adjusted in the same cycle as the input clock signal CLK. The second timing signal generation circuit 4 makes it possible to generate and output a periodic pulse having a relatively long period and an aperiodic pulse that can be adjusted in units of the input clock signal CLK.

[Second Embodiment]
FIG. 4 is a block diagram showing a detailed configuration of a drive circuit that drives the solid-state imaging device according to the second embodiment of the present invention. The schematic configuration of the drive circuit in the second embodiment is the same as that in FIG. 4 having the same reference numerals as those in FIG. 1 have similar functions.

  As is clear from the comparison between FIG. 4 and FIG. 2, the driving circuit in the second embodiment has a phase of the first timing signal generating circuit 2 as compared with the driving circuit in the first embodiment shown in FIG. The main difference is that the control circuit 3 is composed of a phase comparison circuit 631 and a VCO 632. That is, the phase control circuit 3 constitutes a PLL circuit. Here, the output of the VCO 632 is input to a counter 621 that can output a 1 / N divided signal. The 1 / N frequency-divided signal output from the counter 621 is fed back to the phase comparison circuit 631 and phase-compared with the clock signal CLKI. If the phases do not match, the phase comparison circuit 631 outputs a signal corresponding to the phase difference, controls the VCO 632, and the phase of the clock signal output by the VCO 632 so that the phase matches the 1 / N frequency-divided signal Is adjusted. As a result, the VCO 632 outputs an N-multiplied clock signal of the clock signal CLKI.

  The combinational circuit 622 is a circuit that decodes the counter value of the counter 621, and can generate a rising signal and a falling signal based on the counter value. The signal output from the combinational circuit 622 is output from the output terminals PO1 and PO2 by the flip-flop 124 in synchronization with the multiplied clock signal. As described above, the first timing signal generation circuit 2 of FIG. 4 can adjust the rising and falling timings in the same cycle with respect to the input clock signal CLKI in units of 1 / N of the cycle of the clock signal CLKI. Periodic pulses can be generated. That is, the drive circuit of FIG. 4 can obtain the same effect as the drive circuit in the first embodiment of FIG.

[Example 1]
Next, with reference to FIG. 5, a description will be given of a first embodiment in which the drive circuit of FIG. 1 is applied to an imaging apparatus. FIG. 5 is a block diagram illustrating a configuration example of the imaging apparatus. In FIG. 5, a pulse generation circuit 705 described later is a block including the drive circuit of FIG.

  In FIG. 5, reference numeral 701 denotes a solid-state image sensor for capturing a subject as a video signal. Reference numeral 702 denotes a video signal processing circuit that performs analog signal processing on the imaging signal output from the imaging element 701. Reference numeral 703 denotes an AD converter that performs analog-to-digital conversion of the imaging signal output from the video signal processing circuit 702. A signal processing unit 704 performs various corrections on the image data output from the AD converter 703 and compresses the data. A pulse generation circuit 705 outputs various drive pulses to the solid-state imaging device 701, the video signal processing circuit 702, and the AD converter 703. A general control unit 706 controls various calculations and the entire solid-state imaging device.

  Next, the operation of the image pickup apparatus having the above configuration will be described. In accordance with control signals such as a vertical synchronization signal and a horizontal synchronization signal from the overall control unit 706, the pulse generation circuit 705 outputs various drive pulses for the solid-state image sensor 701. The solid-state imaging device 701 performs exposure and transfer of an imaging signal generated by the exposure by the driving pulse. The imaging signal generated by the solid-state imaging device 701 is converted into a digital signal by the AD converter 703 via the video signal processing circuit 702, and then input to the signal processing unit 704 to perform various corrections and data compression processing. .

  In the description of FIG. 7, the solid-state imaging device 701, the video signal processing circuit 702, the AD converter 703, and the pulse generation circuit 705 are configured as separate devices, but the present invention is not limited to this, and the solid-state imaging device The video signal processing circuit 702, the AD converter 703, and the pulse generation circuit 705 may be configured by one chip.

[Example 2]
Next, with reference to FIG. 6, a second embodiment when the drive circuit of FIG. 1 is applied to an imaging apparatus will be described. FIG. 6 is a block diagram showing a case where the drive circuit of FIG. 1 is applied to a “still video camera” that is an imaging device. 1 is included in a timing generator 8 described later.

  In FIG. 6, 1 is a barrier that serves as a lens switch and a main switch, 2 is a lens that forms an optical image of a subject on the solid-state imaging device 4, 3 is a stop for changing the amount of light passing through the lens 2, and 4 is A solid-state imaging device for capturing an object imaged by the lens 2 as an image signal, 6 an A / D converter that performs analog-digital conversion of an image signal output from the solid-state imaging device 4, and 7 an A / D conversion The signal processing unit 8 performs various corrections on the image data output from the device 6 and compresses the data. The solid state image sensor 4, the imaging signal processing circuit 5, the A / D converter 6, and the signal processing unit 7 A timing generator for outputting a timing signal, 9 is an overall control / arithmetic unit for controlling various operations and the entire still video camera, 10 is a memory unit for temporarily storing image data, and 11 is a recording medium. Interface unit for performing recording or reading, 12 removable recording medium such as a semiconductor memory for recording or reading of the image data, 13 denotes an interface unit for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
When the barrier 1 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 6 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 9 opens the diaphragm 3, and the signal output from the solid-state imaging device 4 is converted by the A / D converter 6 and then sent to the signal processing unit 7. Entered. Based on this data, exposure calculation is performed by the overall control / calculation unit 9.

The brightness is determined based on the result of the photometry, and the overall control / calculation unit 9 controls the aperture according to the result. Next, based on the signal output from the solid-state imaging device 4, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.
Then, after the in-focus state is confirmed, the main exposure starts.

  When the exposure is completed, the image signal output from the solid-state imaging device 4 is A / D converted by the A / D converter 6, passes through the signal processing unit 7, and is written in the memory unit by the overall control / calculation unit 9. Thereafter, the data stored in the memory unit 10 is recorded on a removable recording medium 12 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 9. Further, the image may be processed by directly entering the computer or the like through the external I / F unit 13.

[Example 3]
Next, with reference to FIG. 7, a third embodiment in which the drive circuit of FIG. 1 is applied to an imaging apparatus will be described. FIG. 7 is a block diagram showing a case where the drive circuit of FIG. 1 is applied to a “video camera” that is an imaging device. Note that the drive circuit in FIG. 1 transmits a control pulse to a solid-state imaging device 3 and a sample hold circuit 4 to be described later. Here, the drive circuit is not particularly shown in FIG.

  In FIG. 7, reference numeral 1 denotes a photographing lens that includes a focus lens 1A for performing focus adjustment, a zoom lens 1B for performing a zoom operation, and an imaging lens 1C. 2 is a stop, 3 is a solid-state image sensor that photoelectrically converts an object image formed on the imaging surface to convert it into an electrical image signal, 4 is a sample-and-hold image signal output from the solid-state image sensor 3, and A sample hold circuit (S / H circuit) that amplifies the level and outputs a video signal.

  A process circuit 5 performs predetermined processing such as gamma correction, color separation, and blanking processing on the video signal output from the sample hold circuit 4, and outputs a luminance signal Y and a chroma signal C. The chroma signal C output from the process circuit 5 is subjected to white balance and color balance correction by the color signal correction circuit 21 and output as color difference signals RY and BY.

  Also, the luminance signal Y output from the process circuit 5 and the color difference signals RY and BY output from the color signal correction circuit 21 are modulated by an encoder circuit (ENC circuit) 24, and are used as standard television signals. Is output. Then, it is supplied to a monitor EVF such as a video recorder (not shown) or an electronic viewfinder.

  Next, reference numeral 6 denotes an iris control circuit, which controls the iris driving circuit 7 based on the video signal supplied from the sample and hold circuit 4 and opens the aperture 2 so that the level of the video signal becomes a predetermined value. The ig meter is automatically controlled to control the amount.

  Reference numerals 13 and 14 denote different band-limited bandpass filters (BPFs) for extracting high-frequency components necessary for performing focus detection from the video signal output from the sample and hold circuit 4. The signals output from the first band pass filter 13 (BPF 1) and the second band pass filter 14 (BPF 2) are gated by the gate circuit 15 and the focus gate frame signal, respectively, and the peak value is detected by the peak detection circuit 16. Is detected and held, and input to the logic control circuit 17.

  This signal is called a focus voltage, and the focus is adjusted by this focus voltage. Reference numeral 18 denotes a focus encoder that detects the moving position of the focus lens 1A, 19 denotes a zoom encoder that detects the focal length of the zoom lens 1B, and 20 denotes an iris encoder that detects the opening amount of the diaphragm 2. The detection values of these encoders are supplied to a logic control circuit 17 that performs system control.

  The logic control circuit 17 performs focus detection by performing focus detection on the subject based on a video signal corresponding to the set focus detection area. That is, the peak value information of the high frequency components supplied from the respective band pass filters 13 and 14 is taken in, and the focus motor 10 is supplied to the focus drive circuit 9 to drive the focus lens 1A to the position where the peak value of the high frequency components is maximized. Control signals such as a rotation direction, a rotation speed, and rotation / stop are supplied and controlled.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

It is a block diagram which shows schematic structure of the drive circuit (pulse generation circuit) which drives the solid-state image sensor in 1st embodiment of this invention. FIG. 2 is a block diagram illustrating a detailed configuration example of a drive circuit illustrated in FIG. 1. FIG. 3 is a diagram illustrating a correspondence example with respect to changes in temperature and power supply voltage of the drive circuit illustrated in FIGS. 1 and 2. It is a block diagram which shows the detailed structure of the drive circuit which drives the solid-state image sensor in 2nd embodiment of this invention. It is a block diagram which shows the structural example of an imaging device. It is a block diagram which shows the case where the drive circuit of FIG. 1 is applied to the "still video camera" which is an imaging device. It is a block diagram which shows the case where the drive circuit of FIG. 1 is applied to the "video camera" which is an imaging device. It is a figure which shows the conventional pulse generation circuit. 9 is a timing chart showing an operation of the pulse generation circuit of FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Clock distribution circuit 2 1st timing signal generation circuit 3 Phase control circuit 4 2nd timing signal generation circuit 122 Counter 123 Combination circuit 124 Flip-flop 401 Clock route buffer 402 Clock branch buffer 403 Clock leaf buffer 421 Selector 431 Tap delay Circuit 432 Control signal generation circuit 433 Phase comparison circuit 621 Counter (1 / N frequency dividing circuit)
622 Combinational circuit 631 Phase comparison circuit 632 VCO
701 Image sensor 702 Video signal processing circuit 703 AD converter 704 Signal processing unit 705 Pulse generation circuit 706 Overall control unit

Claims (7)

Phase control means for performing phase control of the second clock signal so as to have a phase corresponding to the phase of the first clock signal;
First timing signal generating means for generating a pulse having a periodic waveform based on the second clock signal phase-controlled by the phase control means;
Second timing signal generating means for generating a periodic pulse and / or an aperiodic pulse synchronized with the first clock signal;
Clock distribution for distributing the first clock signal to the first timing signal generating means and the second timing signal generating means without relative delay difference based on the inputted third clock signal And a means for generating a pulse.   The clock distribution means has a configuration in which a plurality of buffers are connected in a tree shape, and the output loads of the buffers connected to the same stage of the tree are configured to be the same. The pulse generation circuit according to claim 1.   When the phase control unit performs phase control using a tapped delay circuit including a plurality of delay elements, the first timing signal generation unit is included in the tapped delay circuit. The pulse generation circuit according to claim 2, wherein the output of any one of the delay elements is selected and output.   The phase control means performs phase control using a VCO and a frequency divider, and the VCO is an integral multiple of the frequency of the first clock according to the frequency division by the frequency divider. 3. The pulse generation circuit according to claim 2, wherein the second clock signal having a frequency of 1 is output. 4. The second timing signal generating means is
A counter that counts changes in the first clock signal output from the clock distribution means;
A logic circuit that generates a rising pulse or a falling pulse with reference to a count value of the counter;
4. A synchronous output circuit that outputs the rising pulse or the falling pulse output from the logic circuit as a pulse signal synchronized with the first clock signal output from the clock distribution unit. Or the pulse generation circuit of 4. An image sensor;
Comprising the pulse generation circuit according to any one of claims 1 to 5,
An imaging apparatus, wherein the pulse generation circuit generates a driving pulse for driving the imaging element.   A camera comprising: the imaging apparatus according to claim 6; and an optical system that forms an image of light on the imaging apparatus.

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