JPH09200454A - Image reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the image reader which can easily obtain an optimum timing signal for image signal processing. SOLUTION: A phase shifting circuit 22 is arranged for a timing generating circuit 20. Further, the phase shifting circuit 22 is composed of a delay circuit which has plural delay elements or provided with plural output terminals which have different previously set delay quantities. Consequently, even if a product is partially changed in specifications or if a custom IC has a difference in delay time, the timing generating circuit which generates various clocks need not be reviewed at each time. Further, a waveform signal monitor circuit 15 and an optimum timing detecting circuit 16 are arranged to automatically detect the optimum timing of various timing signals and vary and set it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading device, and more particularly to an image reading device in a copying machine, a video camera or the like.

[0002]

2. Description of the Related Art Conventionally, an apparatus having a reading element such as a CCD, for example, an image reading apparatus having an original reading section of a copying machine or a reading section of a video camera, reads a new product of the copying machine or the video camera. The signal processing circuit associated with the element and the reading element uses the one before the new product, and only the processing speed is increased, that is, a so-called upgraded version has been issued as the new product.

FIG. 6 shows a CCD used in a document reading device of a conventional digital copying machine or a video camera.
An example of 60 signal processing circuits is shown, and in FIG.
The waveform of the image signal in each block of the signal processing circuit is shown.

FIG. 7A shows an image signal read by the CCD 60. Odd and Even mean output signals of odd-numbered and even-numbered pixels of the CCD 60. Particularly, the CCD operated at a high speed is of a two-phase drive type in order to improve the output efficiency. Odd and Ev
En is out of phase with each other, and each pixel includes a reset period, a field through period, and an image output period. As shown in FIG. 7A, the image output period is The period during which the pixel occupies only about half of one pixel and is flat and the output is stable is about half of the period.

The sample hold circuit 61 samples and holds the image signal in the stable period of the image output period. In this example, the sample clock is held in synchronization with the falling edge of the sample clock (FIG. 7B).

The channel synthesizing circuit 62 is a so-called gate circuit, which is the output signals of the pixels Odd and Even.
To synthesize. At this time, the composite clock is High and Od
When d is Low, Even is valid (FIG. 7 (c)).

The amplifier circuit 63 sets the image signal at a predetermined level. The A / D conversion circuit 64 includes the amplifier circuit 6
It is a circuit for converting the analog image signal amplified in 3 into a digital signal, and the A / D conversion timing is assumed to be the rising edge of the A / D clock in this example (FIG. 7 (d)).

The timing generation circuit 65 generates the timing signals of the sample clock, the composite clock, and the A / D clock, and outputs them to each circuit of each signal processing circuit 600. The timing generation circuit 65 is an aggregate of logic circuits, and is designed as an LSI so as to obtain optimum timing for each signal processing.

However, when the product is upgraded, the timing generation circuit 65 may be a custom IC.
Since it was not possible to control and manage the delay time of each gate and the stray capacitance on the load side, it had to be reviewed every time at the design stage.

For example, when the clock frequency is set to double, it is not necessary to replace the oscillator with one that matches the frequency, but a new design for optimizing the phase of each timing is newly added. Had to do (new design).

Further, even in the same product, the delay time and stray capacitance of the custom IC may differ for each product, and several tens of gates are used in the custom IC to generate the required timing. The difference between the maximum and minimum delay times is large (mechanical difference).

Further, even in the same machine, the delay time may change due to changes in the ambient temperature of the machine (change over time), and the same applies to machines having a high image quality mode that slows down the processing speed. The delay time is different (mode difference) because it operates at different frequencies in the machine.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the conventional drawbacks and to provide an image reading apparatus capable of easily obtaining an optimum timing signal for signal processing of an image signal.

[0014]

An image reading apparatus according to the present invention includes a plurality of photoelectric conversion elements that perform photoelectric conversion according to an optical image, and a predetermined image area of an image signal obtained by the plurality of photoelectric conversion elements. Image signal processing means for extracting and synthesizing
The image signal processing means has timing generation means for generating a control signal for performing each processing operation, and the phase generation means has a phase varying means for varying the phase of the output control signal.

In the image reading apparatus of the present invention, the phase changing means is composed of a delay circuit having a plurality of delay elements.

In the image reading apparatus of the present invention, a plurality of output terminals having different preset delay amounts are arranged in the phase varying means.

The image reading apparatus of the present invention further includes a predetermined one of analog / digital converting means for converting the analog image signal obtained by the image signal processing means into digital and digital image data obtained by the analog / digital converting means. Waveform signal monitoring means for monitoring the digital image data of the area as a waveform signal, and timing detecting means for detecting the optimum timing for extracting a predetermined image area by the image signal processing means from the digital image data monitored by the waveform signal monitoring means. Including and

[0018]

1 shows an embodiment of an image reading apparatus according to the present invention. The image reading apparatus of this embodiment mainly includes a CCD 10 as photoelectric conversion means, a sample hold circuit 11, a channel synthesis circuit 12, an amplification circuit 13, an A / D conversion circuit 14 as analog / digital conversion means, and a waveform signal monitoring means. , A waveform signal monitor circuit 15 as the above, an optimum timing detection circuit 16 as the timing detection means, a timing generation circuit 20 as the timing generation means, and a phase variable circuit 22 as the phase variable means.

The CCD 10 is a solid-state image sensor, and converts the optical image of the object field formed through a lens system (not shown) or the reflected light of the document into an analog signal having a voltage value according to the intensity of the light. .

Signal processing circuit 1 as image signal processing means
00 is composed of a sample hold circuit 11, a channel synthesizing circuit 12 and an amplifying circuit 13, and a CCD
10, the phase variable circuit 22 and the A / D conversion circuit 14 are connected. The signal processing circuit 100 includes the phase variable circuit 2
CCD in response to various timing signals supplied from 2
Image analog signals input from 10 are processed and A / D
Output to the conversion circuit 14.

The sample hold circuit 11 samples and holds the image signal in the stable period of the image output period shown in FIG. 7A in response to the adjusted sample clock supplied from the phase variable circuit 22. To do. The channel synthesizing circuit 12 is a so-called gate circuit, and is a phase variable circuit 2
The pixel output signals Odd and Even are combined in response to the adjusted channel combination clock supplied from 2. The amplifier circuit 13 sets the image signal at a predetermined level. The sample hold circuit 11 has
There are a normal mode and a through mode, which are output as they are without being processed in the through mode.

The A / D conversion circuit 14 includes a phase variable circuit 22.
The analog image signal amplified by the amplifier circuit 13 in response to the adjusted A / D clock supplied from the converter is converted into a digital signal. The A / D conversion circuit 14 may be of a high speed type.

FIG. 2 shows an enlarged configuration diagram of the timing generation circuit 20 and the phase variable circuit 22. The timing generation circuit 20 is connected to the phase variable circuit 22, generates timing signals of the sample clock, the combined clock, and the A / D clock, and supplies them to the phase variable circuit 22.

The phase variable circuit 22 is connected to the timing generation circuit 20, the signal processing circuit 100, the A / D conversion circuit 14 and the detection circuit 16. The phase variable circuit 22 is
It is composed of a plurality of gate circuits or RCL circuits, performs phase adjustment of clocks which are various timing signals input from the timing generation circuit 20 according to delay amount data of various clocks input from the detection circuit 16, and outputs various adjusted clocks. The signal is supplied to the sample hold circuit 11, the channel synthesizing circuit 12, and the A / D conversion circuit 14 of the signal processing circuit 100.

The waveform signal monitor circuit 15 is connected to the A / D conversion circuit 14 and the optimum timing detection circuit 16. The waveform signal monitor circuit 15 is composed of a storage device such as a memory, monitors digital image data of one pixel input from the A / D conversion circuit 14 as a waveform signal, and outputs it to the optimum timing detection circuit 16.

The optimum timing detection circuit 16 is connected to the waveform signal monitor circuit 15 and the phase variable circuit 22, detects the delay amount data of various clocks from the waveform signal of the image data input from the waveform signal monitor circuit 15, and detects the phase. It is supplied to the variable circuit 22.

Now, the operation of the image reading apparatus of this embodiment will be described. First, the through mode is selected for both the sample and hold circuit 11 and the channel synthesizing circuit 12 of the signal processing circuit 100, and the channel synthesizing circuit 12 selects Od.
Select either d or Even.

The A / D conversion circuit 14 operates at high speed by increasing the frequency of the A / D clock by about 10 times the normal frequency. That is, in this case, the amplified output from the CCD 10 is A / D converted, and digital data having a waveform as shown in FIG. 7A is obtained.

This digital data is input to the waveform signal monitor circuit 15, and the image data for one pixel, for example, is monitored as a waveform signal. The optimum timing detection circuit 16 receives the waveform signal of the image data, and detects which part of one pixel is appropriate as the temporal position of the sample and hold.

The detection method may be carried out while detecting the image data, and for example, the center of the flat portion of the image output period having the waveform as shown in FIG. 7A may be selected. Of course, the middle of the A / D converted positions can be selected by interpolating the data.

The optimum timing of the sample clock detected here is supplied to the phase variable circuit 22 as a delay amount with respect to the original clock, and the phase-adjusted sample clock is obtained. This operation is performed for Odd and Even, respectively.

Next, the optimum timing of the combined clock is similarly detected. At this time, the sample and hold circuit 11 is in the normal mode, and the sample clock has its phase adjusted. Further, the channel synthesizing circuit 12 is in the through mode and the A / D converting circuit 14 operates at high speed. Then, the sample-and-hold and amplified image signals are A / D converted, and digital data having a waveform as shown in FIG. 7B is obtained.

After that, the same operation as described above is performed, so that the digital data is input to the waveform signal monitor circuit 15 so that the image data for one pixel of Odd and Even can be monitored, and this image data is detected by the optimum timing detection circuit 16. Then, the optimum amount of delay is detected and the phase variable circuit 2
Feed to 2.

With respect to the A / D clock, the same operation as described above is performed except that both the sample hold circuit 11 and the channel synthesizing circuit 12 are set to the normal mode. .

FIG. 3 shows another embodiment of the image reading apparatus according to the present invention. As shown in FIG. 3, a delay line 30 having a plurality of delay taps 32 is connected to a sample clock, a composite clock, and an A / D.
There are multiple timing signals for the clock,
The delay tap 32 of each delay line 30 can be selected.

More specifically, the delay line 30 has 5 taps at 10 ns intervals and 5 taps at 2 ns intervals.
When a jumper switch or the like that selects one from 5 taps (6 taps including no delay) is prepared, it is possible to select a delay amount from 0 to 60 ns in 2 ns increments by combining these.

FIG. 4 shows another embodiment of the image reading apparatus according to the present invention. In this example, a plurality of A
It is composed of an ND circuit, an OR circuit, and a NOT circuit. It is possible to prepare two different delay amounts for one timing in advance and select one of the delay amounts as needed.

In a copying machine, especially a high-quality color copying machine,
In some cases, a mode for higher image quality is prepared. In this mode, the S / N ratio of the image signal is increased by slowing down the operation speed, and the developing conditions are stabilized. In this case, it is necessary to change the frequency of the image signal, and it is necessary to change the setting of the phase of the timing of each signal processing.

The operation of the apparatus of the embodiment shown in FIG. 4 will be described below.
First, the phase at each timing in the normal mode and the special mode is adjusted in advance by the phase variable circuit 22 in FIG. 2 or 3. As a result, two output terminals having different delay amounts are formed.

Next, in selecting the delay amount by mode switching when the device is actually used, a mode signal (in this embodiment, High is a normal mode and Low is a special mode) is supplied from the device body. When input, a logical product of the input mode signal and the timing having each delay amount is taken, and the logical sum of the outputs is taken to obtain the timing having the delay amount corresponding to the mode.

FIG. 5 shows another embodiment of the image reading apparatus according to the present invention. The circuit shown in FIG. 5 is a circuit that, when two or more delay amounts are set, selects one delay amount from the set delay amounts. The LSI 50 is a selector, which is an IC that selects and outputs one of the eight inputs, and which input is valid is determined by the states of the selected data input terminals A, B, and C. According to this circuit, not only mode switching,
Even if the phase correction is necessary due to a change with time such as a change in the ambient temperature of the device, it is possible to deal with it. In this case, it is necessary to preset the delay amount corresponding to the ambient temperature.

Although the two-phase output CCD is used in the embodiment of the present invention, it goes without saying that a CCD other than the two-phase output can be used, and when a relatively low speed reading device is used. In some cases, sample hold and channel synthesis are unnecessary.

[0043]

As is apparent from the above description, according to the image reading apparatus of the present invention, the phase variable circuit is arranged at each output of the timing generation circuit, and the sample clock, the composite clock, and the A / D clock are provided. Since it is possible to change each timing signal, it is not necessary to reexamine the timing generation circuit that generates various clocks each time even if the specifications of a product are partially changed or the delay time of the custom IC varies. .

The phase variable circuit 22 is composed of a delay circuit having a plurality of delay elements, and a plurality of circuits are prepared for each of various timing signals.
A more precise delay amount can be selected.

Further, since the phase variable circuit 22 is provided with a plurality of output terminals having different preset delay amounts, when a signal for mode switching is input, the delay amount is selected according to the signal. It

Further, according to the image reading apparatus of the present invention,
Since the waveform signal monitor circuit 15 and the optimum timing detection circuit 16 are provided in the device, it is possible to automatically detect the optimum timings of various timing signals, and change and set the optimum timings.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a configuration example of an image reading apparatus of the present invention.

FIG. 2 is an enlarged configuration diagram of a timing generation circuit and a phase variable circuit of the device shown in FIG.

FIG. 3 is a partial circuit diagram showing another embodiment of the image reading apparatus of the present invention.

FIG. 4 is a partial circuit diagram showing another embodiment of the image reading apparatus of the present invention.

FIG. 5 is a partial circuit diagram showing another embodiment of the image reading apparatus of the present invention.

FIG. 6 is a functional block diagram showing a configuration example of a conventional image reading device.

7 is a timing diagram showing an example of signal waveforms of the device shown in FIG.

[Explanation of symbols]

 10, 60 CCD 11, 61 Sample and hold circuit 12, 62 Channel combination circuit 13, 63 Amplification circuit 14, 64 A / D conversion circuit 15 Waveform signal monitor circuit 16 Optimal timing detection circuit 20, 65 Timing generation circuit 22 Phase variable circuit

Claims (4)

[Claims] 1. A plurality of photoelectric conversion elements for performing photoelectric conversion according to an optical image, and image signal processing means for extracting a predetermined image region from image signals obtained by the plurality of photoelectric conversion elements and synthesizing the image signals. An image reading apparatus having a timing generation unit that generates a control signal for performing each processing operation in the image signal processing unit, wherein the device is a phase of the control signal generated and output by the timing generation unit. An image reading apparatus having a phase changing means for changing the. 2. The image reading apparatus according to claim 1, wherein the phase varying unit is composed of a delay circuit having a plurality of delay elements. 3. The image reading apparatus according to claim 1, wherein the phase varying means is provided with a plurality of output terminals having different preset delay amounts. 4. The image reading device further includes an analog / digital conversion unit for converting the analog image signal obtained by the image signal processing unit into a digital signal, and digital image data obtained by the analog / digital conversion unit. A waveform signal monitor means for monitoring digital image data of a predetermined area as a waveform signal, and an optimum timing for extracting the predetermined image area by the image signal processing means from the digital image data monitored by the waveform signal monitor means. 4. The image reading apparatus according to claim 1, further comprising a timing detection unit that operates.