JP2006042261A - Image pickup device and control method for timing signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image pickup device capable of executing the sampling and holding of a CCD output signal at proper timing corresponding to a CCD drive frequency even if the CCD drive frequency is changed. <P>SOLUTION: A timing signal phase information table in which phase conditions of a timing signal supplied to an image pickup drive part 103 and an analog signal processing part 104 are determined for each CCD drive frequency is stored in a memory 118. Even if the CCD drive frequency is switched, phase conditions corresponding to the CCD drive frequency are set by referring to the timing signal phase information table. The phase of the timing signal generated by a timing signal generating part 117 is properly changed at a timing signal phase changing part 118. Therefore, even when the CCD drive frequency is changed, the sampling and holding of the drive of an image pickup part 102 and the output signal from the image pickup part 102 can be executed at proper timing corresponding to the CCD drive frequency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an imaging apparatus and a timing signal control method, and is particularly suitable for use in an electronic camera or the like capable of recording and reproducing an image captured by a solid-state imaging device such as a CCD.

  2. Description of the Related Art In recent years, imaging devices such as electronic cameras that record and reproduce still images and moving images captured by a solid-state imaging device such as a CCD using a memory card having a solid-state memory element as a recording medium have been actively developed and marketed.

FIG. 8 is a block diagram illustrating a general configuration of an image input unit in an imaging apparatus such as an electronic camera.
In FIG. 8, 801 is a CCD sensor which is a solid-state imaging device, 805 is a CCD driving circuit, 802 is a correlated double sampling (hereinafter CDS) circuit, 803 is an amplifier, and 804 is an analog-digital converter (hereinafter ADC). is there.

  The CCD sensor 801 is driven by signals such as a horizontal transfer pulse, a reset gate pulse, a vertical transfer pulse, and an electronic shutter pulse supplied from the CCD drive circuit 805, and converts an optical image of a subject into an electrical signal. Among the signals supplied from the CCD drive circuit 805, in particular, the phases and pulse widths of the horizontal transfer pulse and the reset gate pulse change the one-pixel periodic signal waveform of the CCD output.

  It is common to have a CDS circuit 802 for removing a reset noise component generated at the time of CCD transfer at the subsequent stage of the CCD sensor 801. Inside the CCD sensor 801, the charge exposed and accumulated by the light receiving element is transferred to the floating capacitor of the output unit for each pixel by the transfer pulse, and the signal of one pixel is supplied from the floating capacitor to the output buffer and converted into a voltage signal. Thus, video signals in units of one pixel are sequentially output. The floating capacitor is cleared by a reset pulse every time a signal of one pixel is output.

  Thus, the output signal of the CCD sensor 801 is composed of a feed-through portion and a video signal portion in which the reset component generated by the reset operation of the floating capacitor and the correlation noise of the reset pulse are superimposed for each pixel. The CDS circuit 802 is a noise removing circuit that obtains a difference between the signal level of the feedthrough portion and the signal level of the video signal portion of the output signal of the CCD sensor 801 and thereby eliminates the correlation noise component from the video signal. .

  FIG. 9 is a block diagram showing a basic configuration of a general CDS circuit. FIG. 10 shows a sample and hold circuit for extracting the signal level of the feedthrough portion and the signal level of the video signal portion by the CDS circuit. It is a figure which shows a control timing.

9 and 10, CCDOUT is an output signal of the CCD sensor, SHP is a pulse signal for sample-holding a signal in the feedthrough period TP for holding the reset level, and SHD is a signal in the video signal output period TD. Is a pulse signal for sample-holding.
The CDS circuit samples and holds the output signal CCDOUT of the CCD sensor in accordance with the pulse signals SHP and SHD by the sample and hold circuits 901 and 902 and the sample and hold circuit 903 connected in series. The difference of each output is taken.

  Returning to FIG. 8, the output image pickup signal of the CDS circuit 802 is amplified to a predetermined signal level in accordance with the input range of the ADC 804 by the amplifier 803, converted into a digital signal by the ADC 804, and further a digital signal processing circuit ( (Not shown).

  Here, in recent years, an imaging apparatus such as an electronic camera tends to increase in resolution and operation speed related to shooting year by year in response to market needs for higher image quality and higher definition. However, there are many types of such image pickup apparatuses having a high-speed continuous shooting function, an electronic viewfinder (hereinafter, EVF) function, and a moving image shooting function. To realize these functions, the CCD drive frequency is increased. There is a need. However, since the power consumption of the imaging system is proportional to the frequency, increasing the CCD drive frequency increases the power consumption and greatly reduces the number of images that can be taken. On the other hand, there is one that changes the CCD drive frequency in accordance with the operation status of the imaging device (see, for example, Patent Document 1).

JP 2001-268453 A

However, when the CCD drive frequency is varied in the image pickup apparatus, there are the following problems.
The timing at which the signal is sampled and held by the CDS circuit described above greatly contributes to the signal-to-noise ratio (hereinafter referred to as S / N) of the image pickup signal, and is therefore optimal for performing sample and hold so as to maximize the S / N. The phase and pulse width may vary depending on the CCD drive frequency.
Further, each phase and pulse width of the horizontal transfer pulse and the reset gate pulse change the one-pixel period signal waveform of the CCD output, so that the S / N is maximized by changing the CCD output signal waveform according to the CCD driving frequency. In some cases, the optimum phase and pulse width for performing sample and hold are different.

  An object of the present invention is to make it possible to sample and hold a CCD output signal at an appropriate timing according to the CCD driving frequency even if the CCD driving frequency is changed.

An imaging apparatus according to the present invention includes a driving unit that drives an imaging unit that converts an optical image of a subject into an electrical signal, a signal processing unit that performs predetermined processing on an output signal of the imaging unit, and a driving frequency associated with the driving unit. A basic clock output means for outputting a basic clock signal whose frequency can be changed, and a timing signal supplied to the driving means and the signal processing means based on the basic clock signal from the basic clock output means A basic signal output from the basic clock output means, and a timing signal control means for generating and outputting a timing signal information table in which change information related to the timing signal is determined for each frequency of the basic clock signal According to the frequency of the signal, the timing signal control means converts the generated timing signal into the change information. Accordingly and changes output.
The imaging apparatus of the present invention includes an imaging unit that converts an optical image of a subject into an electrical signal, a driving unit that drives the imaging unit, a signal processing unit that processes an output signal of the imaging unit, and the driving unit. A basic clock generating means for generating a basic clock serving as a reference for the driving frequency, and a timing for generating a timing signal to be supplied to the driving means and the signal processing means based on a basic clock signal from the basic clock generating means An image pickup apparatus including a signal generation unit, wherein a clock frequency changing unit that changes a frequency of a basic clock signal generated by the basic clock generation unit and a phase of an output signal of the timing signal generation unit according to a phase condition Timing signal phase changing means for changing the basic clock signal changed by the clock frequency changing means A timing signal phase information table determined by the timing signal phase changing means for each frequency, and when the frequency of the basic clock signal is changed by the clock frequency changing means, refer to the timing signal phase information table; The phase condition is set.
The imaging apparatus of the present invention includes an imaging unit that converts an optical image of a subject into an electrical signal, a driving unit that drives the imaging unit, a signal processing unit that processes an output signal of the imaging unit, and the driving unit. A basic clock generating means for generating a basic clock serving as a reference for the driving frequency, and a timing for generating a timing signal to be supplied to the driving means and the signal processing means based on a basic clock signal from the basic clock generating means An image pickup apparatus comprising: a signal generation unit; a clock frequency changing unit that changes a frequency of a basic clock signal generated by the basic clock generation unit; and a pulse width of an output signal of the timing signal generation unit Timing signal pulse width changing means that changes according to the above, and the basic that is changed by the clock frequency changing means A timing signal pulse width information table defined by the timing signal pulse width changing means for each frequency of the lock signal, and the timing signal pulse width when the frequency of the basic clock signal is changed by the clock frequency changing means The pulse width condition is set with reference to an information table.
In addition, the timing signal control method of the present invention includes an imaging unit that has a driving unit that drives an imaging unit that converts an optical image of a subject into an electrical signal, and a signal processing unit that performs predetermined processing on an output signal of the imaging unit. A timing signal control method in the apparatus, which is generated in a basic clock generation step for generating a basic clock signal that is a reference of a driving frequency for the driving means and whose frequency can be changed, and the basic clock generation step A timing signal control step for generating and outputting a timing signal to be supplied to the driving means and the signal processing means based on a basic clock signal, and for each frequency of the basic clock signal in the timing signal control step. Generated in the basic clock generation step in the timing signal information table that defines the change information related to the timing signal. According to the general clock signal change information corresponding to the frequency of which is characterized in that it changes the generated timing signal output.

  According to the present invention, the timing signal supplied to the driving means and the signal processing means is appropriately changed and output according to the change information corresponding to the driving frequency serving as the reference of the basic clock signal with reference to the timing signal information table. Even if the frequency is changed, the image pickup means can be driven and the image signal that is the output signal of the image pickup means can be sampled and held at an appropriate timing according to the drive frequency, and S / N degradation of the image pickup signal is suppressed. Thus, a high-quality captured image can be generated.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to the first embodiment of the present invention. In the following, a digital camera will be described as an example, but the present invention is not limited to this.

  In FIG. 1, reference numeral 101 denotes an imaging optical system that forms a subject image. Reference numeral 102 denotes an imaging unit that converts an object image formed by the imaging optical system 101 into an electrical signal and outputs the electrical signal. Reference numeral 103 denotes an imaging drive unit that supplies each signal and drives the imaging unit 102. Reference numeral 104 denotes an analog signal processing unit that performs predetermined processing on the output signal of the imaging unit 102, and reference numeral 105 denotes an ADC unit that converts the analog image signal output from the analog signal processing unit 104 into a digital image signal.

  A signal processing unit 106 performs image processing such as white balance adjustment, γ correction, and pixel interpolation on the image signal converted into the digital image signal by the ADC unit 105. Reference numeral 107 denotes a frame memory unit configured by a DRAM or the like for temporarily storing digital image signals, and reference numeral 108 denotes a compression unit that compresses the digital image signals stored in the frame memory unit 107 by a compression technique such as JPEG. . The compression operation in the compression unit 108 is started along with the release operation at the time of shooting. Reference numeral 109 denotes a recording media unit such as a flash memory that stores the digital image signal compressed by the compression unit 108.

  Reference numeral 110 denotes an NTSC / PAL encoder unit that converts a digital image signal stored in the frame memory unit 107 into an NTSC or PAL signal. Reference numeral 111 denotes an image signal converted into an NTSC or PAL signal by the NTSC / PAL encoder unit 110. A display unit (for example, an electronic viewfinder) to display. A system control unit 112 controls each unit of the imaging apparatus (digital camera). Reference numeral 113 denotes a memory unit that stores an information table, which will be described later, and reference numeral 114 denotes an operation unit for the user to perform various operations on the imaging apparatus.

  Reference numeral 115 denotes a basic clock generation unit that generates and outputs a basic clock signal serving as a reference for the CCD drive frequency related to the operations of the imaging drive unit 103, the analog signal processing unit 104, the ADC unit 105, and the like. Reference numeral 116 denotes a clock frequency changing unit that changes the frequency of the basic clock signal output from the basic clock generating unit 115.

  A timing signal 117 is supplied to the imaging drive unit 103, the analog signal processing unit 104, and the ADC unit 105 based on the basic clock signal supplied from the basic clock generation unit 115 at a frequency determined by the clock frequency changing unit 116. It is a timing signal generation part to generate. A timing signal phase changing unit 118 changes the phase of the output signal of the timing signal generating unit 117.

Here, the clock frequency changing unit 116, the timing signal generating unit 117, and the timing signal phase changing unit 118 are controlled by the system control unit 112.
The display unit 111 can simultaneously display the image related to the image signal, the operation items in the operation unit 114, the current operation mode and state of the digital camera, and the display when the CCD drive frequency is changed. It can be carried out.

FIG. 2 is a diagram illustrating a configuration example of the timing signal generation unit 117.
In FIG. 2, reference numeral 201 denotes a frequency divider that divides the basic clock signal input from the outside (the basic clock generator 115 shown in FIG. 1) by half. Hereinafter, the clock signal divided and output by the frequency divider 201 is referred to as a clock signal MCKO.

  Reference numeral 202 denotes a CCD drive signal generator that generates various signals for CCD drive based on the clock signal MCKO, and 203 generates various signals for analog signal processing and ADC control based on the clock signal MCKO. A video signal processing control signal generator. Reference numeral 204 denotes a serial I / F unit for receiving a control signal from the system control unit 112. That is, the timing signal generation unit 117 is controlled by the system control unit 112.

  The CCD drive signal generation unit 202 generates each signal determined for each operation mode of the digital camera with a phase based on the rising edge of the divided clock signal MCKO, and supplies the signal to the imaging drive unit 103. The signal generated by the CCD drive signal generator 202 includes a horizontal transfer pulse, a reset gate pulse, a vertical transfer pulse, and an electronic shutter pulse.

  Here, the phase of the horizontal drive pulse and the reset gate pulse is determined based on a command from the system control unit 112 by an analog delay element, a digital delay processing circuit, or the like provided in the timing signal phase change unit 118. The information is appropriately changed and supplied to the imaging drive unit 103. In other words, the horizontal drive pulse and the reset gate pulse generated by the CCD drive signal generation unit 202 are supplied to the imaging drive unit 103 after the timing signal phase change unit 118 sets a predetermined phase condition from the rising reference of the clock signal MCKO. Is done.

  The video signal processing control signal generation unit 203 generates each signal determined for each operation mode of the digital camera based on the clock signal MCKO, and supplies the signal to the analog signal processing unit 104 and the ADC unit 105. Signals generated by the video signal processing control signal generation unit 203 include pulse signals SHP and SHD for performing sample and hold, a timing pulse signal ADCLK related to the ADC unit 105, and signals PBCLK and CLPOB.

  Here, the phase of the pulse signals SHP and SHD and the timing pulse signal ADCLK is appropriately changed based on a command from the system control unit 112 by an analog delay element or a digital delay processing circuit in the timing signal phase changing unit 118. The analog signal processing unit 104 and the ADC unit 105 are supplied. In other words, the pulse signals SHP and SHD and the timing pulse signal ADCLK generated by the video signal processing control signal generating unit 203 are analogized after the timing signal phase changing unit 118 makes a predetermined phase condition from the rising reference of the clock signal MCKO. The signal is supplied to the signal processing unit 104 and the ADC unit 105.

These phase conditions are stored in advance in the memory unit 113 as a timing signal phase information table as shown in FIG. 4 as an example, and are set with reference to this timing signal phase information table.
FIG. 4 is a diagram illustrating an example of the timing signal phase information table.
As shown in FIG. 4, in the timing signal phase information table, the phase conditions of the horizontal drive pulse, the reset gate pulse, the pulse signals SHP, SHD, and the timing pulse signal ADCLK are defined for each CCD drive frequency.

  Here, the reason why the phase of the timing signal such as the horizontal drive pulse, the reset gate pulse, the pulse signals SHP and SHD, and the timing pulse signal ADCLK is changed for each CCD drive frequency will be described.

FIG. 3 is a diagram showing a waveform example of an output signal output from the image pickup unit 102, in which the CCD drive frequency is doubled with respect to the waveform of the output signal shown in FIG.
As shown in FIG. 3, one pixel period of the CCD output signal CCDOUT is proportional to the CCD drive frequency, while the rise and fall times of the optical output signal indicate the transfer efficiency of the transfer stage in the CCD of the image pickup unit 102. It depends on the slew rate characteristics of the output stage buffer amplifier.

  Therefore, when increasing the CCD drive frequency, for example, the timing margin in the analog signal processing unit 104 is increased by advancing the phase of the reset gate pulse among the CCD drive pulse signals to widen the video signal period TP. There is a case that can be made. As described above, the waveform of the CCD output signal CCDOUT changes, and the optimum phase for performing the sample hold may be different so as to maximize the S / N of the imaging signal.

  Therefore, in the first embodiment, for example, the timing signal phase information table shown in FIG. 4 is provided, and even if the CCD driving frequency is switched, the phase condition is referred to the timing signal phase information table for each CCD driving frequency. And the timing signal phase changing unit 118 appropriately changes the phase of the timing signal generated by the timing signal generating unit 117.

  As a result, even when the CCD drive frequency is set higher than that during single-shot still image shooting for high-speed continuous shooting, EVF display, moving image shooting, etc., in the imaging device, the optimum phase corresponding to the CCD driving frequency is obtained. Based on the timing signal, the CCD drive and the sample hold of the CCD output signal can be performed.

  In addition, in the imaging device, the CCD drive frequency was lowered compared with single image shooting in order to increase the total number of images that can be taken even if the remaining battery level decreases and the number of images that can be taken per unit time decreases. In this case, the CCD drive frequency is halved as compared with single image shooting, but the CCD is driven horizontally even if EVF display is performed without reducing the substantial frame rate. Based on the timing signal having the optimum phase according to the frequency, the CCD drive and the sample hold of the CCD output signal can be performed.

  Therefore, even when the CCD driving frequency is changed, the CCD driving and the sample output holding of the CCD output signal can be performed at an appropriate timing according to the CCD driving frequency. A quality captured image can be generated.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 5 is a block diagram showing a configuration example of an imaging apparatus according to the second embodiment of the present invention. In the following, a digital camera will be described as an example as in the first embodiment, but the present invention is not limited to this. In FIG. 5, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  In FIG. 5, reference numeral 518 denotes a timing signal pulse width changing unit that changes the pulse width of the output signal of the timing signal generating unit 117.

  The configuration of the timing signal generator 117 in FIG. 5 is the same as that of the timing signal generator 117 in the first embodiment shown in FIG. 2, but the CCD drive signal generator 202 is determined for each operation mode of the digital camera. Each signal having the obtained pulse width is generated and supplied to the imaging drive unit 103.

  Here, the horizontal drive pulse and the reset gate pulse generated by the CCD drive signal generation unit 202 are processed by the system control unit by an analog delay element, a digital delay processing circuit, or the like provided in the timing signal pulse width change unit 518. Based on the command from 112, the pulse width is appropriately changed and supplied to the imaging drive unit 103. In other words, the horizontal drive pulse and the reset gate pulse are supplied to the imaging drive unit 103 after the timing signal pulse width changing unit 518 makes a predetermined pulse width condition.

  Also, the video signal processing control signal generation unit 203 generates each signal having a pulse width determined for each operation mode of the digital camera, and supplies the signal to the analog signal processing unit 104 and the ADC unit 105.

  Here, the pulse signals SHP and SHD and the timing pulse signal ADCLK generated by the video signal processing control signal generation unit 203 are controlled by an analog delay element or a digital delay processing circuit in the timing signal pulse width changing unit 518. Based on a command from the unit 112, the pulse width is appropriately changed and supplied to the analog signal processing unit 104 and the ADC unit 105. In other words, the pulse signals SHP and SHD and the timing pulse signal ADCLK are supplied to the analog signal processing unit 104 and the ADC unit 105 after the timing signal pulse width changing unit 518 makes a predetermined pulse width condition.

These phase conditions are stored in advance in the memory unit 113 as a timing signal pulse width information table as shown in FIG. 7 as an example, and are set with reference to this timing signal pulse width information table.
FIG. 7 is a diagram illustrating an example of a timing signal pulse width information table.
As shown in FIG. 7, the timing signal pulse width information table defines the pulse width conditions of the horizontal drive pulse, reset gate pulse, pulse signals SHP, SHD, and timing pulse signal ADCLK for each CCD drive frequency. Yes.

  Here, the reason why the pulse widths of the timing signals such as the horizontal drive pulse, the reset gate pulse, the pulse signals SHP and SHD, and the timing pulse signal ADCLK are changed for each CCD drive frequency will be described.

FIG. 6 is a diagram illustrating a waveform example of an output signal output from the imaging unit 102, in which the phase of the reset gate pulse is advanced with respect to that illustrated in FIG.
As can be seen from FIG. 6, the time width of the feedthrough portion and the video signal portion are almost equal because the phase of the reset gate pulse is advanced, and the timing margin in the analog signal processing unit 104 can be increased. Recognize. However, as can be seen from the comparison with that shown in FIG. 10, when the CCD drive frequency is increased, the time width of the feedthrough portion and the video signal portion is shortened, and the timing condition in the analog signal processing unit 105 becomes severe. End up.

  Therefore, when the CCD drive frequency is increased, for example, it may be effective to reduce the pulse width of the reset gate and increase the time width of the feed-through portion or the video signal portion of each CCD drive pulse signal. . When the CCD drive frequency is increased, the waveform of the CCD output signal OUT changes, and the optimum pulse width for performing sample hold may be different so as to maximize the S / N of the imaging signal.

  Therefore, in the second embodiment, for example, the timing signal pulse width information table shown in FIG. 7 is provided. Even if the CCD driving frequency is switched, the timing signal pulse width information table is referred to for each CCD driving frequency. A pulse width condition is set, and the timing signal pulse width changing unit 518 changes the pulse width of the timing signal generated by the timing signal generating unit 117 as appropriate.

  As a result, even when the CCD driving frequency is set higher than that during single-shot shooting for performing high-speed continuous shooting, EVF display, moving image shooting, and the like in the imaging device, an optimum pulse corresponding to the CCD driving frequency is obtained. Based on the timing signal having the width, it is possible to perform CCD driving and sample hold of the CCD output signal.

  In addition, in the imaging device, the CCD drive frequency was lowered compared with single image shooting in order to increase the total number of images that can be taken even if the remaining battery level decreases and the number of images that can be taken per unit time decreases. In this case, the CCD drive frequency is halved as compared with single image shooting, but the CCD is driven horizontally even if EVF display is performed without reducing the substantial frame rate. Based on the timing signal having an optimum pulse width corresponding to the frequency, CCD drive and sample hold of the CCD output signal can be performed.

  Therefore, even when the CCD driving frequency is changed, the CCD driving and the sample output holding of the CCD output signal can be performed at an appropriate timing according to the CCD driving frequency. A quality captured image can be generated.

  In the first embodiment described above, the phase of the timing signal generated by the timing signal generation unit 117 is changed by the timing signal phase change unit 118, and in the second embodiment, the timing signal generation unit 117 generates the timing signal. Although the timing signal pulse width changing unit 518 changes the timing signal pulse width, both the phase and pulse width of the timing signal generated by the timing signal generating unit 117 may be changed.

(Other embodiments of the present invention)
In order to operate various devices to realize the functions of the above-described embodiments, program codes of software for realizing the functions of the above-described embodiments are provided to an apparatus or a computer in the system connected to the various devices. What is implemented by operating the various devices according to a program supplied and stored in a computer (CPU or MPU) of the system or apparatus is also included in the scope of the present invention.

  In this case, the program code of the software itself realizes the functions of the above-described embodiments, and the program code itself constitutes the present invention. Further, means for supplying the program code to the computer, for example, a recording medium storing the program code constitutes the present invention. As a recording medium for storing the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  Further, by executing the program code supplied by the computer, not only the functions of the above-described embodiments are realized, but also the OS (operating system) or other application software in which the program code is running on the computer, etc. It goes without saying that the program code is also included in the embodiment of the present invention even when the functions of the above-described embodiment are realized in cooperation with the embodiment.

  Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the CPU provided in the function expansion board or function expansion unit based on the instruction of the program code Needless to say, the present invention also includes a case where the functions of the above-described embodiment are realized by performing part or all of the actual processing.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 is a block diagram illustrating a configuration example of an imaging apparatus according to a first embodiment of the present invention. It is a figure which shows the structural example of a timing signal generation part. It is a figure for demonstrating operation | movement of the imaging device in 1st Embodiment. It is a figure which shows an example of a timing signal phase information table. It is a block diagram which shows the structural example of the imaging device by the 2nd Embodiment of this invention. It is a figure for demonstrating operation | movement of the imaging device in 2nd Embodiment. It is a figure which shows an example of a timing signal pulse width information table. It is a block diagram which shows the structure of the image input part in the conventional imaging device. It is a block diagram which shows the basic composition of a CDS circuit. It is a figure for demonstrating operation | movement of a CDS circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 102 Image pick-up part 103 Image pick-up drive part 104 Analog signal processing part 105 ADC part 112 System control part 113 Memory part 115 Basic clock generation part 116 Clock frequency change part 117 Timing signal generation part 118 Timing signal phase change part 518 Timing signal pulse width change part

Claims (11)

Driving means for driving imaging means for converting an optical image of a subject into an electrical signal;
Signal processing means for performing predetermined processing on the output signal of the imaging means;
A basic clock output means for outputting a basic clock signal capable of changing the frequency as well as a reference for the driving frequency of the driving means;
A timing signal control means for generating and outputting a timing signal to be supplied to the driving means and the signal processing means based on a basic clock signal from the basic clock output means;
A timing signal information table in which change information related to the timing signal is defined for each frequency of the basic clock signal;
The imaging apparatus according to claim 1, wherein the timing signal control means changes and outputs the generated timing signal according to the change information in accordance with the frequency of the basic clock signal output from the basic clock output means.   The imaging apparatus according to claim 1, wherein the timing signal control unit changes at least one of a phase and a pulse width of the generated timing signal according to the change information. The timing signal control means generates a timing signal based on a basic clock signal from the basic clock output means;
The imaging apparatus according to claim 1, further comprising a timing signal changing unit that changes the timing signal generated by the timing signal generating unit according to the change information. The basic clock output means generates basic clock signal and outputs basic clock signal; and
The imaging apparatus according to claim 1, further comprising: a clock frequency changing unit that changes a frequency of the basic clock signal generated by the basic clock signal generating unit.   5. The timing signal change information according to the frequency is set by referring to the timing signal information table when the frequency of the basic clock signal is changed by the clock frequency changing means. Imaging device. Imaging means for converting an optical image of a subject into an electrical signal, driving means for driving the imaging means, signal processing means for processing an output signal of the imaging means, and a basic reference for driving frequency related to the driving means An imaging apparatus comprising basic clock generating means for generating a clock and timing signal generating means for generating a timing signal to be supplied to the driving means and the signal processing means based on a basic clock signal from the basic clock generating means Because
Clock frequency changing means for changing the frequency of the basic clock signal generated by the basic clock generating means;
Timing signal phase changing means for changing the phase of the output signal of the timing signal generating means according to a phase condition;
A timing signal phase information table defined by the timing signal phase changing means for each frequency of the basic clock signal changed by the clock frequency changing means;
An imaging apparatus, wherein the phase condition is set by referring to the timing signal phase information table when the frequency of the basic clock signal is changed by the clock frequency changing means. Imaging means for converting an optical image of a subject into an electrical signal, driving means for driving the imaging means, signal processing means for processing an output signal of the imaging means, and a basic reference for driving frequency related to the driving means An imaging apparatus comprising basic clock generating means for generating a clock and timing signal generating means for generating a timing signal to be supplied to the driving means and the signal processing means based on a basic clock signal from the basic clock generating means Because
Clock frequency changing means for changing the frequency of the basic clock signal generated by the basic clock generating means;
Timing signal pulse width changing means for changing the pulse width of the output signal of the timing signal generating means according to a pulse width condition;
A timing signal pulse width information table defined by the timing signal pulse width changing means for each frequency of the basic clock signal changed by the clock frequency changing means;
An imaging apparatus, wherein when the frequency of a basic clock signal is changed by the clock frequency changing means, the pulse width condition is set with reference to the timing signal pulse width information table.   The timing signal includes a horizontal drive pulse for driving the imaging means, a reset gate pulse, a first sample hold pulse for sampling and holding the output signal of the imaging means in a feedthrough period, and a sample hold in an optical output period. 8. The method according to claim 1, further comprising: at least one of a second sample hold pulse to be performed and an analog / digital conversion timing pulse for converting an output signal of the imaging unit into a digital signal. The imaging device according to item.   The frequency change of the basic clock signal is still image single shooting, still image continuous shooting, moving image shooting, electronic viewfinder display, which is the operation mode of the device, and the remaining battery level which is the operation state of the device, The imaging apparatus according to claim 1, wherein the imaging apparatus is performed based on at least one piece of information.   The imaging apparatus according to claim 1, wherein when the frequency of the basic clock signal is changed, frequency change display is performed. A timing signal control method in an imaging apparatus, comprising: a driving unit that drives an imaging unit that converts an optical image of a subject into an electrical signal; and a signal processing unit that performs predetermined processing on an output signal of the imaging unit.
A basic clock generating step for generating a basic clock signal that is a reference of a driving frequency related to the driving means and whose frequency can be changed;
A timing signal control step of generating and outputting a timing signal to be supplied to the driving means and the signal processing means based on the basic clock signal generated in the basic clock generation step;
In the timing signal control step, a change corresponding to the frequency of the basic clock signal generated in the basic clock generation step in the timing signal information table in which change information related to the timing signal is determined for each frequency of the basic clock signal A timing signal control method, comprising: changing and outputting a generated timing signal according to information.

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