JP2000165759A - Endoscope image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an endoscope image pickup device for correcting cable length in a small-scaled circuit constitution. SOLUTION: Horizontal transfer pulses ϕH1 and ϕH2 and a reset pulse ϕR whose frequencies are high among the driving signals of a CCD 2 are generated by a driving signal generating circuit 11 operating with a clock signal CLK, and the other driving signals whose frequencies are low are generated by a DSP 13 operating with a clock signal MCK, and applied to the CCD 2. An image pickup signal CCDout obtained by the CCD 2 is converted into a video signal by a CDS circuit 12 and a DSP 13 operating with a clock signal MCK. A clock signal CLK is obtained by a phase comparator 18 and a VCO 19 so that the phase of reset pulse components extracted from the image pickup signal matches with the phase of the clocks signal MCK by a reset pulse extracting and shaping circuit 16, and signal delay through a cable 5 is corrected. Also, a driving signal generating circuit 11 is constituted of a simple logic circuit in which all the driving signals are not generated, and the circuit scale can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an endoscope imaging apparatus having means for correcting a cable delay between an imaging means such as a CCD and an imaging control means for obtaining a video signal from an imaging signal obtained by the imaging means. Related to the device.

[0002]

2. Description of the Related Art In recent years, portable video cameras for consumer use equipped with a small and high-performance DSP (digital signal processor) for processing video signals have become widespread. Such a video camera generally has an imaging device integrally formed in a housing, which includes an imaging element such as a CCD and an imaging control circuit that processes an imaging signal obtained by driving the CCD and obtains a video signal. Then, for example, the configuration is as shown in FIG. That is, the imaging device 101 shown in FIG.
And an imaging control circuit 103 integrated in a housing, and the imaging control circuit 103 generates a driving signal for driving the CCD 102 and the like.
The timing generator is abbreviated as TG).
An oscillator 112 for supplying a clock signal CLK to the clock signal 11;
A CDS circuit 113 for extracting a video signal component from an image signal obtained by the CCD 102 (correlated double sampling processing is abbreviated as CDS in the present application);
And a DSP 114 (in the present application, a digital signal processor is abbreviated as DSP) for performing various video signal processing on the video signal obtained in step 3 and outputting a video signal that can be rendered on a display device such as a TV monitor (not shown). It is configured.
Here, the DSP 114 is formed of one semiconductor element in which a processing circuit for performing various video signal processing is highly integrated, and forms the imaging device 101 together with the TG 111 and various peripheral ICs forming the CDS circuit 113. ing. Thus, the CCD 102 and the imaging control circuit 103
Is stored in the same case, the TG111 and the CCD
102 and the CCD 102 and the CDS circuit 113 are arranged close to each other, so that there is usually no problem in many cases even if the configuration is performed without considering the delay of the drive signal and the imaging signal. Further, even when a minute delay occurs, the TG
111 and the CDS circuit 113 and DSP1
A fixed phase difference may be fixedly expected in advance between the operation timings of FIG.

[0003] In recent years, endoscopes that allow an elongated insertion portion to be inserted into a body cavity, a pipe, or the like to observe a subject in the body cavity, a pipe, or the like have been widely used. In such an endoscope, for example, a subject image is transmitted from the distal end of the insertion section to an operation section provided continuously on the base end side of the insertion section, and via an eyepiece provided continuously on the operation section, It is configured so that a subject image can be visually observed. In such an endoscope, not only a subject image is observed visually, but also a camera head is attached to an eyepiece, and a C provided in the camera head is provided.
An imaging signal from an imaging element such as a CD
The image data is transmitted to an imaging controller generally called a CU (camera control unit), and the CCU converts the imaging signal into a video signal that can be displayed on a monitor, so that a subject image can be displayed on a TV monitor or the like. In other words, the endoscope imaging device, which is an imaging device for an endoscope, has a configuration in which the CCD and the CCU are arranged apart from each other and are connected by a cable. Therefore, when trying to use the imaging apparatus as shown in FIG. 11 as an endoscope imaging apparatus, a delay occurs in the drive signal and the imaging signal transmitted through the cable, and the imaging signal is delayed with respect to the operation timing of the CDS circuit 113 and the DSP 114. May be delayed.

Therefore, conventionally, an endoscope imaging apparatus may be provided with a means for performing cable length correction for correcting signal delay caused by cable length. FIG.
1 shows a configuration example of a conventional endoscope imaging apparatus 121 provided with a cable length correction unit. In the endoscope imaging apparatus 121, the TG 131 generates a drive signal according to the clock signal CLK, the CCD 122 outputs an image signal according to the drive signal, and the CDS circuit 133 extracts a video signal from the image signal according to the sampling signal from the TG 135. And
DSP1 according to clock signal MCK from TG 135
34 performs video signal processing on the video signal from the CDS circuit 133, and the video signal output from the DSP 134 is output to a TV monitor or the like. Here, the clock signal MCK is generated by the TG 13 according to the clock signal CLK0 generated by the oscillator 136 and having a fixed frequency and phase.
5 and a sampling signal is also generated according to the clock signal CLK0. On the other hand, the reset pulse extraction and shaping circuit 138 extracts a reset pulse component from the imaging signal and outputs a clock signal RCK whose waveform is shaped. The phase of the clock signal RCK is compared with that of the clock signal MCK by the phase comparator 139.
Is an output of V, the oscillation frequency of which is controlled by the input voltage.
CO140 (voltage controlled oscillator)
140 supplies the clock signal CLK to the TG 131. That is, a PLL as a cable length correction unit that generates the clock signal CLK so that the phases of the clock signal RCK and the clock signal MCK extracted from the imaging signal match.
A (phase locked loop) circuit includes a reset pulse extraction and shaping circuit 138, a phase comparator 139, a VCO 140, and the like. Thereby, the timing of the imaging signal matches the operation timing of the CDS circuit 133 and the DSP 134. Generally, T
The G131, 135 and DSP 134 are composed of large-scale semiconductor elements. That is, the CCU of the example shown in FIG.
Reference numeral 124 denotes a large-scale semiconductor device such as a DSP or a TG.
It has a configuration. In addition, when generating a drive signal, a horizontal synchronization signal HD, a vertical synchronization signal VD, a field identification signal, and the like are required in addition to the clock signal CLK. Therefore, the CCU 124 is provided with a phase control circuit 137 for obtaining signals THD and TVD in which the phases of these signals are advanced by the amount of the delay caused by the cable. The phase control circuit 137 outputs clock signals MCK and CCK having different phases.
Since the phase is converted with the LK, complicated timing control is performed.

[0005] An endoscope image pickup device 121 shown in FIG.
Of the CCU 124 having the configuration shown in FIG.
You may change to CU124a. In FIG. 13, the same components as those in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted. Only different points will be mainly described. In the example of FIG. 13, TG13 shown in FIG.
In place of 1, DSP14 has a role similar to that of TG131.
2 are provided. Further, a DSP 141 having the functions of the TG 135 and the DSP 134 shown in FIG. 12 is provided. Further, instead of the oscillator 136 that oscillates the clock signal CLK0 shown in FIG. 12, an oscillator 136a that oscillates the clock signal MCK supplied to the DSP 141 is provided. The configuration of the PLL circuit is similar to that of FIG. The CCU 124a having such a configuration can also perform the same function as the CCU 124 shown in FIG. As described above, the CCU 124a in the example shown in FIG. 13 includes two DSPs 141 and 142 which are large-scale semiconductor elements.

[0006]

As described in the background art, the conventional endoscope imaging apparatus as shown in FIGS. 12 and 13 has two different timings in order to provide a cable length correcting means. TGs and DSPs operating with clock signals MCK and CLK are provided, that is, at least two large-scale semiconductor elements are generally provided. Also,
A complicated circuit for timing control such as a phase control circuit for advancing the phase of the horizontal / vertical synchronization signal was included.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an endoscope imaging apparatus capable of performing cable length correction with a small and simple circuit configuration.

[0008]

In order to achieve the above object, an endoscope imaging apparatus according to the present invention comprises: a solid-state imaging device for imaging a subject and outputting an imaging signal; and a signal component extracted from the imaging signal. Means for shaping the waveform to obtain a first clock signal, first delay means for delaying the first clock signal, signal processing means for processing the imaging signal, and second signal processing means for providing the signal processing means. Means for oscillating a clock signal, second delay means for delaying the second clock signal, and comparing phases of an output signal from the first delay means and an output signal from the second delay means. And a third comparator controlled by an output from the phase comparator.
An oscillator that oscillates the clock signal, a means for generating a horizontal synchronization signal used by the signal processing means in synchronization with the second clock signal, a third delay means for delaying the horizontal synchronization signal, A drive for generating a horizontal transfer pulse and a reset pulse for driving the image sensor from the output signal from the third delay unit and the third clock signal, or a pulse serving as a reference signal for the horizontal transfer pulse and the reset pulse. An endoscope imaging apparatus comprising a signal generation unit, wherein the drive signal generation unit includes the third signal generation unit.
And a circuit for generating a horizontal transfer pulse and a reset pulse from the output signal from the delay means and the third clock signal, or a pulse serving as a reference signal for the horizontal transfer pulse and the reset pulse. And

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 9 relate to a first embodiment of the present invention, FIG. 1 is a block diagram showing an overall configuration of an endoscope imaging apparatus, FIG. 2 is a block diagram showing a configuration of a drive signal generation circuit, and FIG. Is a block diagram showing a configuration of a frequency dividing circuit,
4 is a block diagram showing a configuration of a latch circuit, FIG. 5 is a block diagram showing a configuration of a differentiating circuit, FIG. 6 is a block diagram showing a configuration of a counter circuit and a transfer period determining circuit, and FIG. FIG. 8 is a block diagram showing the configuration of the delay circuit, FIG. 8 is a block diagram showing the configuration of the delay circuit, and FIG.
FIG. 4 is a waveform diagram illustrating an operation of the drive signal generation circuit.

As shown in FIG. 1, an endoscope imaging apparatus 1 according to the present embodiment includes a camera head 3 having imaging means such as a CCD 2 and detachably connected to an eyepiece of an endoscope (not shown).
A driving signal is supplied to the CCD 2 to convert the image signal obtained by the CCD 2 into a video signal that can be output to a display device such as a TV monitor (not shown).
U4 and a cable 5 for connecting the camera head 3 and the CCU 4. That is, the camera head 3 and the CCU 4 are separated from each other by the cable 5.

The CCU 4 includes a drive signal generating circuit 11 for generating high-frequency horizontal transfer pulses φH 1 and φH 2 and a reset pulse φR among the drive signals supplied to the CCD 2.
A CDS circuit 12 for performing a correlated double sampling process on the image pickup signal CCDout obtained by the CCD to extract a video signal component, and a video monitor (not shown) for performing various video signal processes on the video signal obtained by the CDS circuit 12; , An oscillator 14 for oscillating a clock signal MCK having a fixed frequency and phase applied to the DSP 13, and extracting a reset pulse component from the imaging signal CCDout, shaping the waveform, and shaping the clock signal RCK.
And a reset pulse extracting and shaping circuit 16 for obtaining the clock signal DRCK by delaying the phase of the clock signal RCK.
Circuit 17a for obtaining the clock signal DMCK by delaying the phase of the clock signal MCK
b and a clock signal DR
A phase comparator 18 for comparing the phases of CK and the clock signal DMCK, and a VCO 19 for oscillating the clock signal CLK so as to control the oscillation frequency in accordance with the output from the phase comparator 18 and applying the clock signal CLK to the drive signal generation circuit 11. And a delay circuit 15 for delaying the phase of the horizontal synchronization signal HD output from the DSP 13 and providing the horizontal synchronization signal DHD to the drive signal generation circuit 11.

As shown in FIG. 2, the driving signal generating circuit 11 includes a frequency dividing circuit 21 for dividing the frequency of the clock signal CLK by を 得 to obtain a clock signal CLKB.
The horizontal synchronization signal DHD and the clock signal CLKB to CC
A transfer period signal generation circuit 22 for generating a transfer period signal HMASK indicating a horizontal transfer period of D2;
A horizontal transfer pulse generating circuit 23 for obtaining horizontal transfer pulses φH1 and φH2 for driving the CCD 2 from the KB and the transfer period signal HMASK;
A reset pulse generating circuit 24 for generating a reset pulse φR for driving the driving circuit 2, an FF (flip-flop) provided at an output stage of each circuit, and a drive signal generating circuit 11
And a driver 36 that amplifies each drive signal output from the controller 36.

The transfer period signal generating circuit 22 includes a latch circuit 31 for latching the horizontal synchronizing signal DHD, a differentiating circuit 32 for differentiating an output signal from the latch circuit 31,
The output signal from the differentiating circuit 32 and the clock signal CL
A counter circuit 33 that counts the clock signal CLK in accordance with KB, a transfer period start / end timing is determined based on the count value of the counter circuit 33, and a transfer period signal HMA is determined.
It has a transfer period determination circuit 34 for outputting SK.

The horizontal transfer pulse generating circuit 23 calculates a logical product of the clock signal CLKB and the transfer period signal HMASK to obtain a horizontal transfer pulse φH1, and logically inverts the horizontal transfer pulse φH1. And a logic gate circuit for obtaining the horizontal transfer pulse φH2. Thereby, the transfer period signal HMAS
During the horizontal transfer period in which K is valid, a horizontal transfer pulse φH1 having the same waveform as the clock signal CLKB and a horizontal transfer pulse H2 obtained by inverting the horizontal transfer pulse φH1 are output.

The reset pulse generation circuit 24 includes a logic gate circuit for inverting the logic of the clock signal CLKB, a delay element 35 for delaying the phase of the output signal of the logic gate circuit, an output signal of the delay element 35 and the clock signal. And a logic gate circuit that takes a logical product with CLKB. As a result, the rising timing of the clock signal CLKB is the same as that of the clock signal CLKB, and
A reset pulse φR having a pulse width smaller than B is generated.

As shown in FIG. 3, the frequency dividing circuit 21
For example, it is composed of one flip-flop and one logic gate circuit. Thus, a clock signal CLKB obtained by dividing the frequency of the input clock signal CLK by １ ／ is generated.

As shown in FIG.
Is composed of, for example, one latch. Thereby, the clock signal CLKB is valid and the clock signal C
While LK is valid, the input horizontal synchronization signal DHD becomes through, and the horizontal synchronization signal DHD is latched at the timing when the period in which the clock signal CLKB falls and becomes through ends. .

As shown in FIG. 5, the differentiating circuit 32 comprises:
For example, it is composed of two flip-flops and one logic gate circuit. Thus, the output signal from the latch circuit 31 is differentiated.

As shown in FIG.
Is composed of, for example, one 8-bit counter. Thereby, the clock signal CLK is counted while the clock signal CLKB is valid, and the differentiating circuit 32
When the output signal from is valid, the count value is cleared.

The transfer period determination circuit 34 includes, for example, two 8-bit comparison circuits 34 a and 34 b for comparing the count value of the counter circuit 33, and these two comparison circuits 3.
It comprises one RS flip-flop 34c which operates in synchronization with the clock signal CLK according to the outputs of 4a and 34b. Thus, the RS flip-flop 34c is set when the comparison circuit 34a determines the start timing of the transfer period, and the RS flip-flop 3c is set when the comparison circuit 34b determines the end timing of the transfer period.
4c is reset, and the RS flip-flop 34c
Is output as the transfer period signal HMASK.

As shown in FIGS. 2 to 6, the drive signal generation circuit 11 generates high-frequency horizontal transfer pulses φH1 and φH2 and a reset pulse φR among drive signals for driving the CCD 2, and generates low-frequency drive pulses. It does not generate other drive signals such as the vertical transfer pulses φV1 to φV4 and the shutter pulse SHT for driving the electronic shutter of the CCD 2. Further, the drive signal generation circuit 11 is configured by a simple circuit including a flip-flop, a latch, a logic gate circuit, a driver, a counter, a comparator, and the like, and is configured on a small scale.

As shown in FIG. 7, the reset pulse extracting and shaping circuit 16 includes, for example, a reset pulse extracting circuit 16a comprising a selector and a band-pass filter, and a limiter for shaping the output signal of the reset pulse extracting circuit 16a. Waveform shaping circuit 16b composed of amplifier
It is composed of The reset pulse extraction circuit 1
6a extracts, for example, a frequency component of a reset pulse in an optical black period from the imaging signal CCDout, and outputs a signal of the reset pulse component to the waveform shaping circuit 1;
The signal is shaped into a square wave having a duty ratio of about 50% by 6b and output as a clock signal RCK.

The delay circuit 17 comprises a first delay circuit 17
a and a second delay circuit 17b. Each of the delay circuits 17a and 17b includes, for example, two inverters 42, which are logic gate circuits, and a delay element 41 interposed between the two inverters 42, respectively. Each delay element 41 is composed of, for example, one variable resistor and one capacitor. As a result, the delay times of the clock signal RCK and the clock signal MCK are set independently of each other, and the delayed clock signal DRCK and the delayed clock signal DMCK are respectively output.

As shown in FIG. 8, the third delay circuit 15
Is, for example, the first delay circuit 17a or the second delay circuit 1
7b. Thereby, the delay time of the horizontal synchronization signal HD is set, and the delayed horizontal synchronization signal DHD is output.

Next, the operation of the present embodiment will be described. The drive signal generation circuit 11 synchronizes the horizontal transfer pulses φH1, φH2, reset pulse φR
The DSP 13 generates vertical transfer pulses φV1 to φV4 and a shutter pulse SHT in synchronization with the clock signal MCK. These drive signals are supplied to the CCD 2 via the cable 5, and the CCD 2 operates according to the supplied drive signals, and captures an image of a subject such as a body cavity illuminated by illumination light from a light source device (not shown). An image pickup signal CCDout corresponding to the subject image is output. This imaging signal CCDout is transmitted via the cable 5 to the CCU 4
To the CDS circuit 12. At this time,
The imaging signal CCDout input to the CDS circuit 12 is
The phase of the drive signal generated by the drive signal generation circuit 11 is delayed due to the signal delay in the round trip of the cable 5. C
The DS circuit 12 performs a correlated double sampling process and a gain adjustment process on the imaging signal CCDout to extract a video signal component. At this time, the CDS circuit 12 outputs the clock signal M
It operates under the control of sampling signals SHP and SHD generated by the DSP 13 in synchronization with CK. This C
The video signal extracted by the DS circuit 12 is subjected to various video signal processing by the DSP 13 and output. This DSP13
Is output to a TV monitor or the like,
The TV monitor draws a subject image picked up by the CCD 2. In the DSP 13, for example, A / D conversion processing, luminance / color signal separation processing, white balance processing, enhancement processing, dimming detection processing, gamma & knee processing, D / D
Video signal processing such as A conversion processing is performed.

Also, the CCD 2 is connected to the C
The imaging signal CCDout transmitted to the CU 4 is input to the reset pulse extraction and shaping circuit 16. The reset pulse extraction and shaping circuit 16 extracts a reset pulse component from the imaging signal CCDout and outputs a clock signal RCK obtained by shaping the reset pulse component into a square wave. This clock signal RCK
Is input to the delay circuit 17a.
Is a clock signal DR obtained by delaying the clock signal RCK.
CK is given to the phase comparator 18. The clock signal DMCK obtained by delaying the clock signal MCK from the oscillator 14 by the delay circuit 17b is input to the phase comparator 18. The phase comparator 18 outputs the clock signal D
The phase of RCK and the clock signal DMCK are compared, and for example, the signal PH whose voltage level is changed in accordance with the phase difference.
Apply ASE to VCO 19. And the VCO 19
A clock signal CLK whose oscillation frequency is controlled according to, for example, a voltage level of the signal PHASE is supplied to the drive signal generation circuit 11. At this time, the phase comparator 18 and the VC
The clock signal CLK is output from the VCO 19 by the PLL circuit composed of O19 and the like such that the phases of the clock signal DRCK and the clock signal DMCK match. Further, by adjusting the delay times of the delay circuits 17a and 17b, the phases of the sampling signals SHD and SHP provided from the DSP 13 to the CDS circuit 12 and the imaging signal C are adjusted.
The phase of CDout can be adjusted so as to have an optimum relationship regardless of the cable length of the cable 5, and the correlated double sampling processing by the CDS circuit 12 is optimally executed.

The frequency of the clock signal CLK output from the VCO 19 is substantially twice the frequency of the reset pulse φR, and the drive signal generation circuit 11 At 1/2
The horizontal transfer pulses φH 1 and φH 2 and the reset pulse φR are generated in accordance with the clock signal CLKB divided into two. With such a PLL circuit, the phase of the imaging signal CCDout supplied to the CDS circuit 12 matches the phase of the clock signal MCK which is the operation reference of the DSP 13 and the CDS circuit. That is, the endoscope imaging apparatus 1 is connected to the cable 5
Cable length correction means for correcting the signal delay caused by the As described above, the clock signal CLK input from the VCO 19 to the drive signal generation circuit 11 is frequency-divided by で in the frequency divider circuit 21. The frequency-divided clock signal CLKB is It is provided to each unit of the generation circuit 11. At this time, by using the clock signal CLKB divided by the frequency dividing circuit 21, the duty ratio of the horizontal transfer pulses φH1 and φH2 generated by the drive signal generating circuit 11 is secured to approximately 50%.

The transfer period signal generation circuit 22 of the drive signal generation circuit 11 generates a transfer period signal HMASK from the clock signals CLK and CLKB and the horizontal synchronization signal DHD. Then, the horizontal transfer pulse generation circuit 23 converts the clock signal CLKB and the transfer period signal HMASK into
Horizontal transfer pulses φH1 and φH2 are generated. Also, the reset pulse generation circuit 24 generates the clock signal CLKB
Generates a reset pulse φR.

FIG. 9 shows the relationship between the main signals in the drive signal generation circuit 11. As shown in the figure, the clock signal CLKB reduces the frequency of the clock signal CLK by 1 /.
The frequency is divided by two. The horizontal transfer pulse φH1
Has a waveform similar to that of the clock signal CLKB when the transfer period signal HMASK is valid. The horizontal transfer pulse φH2 has a waveform obtained by inverting the horizontal transfer pulse φH1. Also, the reset pulse φR
Has a waveform in which the pulse width of the clock signal CLKB is narrowed. Thus, the horizontal transfer pulses φH1, φH2
And the reset pulse φR has a phase relationship of clock signal CL.
K is uniquely managed.

The horizontal synchronizing signal DHD applied to the drive signal generating circuit 11 is obtained by delaying the horizontal synchronizing signal HD generated by the DSP 13 by the delay circuit 15. By adjusting the delay time of the delay circuit 15, the phase of the horizontal synchronization signal DHD input to the latch circuit 31 with respect to the clock signal CLK is adjusted, whereby the period of the transfer period signal HMASK is adjusted, and the horizontal transfer pulse is adjusted. φH
1. The pause period of φH2 is adjusted. Here, by adjusting the delay circuit 15 so that the phase of the horizontal synchronization signal DHD input to the latch circuit 31 is in the middle of the latch position,
During a period approximately twice the pulse width of the clock signal CLK, even if the clock signal CLK fluctuates due to a signal delay due to the cable 5 or a fluctuation in the signal delay due to a temperature change, the imaging signal C
A deviation between the timing of CDout and the operation timing of the DSP 13 can be prevented, and a malfunction such as color inversion in the video signal processing by the DSP 13 can be prevented. That is, by adjusting the delay circuit 15, it is possible to adjust a margin for malfunction such as color inversion.

As described above, according to the endoscope imaging apparatus 1 of the present embodiment, the reset pulse extraction shaping circuit 1
According to 6, the phase comparator 18 compares the phase of the clock signal DRCK obtained by extracting the reset pulse from the imaging signal CCDout and delaying the waveform of the clock signal RCK, and the phase of the clock signal DMCK obtained by delaying the clock signal MCK. VCO 1 according to the output from phase comparator 18
9 controls the oscillation frequency of the clock signal CLK, and the drive signal generation circuit 11 generates the horizontal transfer pulses φH1 and φH2 and the reset pulse φR to drive the CCD 2 according to the clock signal CLK, so that the cable length can be corrected. It has become. Further, the drive signal generation circuit 11 is configured by a simple circuit including a flip-flop, a latch, a logic gate circuit, a driver, a counter, a comparator, and the like.
This is configured on a small scale as compared with a case where this is configured by, for example, a DSP or the like. Also, the horizontal synchronizing signal HD etc.
3 does not perform complicated control such as advancing this phase, and has a simpler circuit configuration than the conventional technology. As mentioned above,
According to the endoscope imaging apparatus 1 of the present embodiment, cable length correction can be performed with a small and simple circuit configuration. Also, by providing the delay circuits 17a and 17b, D
The phase of the sampling signals SHD, SHP and the like provided from the SP 13 to the CDS circuit 12 and the phase of the imaging signal CCDout can be adjusted so as to have an optimum relationship regardless of the cable length of the cable 5. The sampling process is performed optimally. Further, the provision of the delay circuit 15 allows the clock signal CLK to be changed due to a signal delay due to the cable 5 or a change in signal delay due to a temperature change.
Can be adjusted so as to prevent a malfunction such as color inversion in the video signal processing by the DSP 13 even if. As described above, it is possible to perform good cable length correction with little influence of temperature fluctuation.

FIG. 10 is a block diagram showing the arrangement of a frequency divider, a transfer period signal generator, a horizontal transfer pulse generator, and a reset pulse generator according to a modification of the first embodiment. Note that, in the present modification, only portions having a different configuration from the first embodiment will be described. Further, portions having the same functions as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 10, in the present modification, the drive signal generation circuit 11 does not generate the horizontal transfer pulses φH1 and φH2 and the reset pulse φR, and generates the reference clock signal CLKB and transfer period signal HMASK and the transfer signal HB via the cable 5.
MASK is provided to the camera head 3.
That is, the frequency divider 21 and the transfer period signal generator 22
Are provided in the drive signal generation circuit 11, and the horizontal transfer pulse generation circuit 23 and the reset pulse generation circuit 24 are provided in the camera head 3. In this modification described above, in addition to the effects of the first embodiment, the cable 5
This has the effect that one signal to be transmitted can be reduced. In addition, horizontal transfer pulses φH1, φH2 and reset pulse φR
Is not output on the CCU 4 side, so that the driver 36 can be omitted from the CCU 4 side. Thereby, the cable 5
The signal level transmitted through the inside can be kept low,
It is possible to realize the endoscope imaging apparatus 1 that is good for noise countermeasures such as C. Further, heat generation inside the CCU 4 can be reduced.

Incidentally, the first delay circuit 17 shown in FIG.
a and the second delay circuit 1
The logic gate circuit 42 constituting 7b may be housed in the same semiconductor package 51. With this configuration, the difference in the delay time variation between the first delay circuit 17a and the second delay circuit 17b due to the temperature variation is offset,
It is possible to improve the margin of the cable length correction by the endoscope imaging apparatus 1 with respect to the temperature fluctuation.

The logic gate circuit 42 forming the third delay circuit 15 shown in FIG. 8 is replaced by the first and second logic circuits 42 shown in FIG.
Logic gate circuit 4 constituting delay circuits 17a and 17b
2 may be housed in the same semiconductor package 51. With this configuration, the difference in the delay time variation between the first and second delay circuits 17a and 17b and the third delay circuit 15 due to the temperature variation is offset, and the horizontal synchronization signal DHD is latched by the latch circuit 31. The shift of the latch timing due to the temperature fluctuation at the time of the reduction is reduced, and the occurrence of the color inversion can be suppressed.

The logic gate circuit forming the waveform shaping circuit 16b shown in FIG. 7 is mounted on the same semiconductor package 51 as the logic gate circuit 42 forming the first and second delay circuits 17a and 17b shown in FIG. It may be configured by storing it.
With this configuration, the fluctuation of the propagation delay time due to the temperature fluctuation in the waveform shaping circuit 16b is caused by the fluctuation of the propagation delay time of one of the logic gate circuits 42 in the second and / or third delay circuits 17a and 17b. Is the same as Further, in this case, a logic gate circuit included in the semiconductor package 51 containing the logic gates constituting the waveform shaping circuit 16b may be inserted in a stage preceding the delay circuit 17b shown in FIG. With this configuration, it is possible to reduce a difference in delay time variation between the clock signal RCK and the clock signal MCK due to a temperature change.

Further, a dummy circuit (not shown) having a configuration following the same delay path as the reset pulse extraction and shaping circuit 16 shown in FIG. 7 may be inserted in the preceding stage of the delay circuit 17b. Further, at this time, the semiconductor components in the dummy circuit arranged at the same position as the semiconductor components such as the selector of the reset pulse extraction and shaping circuit 16 may be housed in the same semiconductor package. With such a configuration, it is possible to cancel a difference in a delay time variation between the clock signal RCK and the clock signal MCK due to a temperature change. In addition, for components other than semiconductor components, such as passive components such as resistors and capacitors, a configuration may be used in which a resistor array is used or thermal coupling is performed in close proximity.

The present invention is not limited to the above-described embodiment, but can be variously modified without departing from the gist of the invention. For example, in the above-described embodiment, the configuration in which the camera head 3 equipped with the CCD 2 and the CCU 4 are connected by the cable 5 has been described.
Needless to say, the CD and the CCU 4 may be connected by a cable.

[Supplementary Note] (Supplementary item 1-1) A solid-state image pickup device that captures an image of a subject and outputs an image pickup signal, and a unit that shapes a signal component extracted from the image pickup signal to obtain a first clock signal. First delay means for delaying the first clock signal, signal processing means for processing the image signal, means for oscillating a second clock signal to be provided to the signal processing means,
Second delay means for delaying the clock signal of
A phase comparator for comparing the phase of the output signal from the delay means with the phase of the output signal from the second delay means, and an oscillator controlled by the output from the phase comparator to oscillate a third clock signal. Means for generating a horizontal synchronization signal used by the signal processing means in synchronization with the second clock signal; third delay means for delaying the horizontal synchronization signal; and output from the third delay means. A horizontal transfer pulse and a reset pulse for driving the image sensor from the signal and the third clock signal, or a drive signal generating unit for generating a pulse serving as a reference signal for the horizontal transfer pulse and the reset pulse. An endoscope imaging apparatus, wherein the drive signal generation means includes a horizontal transfer pulse and a reset signal based on an output signal from the third delay means and the third clock signal. Pulse, or, endoscopic imaging apparatus characterized by being configured from a circuit for generating a pulse as a reference signal of the horizontal transfer pulse and the reset pulse.

(Additional Item 1-2) In the endoscope imaging apparatus according to additional item 1-1, the oscillator oscillates at a frequency twice as high as the reset pulse as a third clock signal. The drive signal generating means has a circuit that operates using the third clock signal as a reference clock, and divides the frequency of the third clock signal by half to output a fourth clock signal.

(Additional Item 1-3) The endoscope imaging apparatus according to Additional Item 1-2, wherein the drive signal generating means generates a transfer period signal indicating a pause period of the horizontal transfer pulse. A period signal generation circuit.

(Additional Item 1-4) The endoscope imaging apparatus according to additional item 1-3, wherein the transfer period signal generation circuit comprises:
A latch circuit that latches an output signal of the third delay unit in accordance with the third clock signal and the fourth clock signal, and differentiates an output signal of the latch circuit in accordance with the third clock signal A differentiating circuit, and the third clock signal according to the fourth clock signal and the output signal of the differentiating circuit.
A counter circuit for counting the number of pulses of the clock signal of
A circuit for determining a start timing and an end timing of the transfer period signal according to the count value of the counter circuit to obtain a transfer period signal.

(Supplementary item 2-1) A solid-state imaging device for imaging a subject and outputting an imaging signal, a means for waveform-shaping a signal component extracted from the imaging signal to obtain a first clock signal, First delay means for delaying one clock signal, signal processing means for processing the imaging signal, means for oscillating a second clock signal to be provided to the signal processing means, and delaying the second clock signal A second delay unit, a phase comparator for comparing a phase of an output signal from the first delay unit with a phase of an output signal from the second delay unit, and a phase comparator controlled by an output from the phase comparator. Third
An oscillator that oscillates the clock signal, a means for generating a horizontal synchronization signal used by the signal processing means in synchronization with the second clock signal, a third delay means for delaying the horizontal synchronization signal, A drive for generating a horizontal transfer pulse and a reset pulse for driving the image sensor from the output signal from the third delay unit and the third clock signal, or a pulse serving as a reference signal for the horizontal transfer pulse and the reset pulse. An endoscope imaging apparatus comprising a signal generation unit, wherein a semiconductor circuit forming the first delay unit and a semiconductor circuit forming the second delay unit are contained in the same semiconductor element. An endoscope imaging device characterized by the above-mentioned.

(Additional Item 2-2) The endoscope imaging apparatus according to additional item 2-1 wherein the semiconductor circuit forming the first delay means and the semiconductor circuit forming the second delay means An endoscope imaging apparatus, wherein a semiconductor circuit constituting the third delay means is housed in the same semiconductor element.

[0044]

As described above, according to the present invention,
Cable length correction can be performed with a small and simple circuit configuration.

[Brief description of the drawings]

FIGS. 1 to 9 relate to a first embodiment of the present invention, and FIG. 1 is a block diagram showing an overall configuration of an endoscope imaging apparatus;

FIG. 2 is a block diagram illustrating a configuration of a drive signal generation circuit.

FIG. 3 is a block diagram showing a configuration of a frequency dividing circuit;

FIG. 4 is a block diagram illustrating a configuration of a latch circuit.

FIG. 5 is a block diagram showing a configuration of a differentiating circuit;

FIG. 6 is a block diagram illustrating a configuration of a counter circuit and a transfer period determination circuit.

FIG. 7 is a block diagram showing a configuration of a reset pulse extraction shaping circuit and a delay circuit;

FIG. 8 is a block diagram illustrating a configuration of a delay circuit.

FIG. 9 is a waveform chart showing an operation of the drive signal generation circuit.

FIG. 10 is a block diagram showing arrangement positions of a frequency divider, a transfer period signal generator, a horizontal transfer pulse generator, and a reset pulse generator according to a first modification of the first embodiment;

11 to 13 are used for explaining a conventional technique, and FIG. 11 is a block diagram showing a configuration example of an imaging device such as a video camera.

FIG. 12 is a block diagram illustrating a configuration example of an endoscope imaging apparatus including a cable length correction unit.

FIG. 13 is a block diagram showing a configuration example different from FIG. 12 of an endoscope imaging apparatus including a cable length correction unit;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Endoscope imaging device 2 ... CCD 4 ... CCU 5 ... Cable 11 ... Drive signal generation circuit 12 ... CDS circuit 13 ... DSP 14 ... Oscillator 16 ... Reset pulse extraction and shaping circuit 18 ... Phase comparator 19 ... VCO

Continued on the front page F term (reference) 4C061 AA00 AA29 BB01 CC07 DD00 FF02 JJ19 LL03 NN01 NN03 SS03 SS12 SS17 UU03 UU09 5C022 AA09 AB64 AB65 AB68 AC42 AC69 AC75 5C024 AA01 CA25 FA01 GA11 HA09 5C054 AA01 CA03 EC03 FA03 HA12

Claims (1)

[Claims] A solid-state image pickup device for picking up an image of a subject and outputting an image pickup signal;
Means for obtaining a clock signal, first delay means for delaying the first clock signal, signal processing means for processing the image signal, and means for oscillating a second clock signal to be provided to the signal processing means. A second delay unit that delays the second clock signal; a phase comparator that compares a phase of an output signal from the first delay unit with an output signal from the second delay unit; An oscillator controlled by an output from the phase comparator to oscillate a third clock signal; a means for generating a horizontal synchronization signal used by the signal processing means in synchronization with the second clock signal; Third delay means for delaying a synchronization signal; a horizontal transfer pulse and a reset pulse for driving the image sensor from an output signal from the third delay means and the third clock signal; And a drive signal generating means for generating a pulse serving as a reference signal of the horizontal transfer pulse and the reset pulse, wherein the drive signal generating means comprises: An endoscope comprising a circuit for generating a horizontal transfer pulse and a reset pulse from an output signal and the third clock signal, or a pulse serving as a reference signal of the horizontal transfer pulse and the reset pulse. Imaging device.