JP2002369072A - Signal processor and driving control method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To immediately restore the inter-timing clock phase of a camera head side and a camera main body side to a positive phase when the phase is turned to be negative, and to automatically correct a power supply voltage to be supplied from the camera main body side to the camera head side in a head separation type 3CCD camera. SOLUTION: Timing clocks CKa and CKb to be outputted from timing generators 113 and 121 at camera main body 110 side and a camera ahead 120 side are phase-compared, and a clock generator 111 is controlled according to the phase compared output. The timing clock CKb to be outputted from the head side timing generator 121 is superimposed on DC components corresponding to a head side power supply voltage, and the DC components are extracted from the signal by the main body 110 side, and fed back to a voltage control type voltage booster 119 so that a stable power supply voltage can be obtained as the boosted power supply voltage, and transmitted form the main body 110 side to the head 120 side under the consideration of the influence of voltage drop due to a plurality of cable lengths.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus main body including a main body side signal processing means for performing signal processing in accordance with a timing pulse generated by a main body side timing generation means based on a clock given by a clock generation means;
A signal processing device comprising a head provided with a head-side signal processing means for performing signal processing in accordance with a timing pulse generated by a head-side timing generation means based on a clock supplied from the apparatus main body via a cable, and a drive therefor Regarding the control method, for example, a so-called head-separated type in which an imaging unit (camera head) and a signal processing unit (camera main body) that processes and outputs an imaging signal from the imaging unit are separated and connected therebetween by a cable or the like. It is applied to an imaging system called a camera.

[0002]

2. Description of the Related Art Conventionally, in an imaging system using a solid-state imaging device such as a CCD image sensor, an imaging unit (camera head) and a signal processing unit (camera body) for processing and outputting imaging signals from the imaging unit are separated. In addition, there have been proposed many imaging systems called so-called head-separated cameras in which a cable or the like is connected between them.

[0003] Referring to FIG.
A conventional example of the CCD camera 200 will be described.

This head-separated 3CCD camera 200
Is composed of a camera body 210, a camera head 220, and an imaging lens 230. The camera body 210 and the camera head 220 are connected via a cable 240.

The camera body 210 is, for example, 28 MHz
, A clock generator 211 for generating a clock CK0, a synchronization generator 212 for generating a horizontal synchronization signal HD and a vertical synchronization signal VD, a timing generator 213, and a signal processing circuit 214.

The camera head 220 includes a timing generator 221, a CCD image sensor 222R for capturing a red image, and a CCD image sensor 22R for capturing a green image.
CCD image sensor 222B for capturing 2G and blue images
And an operational amplifier 223.

The clock generator 211 of the camera body 210
Supplies the clock CK0 to the timing generator 213. The clock CK0 generated by the clock generator 211 is supplied to the timing generator 221 of the camera head 220 via the signal line L2.

Further, the synchronization generator 21 of the camera body 210
2 supplies the horizontal synchronizing signal HD and the vertical synchronizing signal VD to the timing generator 213. Further, the synchronization generator 21
2 is supplied to the timing generator 221 of the camera head 220 via the signal line L1.

Further, a timing generator 213 on the camera body 210 side generates an image signal based on a clock CK0 provided by the clock generator 211 and a horizontal synchronization signal HD and a vertical synchronization signal VD provided by the synchronization generator 212. 14 MHz timing clock CKa and various timing pulses SHP and SH necessary for signal processing
D and the like are generated and given to the signal processing circuit 214.

Then, the signal processing circuit 214 converts the image signal supplied from the operational amplifier 223 of the camera head 220 through the signal line L3 into the timing generator 2
Based on the timing clock CKa and various timing pulses SHP and SHD provided by the control unit 13, signal processing such as predetermined process processing is performed to output a color video signal.

The camera head 220 is mounted on the camera body 2
The drive is performed by supplying the main body side power supply voltage as the camera head side power supply voltage through the signal line L4 from the 10 side.

The timing generator 221 of the camera head 220 has a clock CK0 of 28 MHz supplied from the clock generator 211 of the camera body 210 through a signal line L2 and a signal line CK0 of the synchronization generator 212 of the camera body 210. Based on the horizontal synchronization signal HD and the vertical synchronization signal VD supplied through L1, a CCD image sensor 222R for capturing a red image and a C
CD image sensor 222G and CC for capturing a blue image
14 MHz for driving the D image sensor 222B
And generates various timing pulses SHP,
Generate SHD.

The 14 MHz timing clock CKb generated by the timing generator 221 is supplied to a CCD image sensor 222R for capturing a red image, a CCD image sensor 222G for capturing a green image, and a CCD image sensor 222B for capturing a blue image. Is done. The timing pulses SHP and SHD generated by the timing generator 221 are correlated double sampling.
(CDS: Correlated Double Sampling) is supplied to the operational amplifier 223 as a sampling clock.

The CCD image sensor 222R for capturing the red image and the CCD image sensor 2 for capturing the green image.
CCD image sensor 22 for capturing 22G and blue images
The image output by 2B is amplified by the operational amplifier 223, correlated double-sampled, taken out, amplified as an image signal, and supplied to the signal processing circuit 214 of the camera body 210 through the signal line L3.

In the head-separated type 3CCD camera 200, each of the timing generators 213 and 221 divides the frequency of the 28 MHz clock CK0 generated by the clock generator 211 of the camera body 210 into 1/2, and
MHz timing clocks CKa and CKb are generated. The timing generators 213 and 221 are synchronized by the horizontal synchronization signal HD and the vertical synchronization signal VD generated by the synchronization generator 212 on the camera body 210 side.

Next, each signal timing in the head-separated 3CCD camera 200 will be described with reference to the timing chart of FIG.

That is, FIG. 4A shows the clock generator 21.
The waveform of the clock CK0 of 1 to 28 MHz is shown. 14 MH from the timing generator 213 of the camera body 210
The waveform of the z timing clock CKa is shown in FIG. 4B.

FIG. 4C shows an SHP signal from the timing generator 213 of the camera body 210, which is a pulse signal for sampling and holding the precharge portion in the CCD output signal.

FIG. 4D shows an SHD signal from the timing generator 213 of the camera body 210, which is a pulse for sampling and holding the data portion in the CCD output signal.

FIG. 4E shows that the 14 MHz timing clock CKb from the timing generator 211 of the camera head 220 is output from the timing generator 213 of the camera body 210.
The phase is opposite to the 14 MHz timing clock CKa.

FIG. 4F is a timing chart of the signal from the timing generator 221 on the camera head 220 side at the timing of FIG. 4E.
An HP signal, which is a pulse signal for sampling and holding the precharge portion in the CCD output signal.

FIG. 4G is a timing chart showing the operation of the timing generator 221 on the camera head 220 side at the timing shown in FIG. 4E.
An HD signal, which is a pulse for sampling and holding the data portion in the CCD output signal.

When the 14 MHz timing clock of the camera head 220 is in phase with the 14 MHz timing clock of the camera body 210, the 14
The waveform of the MHz timing clock is the same as in FIG. 4B.

Therefore, if the waveform of the 14 MHz timing clock on the camera head 220 side is as shown in FIG. 3E with respect to the waveform of the 14 MHz timing clock on the camera body 210 side in FIG.
The phase of the 14 MHz timing clock on the camera body 210 side is opposite to the phase of the 14 MHz timing clock on the camera body 210 side, and the waveform of the 14 MHz timing clock on the camera head 220 side is the 14 MHz timing clock on the camera body 210 side in FIG. If the clock waveform is the same, it can be determined that the phase between the 14 MHz timing clock on the camera head 220 side and the 14 MHz timing clock on the camera body side is the same.

[0025]

By the way, in the head-separated type 3CCD camera 200 having the above-mentioned structure, the clock CK0 from the clock generator 211 is obtained by dividing the clock CK0 by the timing generators 213 and 221 respectively. If the timing clocks CKa and CKb are out of phase with each other, the color video signal obtained from the signal processing circuit 214 will not be a normal video signal.

Since such a phenomenon (which theoretically occurs with a probability of 50%) often occurs when the power supply is turned on, this phenomenon is usually detected by software when the power supply is turned on. The clock generator 211 temporarily stops the oscillation of the clock generator 211 and oscillates again, so that the timing clocks CKa and CKb have the same phase. However, during shooting of the subject, the timing clocks CKa and CKb may be out of phase due to disturbances such as electrostatic noise. In such a case, the imaging is stopped, the power is turned off, and then the power is turned on again. Then, the timing clocks CKa and CKb must be in phase, which is very inconvenient in practical use.

A head-separated 3CCD camera 200
In this case, since the camera head 220 and the camera body 210 are connected via the cable 240, a difference in voltage drop caused by a plurality of types of cable lengths connecting the camera head 220 and the camera body 210 causes the camera head side power supply to change. There is a possibility that the power supply voltage supplied to the timing generator 221 and the operational amplifier 223 on the camera head 220 side does not satisfy the power supply voltage specification. In this case, the operation of the head-separated 3CCD camera 200 Cannot be guaranteed.

In view of the above-mentioned conventional problems, an object of the present invention is to provide a camera head having an image pickup device and a camera head side timing generator for supplying a timing signal to the image pickup device, and an image pickup signal from the image pickup device. A signal processing circuit for obtaining a video signal by performing signal processing, a camera body side timing generator for supplying a timing signal to the signal processing circuit, a clock generator for generating a clock supplied to the camera head side timing generator, a camera body side timing A camera body including a clock generator for generating a clock to be supplied to the generator, a camera body including a synchronization generator for generating horizontal and vertical synchronization signals to be commonly supplied to a camera head side and a camera body side timing generator, And the camera body are connected to each other through signal lines, and the camera head side and the camera body side In ring generator, by dividing with a same frequency division ratio of the clock signal from the clock generator,
In addition to generating timing clocks for the camera head and the camera body, respectively, synchronizing with the timing clocks for the camera head and the camera body, respectively, and generating a phase discriminating signal for the camera head and the camera body indicating the respective phases. It is an object of the present invention to provide a head-separated 3CCD camera capable of immediately returning to the normal phase when the phase between the timing clocks on the camera head side and the camera body side is reversed.

The power supply voltage supplied from the camera body side to the camera head side is set so that the power supply voltage supplied from the camera body side to the timing generator and the operational amplifier on the camera head side does not satisfy the power supply voltage specification. The purpose is to enable automatic correction.

[0030]

According to the present invention, there is provided an apparatus main body including a main body side signal processing means for performing signal processing in accordance with a timing pulse generated by a main body side timing generation means based on a clock provided by a clock generation means; A signal processing apparatus comprising a head and a head having signal processing means for performing signal processing in accordance with a timing pulse generated by a head-side timing generation means based on a clock supplied from the apparatus main body via a cable, Phase comparing means for comparing the phase of the timing pulse generated by the main body-side timing generating means with the timing pulse generated by the head-side timing generating means, and converting means for converting the phase comparison output by the phase comparing means into a control voltage And the control power obtained by this conversion means. A voltage-controlled clock generating means whose oscillation phase is controlled by the main body-side timing generating means, wherein a clock generated by the voltage-controlled clock generating means is supplied to the head-side timing generating means; The oscillation phase of the voltage-controlled clock generation means is controlled by a control voltage obtained by the conversion means so that the timing pulse generated by the control means and the timing pulse generated by the head-side timing generation means have the same phase. And

In the signal processing device according to the present invention, for example,
DC component extracting means for extracting a DC component from a timing pulse generated by the head-side timing generating means, and voltage control for boosting a main body side power supply voltage using the DC component extracted by the DC component extracting means as a control voltage. Providing a mold voltage boosting means in the device main body, supplying a power supply voltage higher than the main body side power supply voltage to the head side as a head side power supply voltage by the voltage control type voltage boosting means,
The head-side timing generation means driven by the head-side power supply voltage generates a timing pulse superimposed on a DC component proportional to the head-side power supply voltage, and returns the timing pulse from the head side to the apparatus main body. By extracting the superposed DC component by the DC component extracting means and controlling the voltage-controlled voltage boosting means, the head-side power supply voltage automatically corrected from the voltage-controlled voltage boosting means is supplied to the head side. Can be supplied.

In the signal processing device according to the present invention, for example, the head is a camera head having an image pickup unit, and the device main body is a signal processing unit that performs signal processing on an image pickup signal supplied from the camera head. Camera body provided with

According to the present invention, there is provided an apparatus main body including a main body side signal processing means for performing signal processing in accordance with a timing pulse generated by a main body side timing generation means based on a clock given by a clock generation means, and supplied from the apparatus main body. A drive control method for a signal processing device, comprising: connecting via a cable to a head including a head-side signal processing unit that performs signal processing in accordance with a timing pulse generated by a head-side timing generation unit based on a clock; The phase of the timing pulse generated by the main body-side timing generator is compared with the phase of the timing pulse generated by the head-side timing generator, and the phase of the clock supplied to the head-side timing generator is determined according to the phase comparison result. Control the main body side timing generator As the timing pulses generated by the generation timing pulse and the head-side timing generating means in phase by, and controls the phase of the clock supplied to the head-side timing generating means.

In the drive control method of the signal processing device according to the present invention, for example, the DC component is extracted from the timing pulse generated by the head-side timing generating means, and the main unit power supply voltage is extracted according to the extracted DC component. Is supplied from the apparatus main body side to the head side, and is superimposed on a DC component proportional to the head side power supply voltage by the head side timing generation means driven by the head side power supply voltage. A timing pulse is generated and returned from the head side to the apparatus main body, and a DC component on which the timing pulse is superimposed is extracted and a head side power supply voltage automatically corrected and supplied to the head side. it can.

[0035]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The present invention is applied to, for example, a head-separated 3CCD camera 100 having a structure as shown in FIG.

This head separated type 3CCD camera 100
The camera body 110 includes a camera body 110, a camera head 120, and an imaging lens 130. The camera body 110 and the camera head 120 are connected via a cable 140.

The camera body 110 is, for example, 28 MHz
Clock generator 111 for generating clock CK0, synchronization generator 112 for generating horizontal synchronization signal HD and vertical synchronization signal VD, timing generator 113, signal processing circuit 1
14, phase comparator 115, loop filter 116, voltage-controlled clock generator 117, low-pass filter 118
And a voltage-controlled voltage booster 119.

The camera head 120 includes a timing generator 121, a CCD image sensor 122R for capturing a red image, and a CCD image sensor 12R for capturing a green image.
CCD image sensor 122B for capturing 2G and blue images
And an operational amplifier 123.

The clock generator 111 of the camera body 110
Supplies the clock CK0 to the timing generator 113.

The synchronization generator 11 of the camera body 110
2 supplies a horizontal synchronizing signal HD and a vertical synchronizing signal VD to the timing generator 113. In addition, the synchronization generator 11
2 are supplied to the timing generator 121 of the camera head 120 via the signal line L1.

The timing generator 113 on the camera body 110 side generates an image signal based on the clock CK0 provided by the clock generator 111 and the horizontal synchronization signal HD and the vertical synchronization signal VD provided by the synchronization generator 112. 14 MHz timing clock CKa and various timing pulses SHP and SH necessary for signal processing
D and the like are generated and supplied to the signal processing circuit 114, and the 14 MHz timing clock CKa is supplied to the phase comparator 115.

Then, the signal processing circuit 114 converts the image signal supplied from the operational amplifier 123 of the camera head 120 through the signal line L3 into the timing generator 1
Based on the timing clock CKa and various timing pulses SHP and SHD provided by the control unit 13, signal processing such as predetermined process processing is performed to output a color video signal.

The phase comparator 11 of the camera body 110
5 is a timing clock C supplied from the timing generator 121 of the camera head 120 via the signal line L5.
Kb is compared in phase with the timing clock CKa provided by the timing generator 113. The phase comparison output by the phase comparator 115, that is, the phase error output of the timing clock CKb with respect to the timing clock CKa is converted to a DC voltage via the loop filter 116 and supplied to the voltage control type clock generator 117 as a control voltage. You.

The voltage-controlled clock generator 117 includes:
The oscillation output is supplied as a clock CK1 to the timing generator 121 of the camera head 120 through the signal line L2.

This voltage controlled clock generator 117
The camera head 120 based on the clock CK1
Clock CK output from the timing generator 121 of FIG.
b (14 MHz) and the timing generator 1 on the camera body side
The oscillation phase is controlled by the control voltage supplied from the phase comparator 115 via the loop filter 116 so that the clock CKb (14 MHz) output from the controller 13 becomes in phase.

The low-pass filter 118 of the camera body 110 extracts the DC component of the signal on which the timing clock CKb supplied from the timing generator 121 of the camera head 120 via the signal line L5 is superimposed,
The extracted DC component is supplied to the voltage-controlled voltage booster 119 as a control voltage. Then, the voltage control type voltage booster 119 on the camera body 110 side supplies a power supply voltage higher than the camera body side power supply voltage obtained by boosting the camera body side power supply voltage as the camera head side power supply voltage.

That is, by controlling the voltage-controlled voltage booster 119 using the DC component extracted by the low-pass filter 118 as a control voltage, the camera head 1
Camera head 1 due to different voltage drops caused by a plurality of cable lengths connecting camera body 20 and camera body 110.
The power supply voltage supplied to the power supply 20 is automatically corrected from becoming unstable, and a stable power supply voltage is supplied from the camera body 110 to the camera head 120 via the signal line L4.

Here, the timing clock CKb returned from the timing generator 121 of the camera head 120 to the camera body 110 through the signal line L5 is formed by superposing a waveform of a signal superimposed on a DC voltage corresponding to the camera head side power supply voltage. As shown in FIG. 2A. FIG. 2B shows a signal waveform of only a DC voltage component extracted by inputting a signal in which the timing clock CKb is superimposed on a DC voltage corresponding to a power supply voltage on the camera head side to a low-pass filter 118 on the camera body 110 side. .

The camera head 110 is mounted on the camera body 1
The power supply voltage automatically corrected from the voltage control type voltage booster 119 on the 10 side is supplied as the camera head side power supply voltage via the signal line L4 to drive.

The timing generator 121 of the camera head 120 is supplied from a voltage-controlled clock generator 117 of the camera body 110 through a signal line L2.
Based on the 8 MHz clock CK1 and the horizontal synchronizing signal HD and the vertical synchronizing signal VD supplied from the synchronizing generator 112 of the camera body 110 through the signal line L1, the CCD image sensor 122R for capturing a red image and the green image capturing And a timing clock CKb of 14 MHz for driving the CCD image sensor 122G and the blue image capturing CCD image sensor 122B, and various timing pulses SHP and SHD necessary for signal processing of the image capturing signal.

The 14 MHz timing clock CKb generated by the timing generator 121 is supplied to a CCD image sensor 122R for capturing a red image, a CCD image sensor 122G for capturing a green image, and a CCD image sensor 122B for capturing a blue image. Is done. The timing pulses SHP and SHD generated by the timing generator 121 are correlated double sampling.
It is supplied to the operational amplifier 123 as a sampling clock for (CDS: Correlated Double Sampling). Further, the timing generator 121 supplies a signal obtained by superimposing the timing clock CKb on a DC voltage corresponding to the head-side power supply voltage to the phase comparator 115 and the low-pass filter 118 of the camera body 110 through the signal line L5.

The CCD image sensor 122R for capturing the red image and the CCD image sensor 1 for capturing the green image.
CCD image sensor 12 for capturing 22G and blue images
The image output by 2B is amplified by the operational amplifier 123, correlated double-sampled, taken out, amplified as an image signal, and supplied to the signal processing circuit 114 of the camera body 110 through the signal line L3.

In the head-separated 3CCD camera 100 having such a configuration, the timing generator 113 on the camera body 110 side and the timing generator 121 on the camera head 120 side are connected to the clock generator 11 on the camera body 110 side.
The clock CK0 of 28 MHz generated by 1 is 1 /
Divided by 2 to 14 MHz timing clock CK
a, CKb is generated. Further, each of the timing generators 1 is controlled by the horizontal synchronization signal HD and the vertical synchronization signal VD generated by the synchronization generator 112 on the camera body 110 side.
13, 121 are synchronized.

In the head-separated 3CCD camera 100, the clock CKb () output from the timing generator 121 of the camera head 120 based on the clock CK1 generated by the voltage-controlled clock generator 117 on the camera body 110 side. 14 MHz) and the clock CKb output from the timing generator 113 on the camera body side.
(14 MHz), the oscillation phase of the voltage-controlled clock generator 117 is controlled by the control voltage supplied from the phase comparator 115 via the loop filter 116 so that each timing Table 11
3, 121 can immediately return to the normal phase when the phase between the generated timing clocks is reversed.

Therefore, in the head-separated 3CCD camera 100, when the phase between the timing clock on the camera body 110 and the timing clock on the camera head 120 is reversed, it can be immediately returned to the normal phase. During imaging, even if the phase between the timing clock on the camera body 110 side and the timing clock on the camera head 120 side is reversed and the color video signal temporarily becomes abnormal, the color video signal is immediately returned to the normal color video signal. In addition, even when the timing clock on the camera body 110 side and the timing clock on the camera head 120 side become opposite in phase when the power supply rises, it is possible to easily and easily return to the normal phase.

The head-separated 3CCD camera 1
00, the timing generator 1 on the camera head 120 side
By extracting the DC component from the timing clock CKb output from the low-pass filter 118 on the camera body 110 side and controlling the voltage-controlled voltage booster 119 as a control voltage using the extracted DC component, the camera head The power supply voltage supplied to the camera head 120 becomes unstable due to different voltage drops caused by a plurality of types of cable lengths connecting the camera body 120 and the camera body 110. A voltage can be supplied to the camera head 120 through the signal line L4.
In the D camera 100, each control voltage for performing the phase control of the timing clock and the correction control of the power supply voltage is set to 1
The clock CKb sent via the signal line L5 can be obtained from the signal superimposed on the DC component.

[0058]

As described above, according to the present invention, there is provided an apparatus including a main body signal processing means for performing signal processing in accordance with a timing pulse generated by a main body timing generation means based on a clock provided by a clock generation means. A signal processing device comprising a main body and a head including a head-side signal processing means for performing signal processing in accordance with a timing pulse generated by a head-side timing generation means based on a clock supplied from the apparatus main body, via a cable A phase comparison between the timing pulse generated by the main body-side timing generator and the timing pulse generated by the head-side timing generator, and a clock supplied to the head-side timing generator in accordance with the phase comparison result Control the phase of the By controlling the phase of the clock supplied to the head-side timing generating means so that the timing pulse generated by the generating means and the timing pulse generated by the head-side timing generating means have the same phase, each timing generating means Can be immediately returned to the normal phase when the phase between the timing clocks is reversed.

Further, according to the present invention, the direct-current component is extracted from the timing pulse generated by the head-side timing generating means, and the main-unit power supply voltage is increased in accordance with the extracted direct-current component. Is supplied from the apparatus body side to the head side, and a DC component corresponding to the head side power supply voltage included in the timing pulse generated by the head side timing generation means driven by the head side power supply voltage is extracted. Thus, the head-side power supply voltage automatically corrected can be supplied to the head side.

Further, according to the present invention, the phase control of the timing clock and the correction control of the power supply voltage are performed based on the timing pulse generated by the head-side timing generating means. Can be minimized. That is, the phase control of the timing clock and the correction control of the power supply voltage can be performed using one signal line.

Therefore, by applying such an invention to a head-separated camera, when the phase between the timing clocks on the camera head side and the camera body side is reversed, it can be immediately returned to the normal phase. Even if the phase between the timing clocks on the camera head side and the camera body side is reversed during imaging, and the color video signal temporarily becomes abnormal, it is possible to immediately return to the normal color video signal, Even when the phase between the timing clocks on the camera head side and the camera body side is reversed when the power supply rises, the phase can be easily and easily returned to the normal phase.

Further, the power supply voltage supplied to the camera head side is automatically corrected from being unstable due to different voltage drops caused by a plurality of types of cable lengths connecting the camera head and the camera body, and the camera body is stabilized. The supplied power supply voltage can be supplied to the camera head side. Moreover,
Since the phase control of the timing clock and the correction control of the power supply voltage are performed based on the timing pulse generated by the head-side timing generating means, an increase in the number of signal lines of the cable connecting the camera body and the head is minimized. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a head-separated 3CCD camera to which the present invention is applied.

FIG. 2 shows a waveform of a signal in which a timing clock generated by a timing generator on the camera head side is superimposed on a DC voltage corresponding to a power supply voltage on the camera head side, and a low-pass on the camera body side in the head-separated 3CCD camera. FIG. 3 is a waveform diagram showing a signal waveform of only the DC voltage component obtained by a filter.

FIG. 3 is a block diagram showing a configuration of a conventional head-separated 3CCD camera.

FIG. 4 is a timing chart showing signal timings in the head-separated 3CCD camera.

[Explanation of symbols]

100 head separated type 3CCD camera, 110 camera body, 111 clock generator, 112 synchronization generator,
113 timing generator, 114 signal processing circuit, 1
15 phase comparator, 116 loop filter, 117
Voltage-controlled clock generator, 118 low-pass filter, 119 voltage-controlled voltage booster, 120 camera head, 121 timing generator, 122R, 122
G, 122 BCCD image sensor, 123 operational amplifier, 130 imaging lens, 140 cable

Claims (5)

[Claims] 1. An apparatus main body comprising a main body side signal processing means for performing signal processing according to a timing pulse generated by a main body side timing generation means based on a clock given by a clock generation means; A signal processing device that is connected via a cable to a head including a head-side signal processing unit that performs signal processing in accordance with a timing pulse generated by the head-side timing generation unit based on the signal. Phase comparing means for comparing the phase of the generated timing pulse with the timing pulse generated by the head-side timing generating means, converting means for converting the phase comparison output by the phase comparing means into a control voltage, and the converting means. Oscillation phase is controlled by control voltage A voltage-controlled clock generating means provided in the apparatus main body, a clock generated by the voltage-controlled clock generating means is supplied to the head-side timing generating means, and a timing pulse generated by the main body-side timing generating means is provided. And a control voltage obtained by said converting means for controlling an oscillation phase of said voltage-controlled clock generating means so that timing pulses generated by said head-side timing generating means have the same phase. 2. A DC component extracting means for extracting a DC component from a timing pulse generated by the head-side timing generating means, and a main-unit-side power supply voltage using the DC component extracted by the DC component extracting means as a control voltage. A voltage-controlled voltage boosting means for boosting the power supply voltage, and supplies a power supply voltage higher than the body-side power supply voltage to the head side as a head-side power supply voltage by the voltage-controlled voltage boosting means; The head-side timing generation means driven by the power supply voltage generates a timing pulse superimposed on a DC component proportional to the head-side power supply voltage, returns the head to the apparatus main body from the head side, and superimposes the timing pulse. Extracting the DC component by the DC component extracting means to control the voltage-controlled voltage boosting means. I, the signal processing apparatus according to claim 1, wherein the automatically corrected head-side power supply voltage from the voltage-controlled voltage boosting means and supplying to the head side. 3. The apparatus according to claim 2, wherein the head is a camera head including an imaging unit, and the apparatus main body is a camera main unit including a signal processing unit that performs signal processing on an imaging signal supplied from the camera head. The signal processing device according to claim 2. 4. An apparatus main body comprising a main body side signal processing means for performing signal processing in accordance with a timing pulse generated by a main body side timing generation means based on a clock provided by a clock generation means, and a clock supplied from the apparatus main body. A drive control method for a signal processing device, comprising connecting a head provided with a head-side signal processing means for performing signal processing in accordance with a timing pulse generated by the head-side timing generation means based on a cable, The phase of the timing pulse generated by the timing generator is compared with the phase of the timing pulse generated by the head-side timing generator, and the phase of the clock supplied to the head-side timing generator is controlled in accordance with the phase comparison result. The main body side timing generation means A signal processing apparatus for controlling the phase of a clock supplied to the head-side timing generator so that the generated timing pulse and the timing pulse generated by the head-side timing generator have the same phase. Control method. 5. A head-side power supply voltage obtained by extracting a direct-current component from a timing pulse generated by the head-side timing generating means and boosting a main-unit power supply voltage according to the extracted direct-current component from the apparatus main body side. The head-side timing generation means, which is supplied to the head side and is driven by the head-side power supply voltage, generates a timing pulse superimposed on a DC component proportional to the head-side power supply voltage, and from the head side, the apparatus body 5. The drive control method for a signal processing device according to claim 4, wherein a DC component on which the timing pulse is superimposed is extracted, and a head side power supply voltage automatically corrected is supplied to the head side.