JP2657125B2 - Imaging system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup system for displaying images obtained from a plurality of image pickup devices on a single reproduction screen.

[0002]

2. Description of the Related Art In a surveillance system or the like using a plurality of television cameras, video signals from the television cameras can be simultaneously reproduced. As such a method of displaying a plurality of playback screens, a method of displaying images captured by each television camera on a plurality of television monitors, a method of displaying each image on one television monitor in a time-division manner, or There is a method of dividing the screen of the television monitor into a plurality of pieces and displaying the screen. In a general surveillance system, it is desired to obtain a plurality of playback screens, but a high resolution is not particularly required in many cases. Therefore, a method of dividing and displaying a plurality of playback screens on a single TV monitor tends to be adopted. It is in.

FIG. 6 is a block diagram showing a configuration of an imaging system for displaying a plurality of reproduction screens on one television monitor. Here, a case is shown in which four reproduction screens are divided and displayed on the television monitor 2 using four television cameras 1a to 1d. Each of the television cameras 1a to 1d is connected in parallel to the main controller 3, and each of the television cameras 1a to 1d
To 1d are input to the main controller 3. This main controller 3
Comprises a synchronizing signal generation circuit 4, a screen control circuit 5, and a field memory 6, synchronizes the operation of each of the television cameras 1a to 1d with a predetermined timing, and synthesizes each of the video signals Ya to Yd to generate four signals. A video signal Ym for splitting and displaying a video on the same screen is created and supplied to the television monitor 2.

[0004] The synchronizing signal generation circuit 4
a to 1d to supply a synchronization signal SY to each of the television cameras 1a.
-1d are matched. On the other hand, the screen control circuit 5 reduces the video signals Ya to Yd obtained from each of the television cameras 1a to 1d to で each in the horizontal scanning period and the vertical scanning period, and temporarily stores the video information corresponding to the four videos in the field. The video information is read out from the field memory 6 in a predetermined order while being stored in the memory 6 to generate a video signal Ym. That is, the video signals Ya to Yd
In the horizontal scanning period and the vertical scanning period, data is thinned out every other pixel and stored in the field memory 6, and video information corresponding to the video from each of the television cameras 1a to 1d is １ ／ of the horizontal scanning period. Each time, every half period of the vertical scanning period, the video signal Ym is obtained. For example, when a screen is displayed in four divided areas A to D as shown in FIG. 7, in the first half period of the vertical scanning, the image corresponding to the video signal Ya in the first half period of the horizontal scanning. The information is read, and the video information corresponding to the video signal Yb is read in the latter half period. And the latter half of vertical scanning 1 /
In the second period, the video information corresponding to the video signal Yc is read out during the first half of the horizontal scanning, and the video information corresponding to the video signal Yd is read out during the second half of the horizontal scanning. Create Ym. Therefore, images from the television cameras 1a to 1d are simultaneously displayed in the divided areas A to D on the playback screen.

By the way, when the imaging system as described above is configured, a field memory 6 capable of storing video information of at least four screens, and video information is read from the field memory 6 while video information is stored in the field memory 6. Therefore, a large-scale circuit configuration such as the screen control circuit 5 for performing the synthesis is required, which leads to an increase in cost. Therefore, as a method of reducing the cost of an imaging system for obtaining a plurality of images, the present applicant has disclosed Japanese Patent Application No. Hei.
No. has been proposed.

FIG. 8 is a block diagram showing a configuration of an imaging system in which connections are simplified. Here, a case in which four television cameras are used as in FIG. 7 will be described. However, for simplification of the drawing, some of the cameras having the same configuration are omitted from the drawing. A television camera 10 serving as a reference for the operation of each television camera includes a synchronization signal generation circuit 11 that generates a synchronization signal SY and an imaging unit 12 that operates upon receiving the synchronization signal SY, and outputs a video signal Y0 according to the synchronization signal SY. I do. The synchronization signal generation circuit 11 is composed of a counter and a decoder. The synchronization signal generation circuit 11 generates a horizontal scanning cycle and a synchronization signal SY including each component of the horizontal scanning cycle by dividing a clock of a fixed cycle, and supplies the synchronization signal SY to the imaging unit 12. In the imaging unit 12, the scanning timing of the imaging device is set in accordance with each component of the synchronization signal SY, the output of the imaging device is subjected to a predetermined format process, and is output as a video signal Y0. The number of pixels of the imaging area of the imaging element mounted on the imaging unit 12 is set to の of the normal number, that is, the number of horizontal and vertical pixels is set to 、. 1 /
It is configured to be completed in two periods.

On the other hand, three television cameras 20a to 20c connected in series to the output of the television camera 10
A synchronization separation circuit 21 for detecting a synchronization signal SY from an input video signal Y0, a timing change circuit 22 for changing the timing of the separated synchronization signal SY to a timing unique to each of the television cameras 20a to 20c, and a synchronization whose timing has been changed. The imaging unit 23 that operates in response to the signals SYa to SYc and the video signal Y output from the imaging unit 23
a signal combining circuit 2 for sequentially adding a to Yc to the video signal Y0
4 and by synchronizing with the TV camera 10,
The video signals Ya to Yc synchronized with the video signal Y0 are output. Since the video signals Ya to Yc output from the imaging unit 23 of each of the television cameras 20a to 20c have the same horizontal scanning timing and vertical scanning timing, the timing of each video signal Ya to Yc should be changed. It can be synthesized without any. Each imaging unit 23
As in the image pickup unit 12 of the television camera 10, an image pickup device in which the number of pixels in the image pickup area is 1/4 is used, and each image in which a video component is superimposed in a half of the horizontal scanning period and the vertical scanning period is used. The signals Ya to Yc are output.
During the period in which the video component is superimposed, the timing change circuit 22
Is set so as not to overlap each of the television cameras 20a to 20c. Accordingly, by sequentially adding each of the video signals Ya to Yc to the video signal Y0 by the combining circuit 24, the four television cameras 10, 20a to 4a, as obtained from the main controller 3 of the imaging system in FIG.
A video signal Ym for dividing and displaying the video from 20c is obtained, and this video signal Ym is supplied to the monitor 2.

[0008]

In the above-described image pickup system, power is supplied from the power supply 30 to each of the television cameras 20a to 20c, but a plurality of television cameras 20a to 20c are connected. Power line in addition to the communication line
There is a problem that the connection of 0, 20a to 20c becomes complicated. In particular, when the number of connected television cameras increases, both the communication line and the power line become longer, and the effect of cost reduction by simplifying the circuit configuration of each of the television cameras 20a to 20c cannot be fully utilized.

Although the power lines can be reduced by incorporating a power source in each of the television cameras 20a to 20c, the circuit scale of each of the television cameras 20a to 20c becomes large and the cost of the television cameras 20a to 20c itself becomes low. Because it increases, it is not preferable to adopt it for an imaging system using a plurality of television cameras. Accordingly, an object of the present invention is to simplify connection of a plurality of television cameras and reduce the cost of an imaging system.

[0010]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and a feature of the present invention is that a plurality of imaging devices are provided on a transmission line through which a video signal and a synchronization signal are transmitted. Are connected in parallel, and by synthesizing the video signal output from each imaging device on the transmission line,
In an imaging system for dividing and displaying an image obtained by each imaging device on a playback screen, a power supply unit for applying a predetermined voltage to the transmission line via an impedance conversion circuit, and a television format synchronization signal to the transmission line. And a synchronizing signal supply means for supplying power from the transmission line via a ripple elimination circuit, and setting the scanning timing of the image sensor by obtaining the synchronization signal from the transmission line. The purpose is to transmit a video signal obtained from an image sensor to the transmission line.

[0011]

According to the present invention, the DC voltage for supplying power to each imaging device is applied to the transmission line via the impedance conversion circuit, whereby the impedance of the transmission line with respect to the high frequency component is kept high. Thus, a DC voltage, a high-frequency video signal and a synchronization signal can be superimposed on the transmission line. Therefore, a single transmission line supplies power and a synchronization signal to a plurality of imaging devices.

[0012]

FIG. 1 is a block diagram showing the configuration of an imaging system according to the present invention. Here, a case will be described in which four television cameras are connected to obtain a four-divided video, but for simplification of the drawings, some of the cameras having the same configuration are omitted from the drawings. The television camera 40 serving as a reference for operation includes a synchronization signal generation circuit 41 for generating a synchronization signal SY, a synchronization signal S
An imaging unit 42 that operates in response to Y, a ripple removal circuit 43 that removes a high-frequency component of the transmission line L to obtain a DC voltage VD, and a regulator circuit 44 that supplies power to each unit of the imaging unit 42. The video signal Y0 including the output is output. The synchronization signal SY has components of a horizontal scanning cycle and a vertical scanning cycle, and determines horizontal and vertical scanning timings of the image sensor of the image pickup unit 42.
The video signal Y0 output from the imaging unit 42 has a format according to the synchronization signal SY, and is output to the transmission line L via the capacitor 45 that blocks a DC component. In addition to the video signal Y0, a DC voltage VD sufficient to drive the television camera 40 is superimposed on the transmission line L. The DC voltage VD is extracted by the ripple removing circuit 43 and supplied to the regulator circuit 44. . The regulator circuit 44 converts the DC voltage VD supplied from the ripple elimination circuit 43 into various voltages necessary for each unit, and supplies each voltage at a predetermined level to the imaging unit 42 and the synchronization signal generation circuit 41.

On the other hand, three television cameras 50a to 50a-5 connected in parallel to the transmission line L to the television camera 40.
0c denotes an imaging unit 51 that operates upon receiving a synchronization signal SY from the transmission line L, and a ripple removal circuit 5 that removes high-frequency components of the transmission line L to obtain a DC voltage VD.
2 and a regulator circuit 53 for supplying power to each section of the imaging unit 42, and outputs video signals Ya to Yc synchronized with the video signal Y0 to the transmission line L. here,
The ripple removing circuit 52 and the regulator circuit 53 are the same as those of the television camera 40, and the DC voltage VD extracted from the transmission line L by the ripple removing circuit 52.
Is input to the regulator circuit 53, and a voltage of a predetermined level is supplied from the regulator circuit 53 to the imaging unit 51. Further, a video signal Y0 is input to the imaging unit 51 from the transmission line L via a capacitor 55 that cuts off a DC component, and the scanning timing of the imaging device is set according to a synchronization signal SY separated from the video signal Y0. . Then, the video signals Ya to Yc output from the imaging unit 51 are output to the transmission line L via the capacitor 55 again. Therefore, the video signal Y0 obtained by each of the television cameras 40, 50a to 50c is transmitted to the transmission line L.
Ya to Yc are added, and the video signal Ym including the synchronization signal SY is superimposed.

A power supply unit 60 for supplying power to each of the television cameras 40 and 50a to 50c by superimposing a DC voltage on the transmission line L includes, for example, a power supply circuit 61 for obtaining a constant DC voltage from a general AC power supply and a transmission circuit 61. The signal processing circuit 63 includes an impedance conversion circuit 62 that superimposes the DC voltage VD from the power supply circuit 61 on the line L, and further receives a video signal Ym of the transmission line L. The impedance conversion circuit 62 is connected to each of the above-described television cameras 4.
0, 50a to 50c, and is configured to superimpose a DC voltage on the transmission line L without lowering the impedance. Then, the signal processing circuit 63 to which the video signal Ym is input from the transmission line L via the capacitor 64 performs signal processing such as level clamp and amplification on the video signal Ym and supplies the video signal Ym to the television monitor 2.

FIG. 2 is a block diagram showing the configuration of the imaging unit 51 of each of the television cameras 50a to 50c. In this figure, the imaging unit 51 of the television camera 50a is shown as an example, but the circuit configuration of the imaging unit 51 is the same for each of the television cameras 50a to 50c. For example, as shown in FIG. 3, the video signal Y0 input from the transmission line L has a video component superimposed only in the first half of each vertical scanning period (1V). Is input to The synchronization separation circuit 71 inputs the video signal Y0, which has only the synchronization component by removing the video component of the video signal Y0, that is, the synchronization signal SY, to the timing generation circuit 72. The removal of the video component in the sync separation circuit 71 is performed, for example, by setting the reference level of the video signal Y0 to V1.
Then, the video signal Y0 is compared with the level V2 lower than the peak value of the timing pulse of the synchronization signal SY, and the comparison result is output as the synchronization signal SY. The timing generation circuit 72 separates a horizontal component and a vertical component from a synchronization signal SY including each component of a horizontal scanning period and a vertical scanning period, and outputs a timing signal of a horizontal scanning period such as a horizontal synchronization signal and a vertical synchronization signal. The timing signal of the vertical scanning cycle is input to the timing change circuit 73. The timing change circuit 73 includes the CCD solid-state imaging device 7.
4 to control the output timing of the video signals Y0, Ya to Ya from the respective television cameras 40, 50a to 50c.
This is to prevent the video components of Yc from overlapping each other, and the scanning timing of the image sensor 74 in each of the television cameras 50a to 50c is 1 / H in each of horizontal scanning and vertical scanning.
It is set to be different every two cycles. TV camera 50a
Then, the synchronization signal SYa whose vertical scanning timing is delayed by 周期 cycle is input to the drive clock generation circuit 75. Therefore, the driving clock generation circuit 75
4 is driven at a timing delayed by １ ／ vertical scanning period, and the image sensor 74 outputs a video component in the latter half of the vertical scanning period. The output of the image pickup device 74 is subjected to signal processing such as sample hold and level correction in a signal processing circuit 76 operating in accordance with the synchronization signal SY, and then, as a video signal Ya as shown in FIG. Is entered. Then, the video signal Ym in which the video component is superimposed in the first half of the vertical scanning period is added to the video signal Ya in which the video component is superimposed in the second half, so that the video signal Ym is output to the transmission line L. Here, the video signal Ym has video components evenly superimposed during the vertical scanning period.
In the horizontal scanning period, the video component is superimposed only in the first half period. Therefore, the latter half of the horizontal scanning period in which the video components are not superimposed is a period in which the video components of the video signals Yb and Yc from the television cameras 50b and 50c connected to the next stage of the television camera 50a are superimposed. Therefore, the video signal Ym in which the video signals Ya to Yc are sequentially superimposed on the video signal Y0 in each of the television cameras 50a to 50c is divided into a horizontal scanning period and a vertical scanning period, and the television cameras 40, 50a to 50c are respectively divided into the respective periods. 50
The video components of video signals Y0 and Ya to Yc from “c” are superimposed, and a four-divided video is displayed on the screen of the television monitor 2.

FIG. 4 shows the impedance conversion circuits 54 and 6
2 is a circuit diagram illustrating an example of a circuit configuration of FIG. Power supply circuit 61
A capacitor C1 and a coil L are connected to an input terminal receiving the DC voltage VD from
1. The emitter of the pnp transistor T1 and the collector of the npn transistor T2 are connected. The resistor R1 has
The base of npn transistor T3, resistor R2 and capacitor C2 are connected, and the base of pnp transistor T1 is connected to the emitter of pnp transistor T4. The base of the pnp transistor T4 is connected to the collector of the npn transistor T3 and the capacitor C3,
The collector is connected to the collector of the pnp transistor T1 and outputs a DC voltage VD. npn transistor T
A resistor R3 is connected to the emitters of N2 and T3, and np
A resistor R4 is connected to the output side of the base of the n-transistor T2, and a resistor R5 and a capacitor C4 are further connected. On the output side, a capacitor C5
And the resistor R6 are connected in series, and high-frequency components on the output side from the connection point of the capacitor C5 and the resistor R6, that is, video signals Y0 and Ya to Yc superimposed on the transmission line L are output. The high-frequency component superimposed on the transmission line L is cut off by the pnp transistors T1 and T4, so that the impedance on the output side is low for the low-frequency component and high for the high-frequency component, and is used for the power source. DC voltage VD and video signals Y0, Ya to Yc can be superimposed on the same transmission line L.

FIG. 5 is a circuit diagram showing an example of the circuit configuration of the ripple elimination circuits 43 and 52. Video signal Y0, Ya
A resistor R11, npn transistors T11 and T1
2, the base of the npn transistor T11 is connected to the emitter of the npn transistor T12, and the DC voltage VD is output from the emitter of the npn transistor T11. npn transistor T11
Capacitors C11 and C12 are respectively connected between the base and the emitter of T12, and a capacitor C13 is connected between the emitter of the npn transistor T11 and the base of the npn transistor T12. And
The bases of the resistor R11 and the npn transistor T12 are grounded via the resistor R12. Therefore, the high frequency component from the input side is cut off by the npn transistors T11 and T12, and the DC voltage VD is output to the output side. Also, since the input impedance is low for low-frequency components and high for high-frequency components, even when power is consumed on the output side, the high-frequency components on the input side are not affected. The video signals Y0, Ya to Yc of the line L are protected.

According to the above configuration, since the impedance of the transmission line L is low with respect to the low-frequency component and high with respect to the high-frequency component, each of the transmission lines L from which the video signals Y0, Ya to Yc are output is provided. TV cameras 40, 50a-5
Even if the DC voltage VD for operating 0c is superimposed, the DC voltage VD and the video signals Y0, Ya to Yc are transmitted by the common transmission line L without affecting the video signals Y0, Ya to Yc. It becomes possible to do.

In this embodiment, the synchronizing signal SY and the DC voltage VD are transmitted to each of the television cameras 50a to 50c.
In this case, the synchronizing signal SY is supplied from each direction from the same direction as the DC voltage VD.
It is also possible to configure to supply to 0a to 50c. In that case, a synchronization signal generation circuit can be provided in the power supply unit 60, and the imaging unit 51 of each of the television cameras 50a to 50c receives the synchronization signal from the power supply side. Further, the signal processing circuit 63 for extracting the video signal Ym from the transmission line L and inputting the video signal Ym to the monitor 2 does not need to be provided in the power supply unit 60, and may be provided in any part of the transmission line L.

[0020]

According to the present invention, since video signals from a plurality of television cameras and a DC voltage supplied to each television camera can be transmitted through a common transmission line, connection of the plurality of television cameras is simplified. The cost of an imaging system using a plurality of television cameras can be reduced. Also, since there is no need to provide a power source for each television camera, it is easy to reduce the size and weight, and the cost of each television camera itself can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an imaging system according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of an imaging unit.

FIG. 3 is a waveform diagram of a video signal.

FIG. 4 is a circuit diagram of an impedance separation circuit.

FIG. 5 is a circuit diagram of a ripple elimination circuit.

FIG. 6 is a block diagram showing a configuration of a conventional system.

FIG. 7 is a schematic diagram showing a configuration of a playback screen.

FIG. 8 is a block diagram illustrating a configuration of an imaging system that synchronizes each television camera.

[Explanation of symbols]

 1a to 1d, TV camera 2 TV monitor 3 Main controller 10, 20a to 20c TV camera 30 Power supply circuit 40, 50a to 50c TV camera 41 Synchronous signal generation circuit 42, 51 Imaging unit 43, 52 Ripple removal circuit 44, 53 Regulator circuit 54, 62 Impedance conversion circuit 61 Power supply circuit 63 Signal processing circuit 71 Synchronization separation circuit 72 Timing generation circuit 73 Timing change circuit 74 CCD solid-state imaging device 75 Drive clock generation circuit 76 Signal processing circuit L Transmission line

Claims (2)

(57) [Claims] 1. A video signal and a synchronizing signal are transmitted in a transmission line, a plurality of imaging devices are connected in parallel, and video signals output from each imaging device are synthesized on the transmission line, so that a reproduction screen is displayed. In an imaging system for dividing and displaying a video obtained by each imaging device, a plurality of imaging devices,
A transmission line in which a plurality of imaging devices are connected in series, power supply means for applying a predetermined voltage to the transmission line via an impedance conversion circuit, and synchronization signal supply means for applying a television format synchronization signal to the transmission line Wherein the plurality of imaging devices obtain power from the transmission line via a ripple elimination circuit , extract the synchronization signal from the transmission line , and
Unique timing set for each imaging device
The scanning timing of the image sensor is set with a delay of
From the image sensor that operates at the set timing.
An imaging system, wherein an obtained video signal is superimposed on the transmission line . 2. A method according to claim 1, wherein said synchronization signal generating means is provided in one of a plurality of imaging devices connected to said transmission line, and said video signal including said synchronization signal is transmitted from said imaging device to said transmission line. The imaging system according to claim 1.