JPH05328227A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain the solid-state image pickup device connecting to a digital picture processing unit and suitable when digital processing is applied to picture data. CONSTITUTION:A sampled analog video signal corresponding to an object is outputted by a CCD1, a CDS/AGC circuit 2 and a process circuit 3. A CCD driving circuit 6 outputs a CCD driving signal such as a horizontal register transfer clock or the like to the CCD 1. When a video signal is delayed with respect to a horizontal synchronizing signal, a shift register 15 is controlled to delay a phase of a horizontal drive pulse HD and when a video signal is led with respect to the horizontal synchronizing signal, a shift register 16 is controlled to delay the phase of the horizontal synchronizing signal. Thus, the digital picture processing unit resamples the video signal at a correct position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device suitable for image input to a digital image processing device.

[0002]

2. Description of the Related Art Recently, a solid-state image pickup device and a digital image processing device are connected to each other, an image is captured by the solid-state image pickup device, input to the digital image processing device, and the image data is digitally processed. Has become relatively easy. 2 is a block diagram showing an example of a conventional solid-state imaging device, and FIG. 3 is a block diagram showing an example of a digital image processing device connected to the solid-state imaging device.

First, the structure and operation of the conventional solid-state image pickup device shown in FIG. 2 will be described. In FIG. 2, the signal output from the CCD image sensor 1 (hereinafter, CCD 1) is a correlated double sampling / AGC circuit 2 (hereinafter, CD
The video signal is input to the S / AGC circuit 2), the S / N is extracted well, the gain is adjusted, and the signal is output. CDS / A
The output of the GC circuit 2 is input to the process circuit 3, subjected to processing such as setup level adjustment and gamma correction, and output. On the other hand, the synchronizing signal generating circuit 4, the timing generator circuit 5, the CCD driving circuit 6, and the clock generator 7 supply various signals for operating the CCD 1, the CDS / AGC circuit 2, and the process circuit 3 described above.

That is, the clock generator 7 supplies a clock to the synchronizing signal generating circuit 4 and the timing generator circuit 5. The synchronization signal generation circuit 4 outputs a horizontal synchronization signal and a vertical synchronization signal to the outside, and supplies a horizontal drive pulse (HD) and a vertical drive pulse (VD) to the timing generator circuit 5 and a blanking pulse to the process circuit 3. .. Then, the timing generator circuit 5 generates a CCD drive pulse by the clock input from the clock generator 7 and the horizontal drive pulse and the vertical drive pulse input from the synchronization signal generation circuit 4, and supplies the CCD drive pulse to the CCD drive circuit 6. The CCD drive circuit 6 generates a CCD drive signal composed of a vertical register transfer clock, a horizontal register transfer clock, an output reset clock, etc. by this pulse and inputs it to the CCD 1 to drive the CCD 1. Further, the timing generator circuit 5 supplies the CDS drive pulse to the CDS / AGC circuit 2 and also supplies the clamp pulse to the CDS / AGC circuit 2.
And to the process circuit 3.

Next, the configuration and operation of the digital image processing apparatus shown in FIG. 3 will be described. In FIG. 3, A / D
The video signal output from the process circuit 3 in FIG. 2 is input to the converter 8. The video signal input to the A / D converter 8 undergoes a pedestal clamp and is A / D converted,
The gradation characteristics are converted by being input to the look-up table 9 (hereinafter, LUT 9). Then, the converted data is written in the video memory 10, and the video signal read from the video memory 10 is D / A converted by the D / A converter 11 and output. The output video signal is displayed on a monitor or the like. By the way, in many cases, a digital image processing apparatus is designed to input a standard video signal for versatility as an input signal.

On the other hand, the horizontal synchronizing signal and the vertical synchronizing signal output from the synchronizing signal generating circuit 4 in FIG. 2 are input to the synchronizing coupling circuit 12, and the synchronizing coupling circuit 12 supplies a clock to the video timing controller 13. Then, the video timing controller 13 supplies to the video memory 10 a memory control signal indicating at which address of the video memory 10 the signal output from the LUT 9 should be written.
Image data processing is performed by a host computer (not shown), and various signals output from the host computer are supplied to the video memory 10 and the video timing controller 13 by the personal computer bus via the bus interface circuit 14, and The video signal read from the video memory 10 is taken into the host computer.

In this way, the solid-state image pickup device shown in FIG. 2 and the digital image processing device shown in FIG. 3 are connected, an image is captured by the solid-state image pickup device, input to the digital image processing device, and the image data is digitally converted. In the case of performing the processing, the applicant of the present invention uses a sample value analog signal, which is a stepwise signal in which adjacent pixel information is not mixed, as a video signal to be input to the digital image processing apparatus, and thus the higher value is obtained. Focusing on the ability to obtain high-quality images, first, Japanese Patent Application No. 3-313604 and Japanese Patent Application No. 4-4
No. 2068 proposed a solid-state imaging device configured to output a sampled analog signal. Therefore, in the solid-state imaging device shown in FIG.
Does not perform processing such as interpolation processing or filtering that causes mixing of pixel information, but only performs processing such as white balance correction or black balance correction.

[0008]

When a sampled analog signal in which adjacent pixel information is not mixed as described above is input to the digital image processing apparatus, the input signal is corrected by the A / D converter 8. It is necessary to resample at the timing, ie at the correct position of the sampled analog signal, which is a stepped signal. As described above, in the digital image processing device, since it is designed to input only the standard video signal and the synchronizing signal as the input signal, it is usually impossible to input the clock from the solid-state imaging device. When the solid-state imaging device configured to output the sample value analog signal as shown in FIG. 2 is connected to the digital image processing device as shown in FIG. 3, the phase for re-sampling the sample value analog signal at the correct position is obtained. Adjustment means are needed.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention relates to a CCD image sensor for photoelectrically converting a subject image and outputting the same, and an output signal of the CCD image sensor is correlated double. Along with sampling
A correlated double sampling / AGC circuit that adjusts and outputs the gain; and a process circuit that processes the output signal of the correlated double sampling / AGC circuit without mixing adjacent pixel information and outputs a sampled value analog signal. A clock is input, a horizontal synchronizing signal, a vertical synchronizing signal, a horizontal driving pulse, and a vertical driving pulse are output, and a synchronizing signal generating circuit that outputs a blanking pulse to the process circuit, the clock, the horizontal driving pulse, and the A timing generator circuit that receives a vertical drive pulse, outputs a first drive pulse and a clamp pulse to the correlated double sampling / AGC circuit, outputs a clamp pulse to the process circuit, and outputs a second drive pulse. And the second drive pulse is input, the C In a solid-state imaging device having a CCD drive circuit for outputting a drive signal including a horizontal register transfer clock to a D image sensor, the phase of the horizontal drive pulse output from the synchronization signal generation circuit is set to an integer of the horizontal register transfer clock. A first shift register for shifting by a unit of a multiple or an integer, and a phase of the horizontal synchronizing signal output from the synchronizing signal generating circuit by an integer multiple of the horizontal register transfer clock or a unit of an integer. A second shift register for
A solid-state imaging device comprising: a controller for controlling the first and second shift registers.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state image pickup device of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the solid-state imaging device of the present invention. In FIG. 1, the same parts as those in FIG. 2 are designated by the same reference numerals.

In FIG. 1, CCD 1 photoelectrically converts a subject image, and the signal output from CCD 1 is CDS / AG.
The video signal is input to the C circuit 2, the S / N is extracted well, and the gain is adjusted and output. The output of the CDS / AGC circuit 2 is input to the process circuit 3 and
Does not perform processing such as interpolation processing or filtering that causes mixing of pixel information, only processing such as white balance correction or black balance correction, and outputs a sample value analog signal in which adjacent pixel information is not mixed.

On the other hand, the clock generator 7 supplies a clock to the synchronizing signal generating circuit 4 and the timing generator circuit 5. The sync signal generation circuit 4 outputs a horizontal sync signal and a vertical sync signal to the outside (digital image processing device), and also outputs a horizontal drive pulse (HD) and a vertical drive pulse (VD). Further, the synchronization signal generation circuit 4 supplies a blanking pulse to the process circuit 3.
The frequency of the clock output from the clock generator 7 is several times the sampling frequency of the sampled analog signal output from the process circuit 3. here,
The vertical drive pulse output from the synchronization signal generation circuit 4 is input to the timing generator circuit 5, and the horizontal drive pulse is input to the shift register 15 newly added according to the present invention and then input to the timing generator circuit 5. It Further, the horizontal synchronizing signal output from the synchronizing signal generating circuit 4 is input to the shift register 16 newly added according to the present invention and then output to the outside.

Then, the timing generator circuit 5 generates a CCD drive pulse by the clock input from the clock generator 7, the horizontal drive pulse input from the shift register 15, and the vertical drive pulse input from the synchronizing signal generation circuit 4. , To the CCD drive circuit 6. The CCD drive circuit 6 generates a CCD drive signal composed of a vertical register transfer clock, a horizontal register transfer clock, an output reset clock, etc. by this pulse and inputs it to the CCD 1 to drive the CCD 1. Further, the timing generator circuit 5 sends the CDS drive pulse to the CD
The clamp pulse is supplied to the CDS / AGC circuit 2 and the process circuit 3 while being supplied to the S / AGC circuit 2.

A clock is input from the clock generator 7 to the shift registers 15 and 16 described above. Further, digital data output from a host computer (not shown) in the digital image processing apparatus shown in FIG. 3 is input to the controller 17 newly added according to the present invention, and control signals are output to the shift registers 15 and 16. ..

By connecting the solid-state image pickup device of the present invention configured as described above and the digital image processing device shown in FIG. 3, an image is captured by the solid-state image pickup device of the present invention and input to the digital image processing device to input the image. When the data is digitally processed, the host computer obtains the shift of the resampling phase by the A / D converter 8 from the distortion of the captured image. For the purpose of correcting this shift, the digital image processing apparatus is connected to the digital image processing apparatus by a communication means such as a mouse, as shown in FIG.
Digital data is supplied as control data to the inside controller 17. Then, when delaying the video signal with respect to the horizontal synchronizing signal, the controller 17 controls the shift register 15 to delay the phase of the horizontal drive pulse output from the synchronizing signal generating circuit 4, and conversely the horizontal synchronizing pulse. When advancing the video signal with respect to the signal, the phase of the horizontal synchronizing signal output from the synchronizing signal generating circuit 4 to the outside is delayed by controlling the cyst register 16.

Further, when fine adjustment is not required when adjusting the phase of the video signal by the shift registers 15 and 16, fine adjustment is required by shifting in units of integer multiples of the horizontal register transfer clock input to the CCD 1. In that case,
The horizontal register transfer clock input to the CCD 1 is shifted by an integer unit. As a result, the sampled analog signal output from the process circuit 3 is resampled at the correct position by the digital image processing device. Although it is possible to provide such a phase adjusting means in the digital image processing device, as described above, the digital image processing device is designed to input a standard video signal as an input signal. It is meaningful to provide the solid-state imaging device with the phase adjusting means.

[0017]

As described in detail above, since the solid-state image pickup device of the present invention outputs image information as a sampled analog signal, it can be connected to a digital image processing device to perform digital processing on image data. Suitable for use,
Further, a first shift register that shifts the phase of the horizontal drive pulse output from the synchronization signal generation circuit by an integral multiple of the horizontal register transfer clock input to the CCD image sensor or by a unit of an integer, and a synchronization signal generation The horizontal shift signal output from the circuit is provided with a second shift register that shifts the phase of the horizontal register transfer clock input to the CCD image sensor by an integral multiple or a unit of an integer. It has a feature that an analog signal can be resampled at a correct position by a digital image processing device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a solid-state imaging device of the present invention.

FIG. 2 is a block diagram showing a conventional solid-state imaging device.

FIG. 3 is a block diagram showing a digital image processing device connected to a solid-state imaging device.

[Explanation of symbols]

 1 CCD image sensor 2 Correlated double sampling (CDS) / AGC circuit 3 Process circuit 4 Synchronization signal generation circuit 5 Timing generator circuit 6 CCD drive circuit 7 Clock generator 15, 16 Shift register 17 Controller

Claims (1)

[Claims] 1. A CCD image sensor for photoelectrically converting and outputting a subject image; a correlated double sampling / AGC circuit for performing correlated double sampling of an output signal of the CCD image sensor and adjusting and outputting the gain; A process circuit that processes the output signal of the correlated double sampling / AGC circuit without mixing adjacent pixel information and outputs a sample value analog signal; a clock is input; a horizontal synchronizing signal, a vertical synchronizing signal, and a horizontal drive pulse And a synchronizing signal generation circuit for outputting a vertical drive pulse and a blanking pulse to the process circuit, the clock, the horizontal drive pulse and the vertical drive pulse are input, and the correlated double sampling /
A timing generator circuit that outputs a first drive pulse and a clamp pulse to the AGC circuit, outputs a clamp pulse to the process circuit, and outputs a second drive pulse, and inputs the second drive pulse. In a solid-state imaging device having a CCD drive circuit for outputting a drive signal including a horizontal register transfer clock to a CCD image sensor, the phase of the horizontal drive pulse output from the synchronization signal generation circuit is an integer of the horizontal register transfer clock. A first shift register that shifts by a unit of a multiple or an integer, and a phase of the horizontal synchronizing signal output from the synchronizing signal generation circuit by an integer multiple of the horizontal register transfer clock or a unit of an integer A second shift register, and the first and second shift registers A solid-state imaging device comprising: a controller for controlling.