JPS6269774A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To remove a longitudinal stripe and the beats which reduces the picture quality by separating and providing a signal processing part and a synchronizing signal generating device from a solid-state image pickup element, a driving circuit, etc., and using a shift register as a frequency dividing circuit. CONSTITUTION:A solid-state image pickup element 1, a driving circuit 2, a driving pulse generating device 3, a voltage control transmitting device 6, a shift register part 4, etc., are separated as an A block and a signal processing part 8 and a synchronizing signal generating device 10 are separated as a B block. Thus, the influence in which the count-down noise by the counter in the internal part of a synchronizing signal generating device 8 at the B block side gives to an element 1, comes to be made smaller, and the beat of the clock of the oscillating frequency of the generating device 10 and an output CK of the oscillating device 6 comes to be also smaller. By using the shift register part 4 as the frequency dividing circuit, the longitudinal stripe pattern count-down noise does not occur. Thus, by separating to the A and B blocks and using the register part 4 as the frequency dividing circuit, the longitudinal stripe and the beat can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a solid-state imaging device that can be used in video cameras and the like.

BACKGROUND OF THE INVENTION In recent years, solid-state imaging devices have been actively researched and developed as new imaging devices, and are rapidly reaching the stage of practical use.

Along with this, the demand for higher resolution or the number of pixels depending on the application is increasing, and a drive circuit that can handle any number of pixels is required. PLL circuits are commonly used to achieve this goal.

The configuration of a conventional solid-state imaging device will be described below with reference to FIG.

1 is a solid-state image sensor, 2 is a photoelectric conversion portion of the solid-state image sensor, and a vertical transfer pulse φV for reading and vertically transferring the signal charge, a horizontal transfer pulse φH for horizontally transferring the signal charge, and a signal. Reset pulse φR to reset
A drive circuit 11 supplies drive pulses Pv and PH2PR that are input to the drive circuit 2, and a drive pulse generator that supplies pulses Ps necessary for the signal processing section 8a, which generates a carrier frequency 94 times higher. This is a crystal terminal that oscillates.

Here, a case where a drive pulse generator 3 as shown in FIG. 3 is used as the drive pulse generator 10 will be described.

In FIG. 3, 21 is a phase comparator, 22 is a filter, 23 is a voltage controlled oscillator, 24 is a frequency divider, 25 is a frequency divider decoder that has both the functions of a frequency divider and a decoder,
26 is an original oscillator with four times the carrier frequency.

Regarding the drive pulse generator 3 configured as above,
The operation will be explained below.

The phase comparator 21 includes a quadruple carrier frequency oscillator 26.
The horizontal synchronizing pulse HD divided by the horizontal period 1 and the divided output HD' from the frequency divider 24 are input, and a pulse indicating the phase difference between the two pulses is output. Next, this pulse is input to the low-pass filter 22, where it is converted into a DC voltage according to the phase difference between HD and HD', and the voltage controlled oscillator 2
3 is input.

Next, a clock pulse CK having a frequency corresponding to the DC voltage value is generated. This clock pulse is counted down to a horizontal period by a frequency divider 24 to generate HD'. It has a more advanced PLL configuration as described above.

Furthermore, the clock pulse CK is frequency-divided into 1/2 to generate pulses Pv, pH, and PR for driving the solid-state image sensor.

Further, the branch decoder 25 sends HD to the phase comparator 21 as a first output, and sends a signal processing pulse P as a second output.
generate s.

Problems to be Solved by the Invention However, with the above configuration, a counter composed of flip-flops is used in the frequency divider 242 of the drive pulse generator 3 and the frequency divider decoder. A pulsed current flows when the state of a lip flop changes, and especially when multiple 7 lip flops change state at the same time, a large amount of pulse current flows.This pulsed current mixes into the video signal via the power supply, ground, etc. Then, a fixed pattern of vertical stripes appears on the monitor screen. Further, the output 4fc of the original oscillator 26 and the clock CK, which is the output of the voltage controlled oscillator 23, had a point (9) at which a beat was generated.

Means for Solving the Problems In order to solve the above problems, the solid-state imaging device of the present invention first uses a shift register as the frequency divider of the drive pulse generator. Second, the solid-state image sensor, drive circuit, drive pulse generator, voltage-controlled oscillator, low-pass filter, phase comparator, and shift register section are separated into a signal processing section and a synchronization signal generator. .

Effect: With this configuration, the noise caused by the countdown disappears, and the beats of 4fo and the clock also disappear.

EXAMPLE An example of the present invention will be described below with reference to FIGS. 1 and 3. FIG. 1 is a block diagram showing the configuration of a solid-state imaging device according to an embodiment of the present invention.

In Figure 1, 1 is a solid-state image sensor, 2 is a photoelectric conversion part of the solid-state image sensor 1, a vertical transfer pulse φ■ for reading and vertically transferring signal charges, and a horizontal transfer pulse for horizontally transferring signal charges. This is a drive circuit that supplies the transfer pulse φH and a reset pulse that resets the signal to the solid-state image sensor. 3 is horizontal synchronization signal HD and vertical synchronization signal VD
A clock CK having the same frequency as the sampling frequency that drives the scanning pulses p, ph, pR, which are input to the drive circuit 2 by inputting the voltage-controlled oscillation output CK having a frequency twice the sampling frequency, and the shift register section 4. ' and supplying the pulse Ps' necessary for signal processing,
This is a driving pulse generator.

A shift register 4 divides the output CK' of the drive pulse generator 3 by a horizontal period of 1. 5 is shift register section 4
This is a phase comparator that compares the phase of the output HD' and the horizontal synchronization signal (1D). 5 is a low-pass filter that receives the output signal of the phase comparator 7 as an input.

Here, it is converted into a DC voltage according to the phase difference between HD and HD'. Reference numeral 6 denotes a voltage controlled oscillator that generates a clock pulse OK having a frequency corresponding to the output of the low-pass filter 6, that is, the DC voltage. This clock pulse is frequency-divided by half inside the drive pulse generator 3 to become a clock CK' having the same frequency as the sampling frequency. 1Q is 4
This is a synchronizing signal generator that includes a crystal oscillator of twice the size of an IC and supplies pulses Ps to the drive pulse generator 3 and the signal processing section 8.

8 is a signal processing section that processes the output of the solid-state image sensor 1 to produce a color television signal, and 9 is its output terminal.

The above is the configuration of this embodiment.

With this configuration, countdown noise does not occur because the first circuit is configured as a shift register as a frequency divider. Second, the solid-state image sensor 1, drive circuit 2, drive pulse generator 3, phase comparator 7, low pass filter 5, voltage controlled oscillator 6, and shift register section 4
As an iA block, a signal processing unit 8 and a synchronization signal generator 1
If o and output terminal 9 are B block, A block and B
By dividing into blocks, the influence of countdown noise caused by the counter inside the synchronization signal generator 8 on the B block side on the solid-state image sensor 1 is reduced.

Furthermore, the number of beats between the oscillation frequency clock of the synchronizing signal generator 10 and the output CK of the voltage controlled oscillator 6 is reduced.

Specifically, the A block and B block are made on separate P plates to prevent vertical stripes and beats.

Effects of the Invention As described above, according to the solid-state imaging device of the present invention, vertical stripes and beats that significantly degrade image quality can be removed.
Its practical effects are enormous.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional solid-state imaging device, and FIG. 3 shows an example of the configuration of a drive pulse generator. FIG. 1... Solid-state image sensor, 2... Drive circuit, 3... Drive pulse generator, 4...
・Shift register section, 5...Low pass filter, 6...Voltage controlled oscillator, 7...Phase comparator, 8...Signal processing section, 9.・・・・・・
Output terminal, 10...Synchronization signal generator.

Claims (2)

[Claims] (1) A solid-state image sensor, a drive circuit that supplies scanning pulses to the solid-state image sensor, a phase comparator whose first input is a horizontal synchronizing signal and whose second input is the output of a shift register, and the phase comparison device. a low-pass filter that receives an output signal of the oscillator as an input, a voltage-controlled oscillator that receives the output of the low-pass filter as an input, a drive pulse generator that receives an output signal of the voltage-controlled oscillator as an input, and a crystal oscillator, a synchronizing signal generator configured to input the output of the driving pulse oscillator to the shift register and supplying pulses to the phase comparator; an output signal of the solid-state image sensor and an output pulse of the driving pulse generator; and an output pulse of the synchronization signal generator, and a signal processing unit that receives the signals as input and outputs a color television signal as an output. (2) The solid-state image sensor, drive circuit, drive pulse generator, voltage-controlled oscillator, low-pass filter, phase comparator, and shift register section must be configured so that they can be separated into a signal processing section and a synchronization signal generator. A solid-state imaging device according to claim (1), characterized in that: