JPH0548664B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides a PLL for a drive circuit of a solid-state image sensor.
The present invention relates to a solid-state imaging device using a (Phase-locked loop) circuit.

Conventional Structure and Problems In recent years, solid-state imaging devices have been actively researched and developed as new imaging devices, and are rapidly reaching the stage of practical application.

Television cameras using solid-state image sensors have many superior characteristics, such as long life, robustness, afterimages, burn-in, and stability, compared to conventional image pickup tube type television cameras.

The position of the photoelectric conversion element is addressed in the solid-state image sensor by the scanning pulse output from the CCD type, which is obtained by transferring the signal charge from the photoelectric conversion element arranged two-dimensionally, or the shift register for vertical and horizontal scanning. There are many methods, such as the MOS type, which reads out the signal.

For the above-mentioned solid-state image sensor, PLL has been mainly used to drive the PAL element. A conventional example will be explained below with reference to FIG. In FIG. 1, 1 is a synchronizing signal generator, and 2 is a PLL circuit which generates a clock from the horizontal synchronizing signal WHD generated by the synchronizing signal generator 1. 3 is a logic circuit that generates the timing necessary for driving the elements using a clock generated by the PLL circuit 2 and a synchronization pulse generated from the synchronization signal generator 1; 4 is a driver that drives the sensor 5;

Next, the PLL circuit section will be explained in more detail with reference to FIG. 6 is the synchronization signal generator 1 in FIG.
A phase comparator that compares the phase of the horizontal synchronization signal (WHD) output from the horizontal synchronization signal (WHD) and the negative edge of the horizontal period pulse generated by dividing the clock that provides the timing necessary for horizontal drive; 7 is the low phase comparator 6. 8 is a voltage-controlled oscillator circuit that generates a clock frequency pulse by the output of the low-pass filter 7; 9 is a voltage-controlled oscillator circuit that generates a clock frequency pulse from the clock frequency; This is a frequency divider that counts down to a horizontal period pulse, and the above constitutes the PLL section.

Next, the operation of the above block will be explained.
Compare the phases of the negative edges of the two inputs of the phase comparator 6, and if the horizontal synchronization signal (WHD) generated from the synchronization signal generator 1 is ahead of the output of the frequency divider 9 in phase, it is set to "H" level. If the phase is delayed, it outputs "L" level. At times other than the above, the state is “OPEN”. The low-pass filter 7 extracts a DC component from the output of the phase comparator 6, thereby generating a voltage corresponding to the phase difference between the two inputs of the phase comparator 6. In the voltage controlled oscillation circuit 8, the capacitance of the variable capacitance diode changes depending on the input voltage level, and the oscillation frequency changes. The frequency divider 9 counts down the pulses generated by the voltage controlled oscillation circuit 8 by the horizontal scanning frequency.

The above is a conventional PLL configuration, and when it is incorporated into the system shown in FIG. 1, pulse noise is generated. This becomes fixed pattern noise in solid-state cameras, which actually appears as a vertical striped pattern on the monitor, and is a factor that prevents the camera from achieving higher sensitivity. The cause of pulse noise is that when the counter in the PLL section counts down to the horizontal scanning frequency, the frequency divider circuit also counts pulses during the video period, so a large amount of noise is generated in the frequency divider circuit and the logic circuit connected to it. A pulse current flows, which mixes into the video signal through the power supply and ground paths, degrading the image quality. This pulse noise can be dealt with to some extent by separating the power supply, ground, etc. around the counter of the PLL section, but in principle it is difficult to reduce it to zero.

OBJECTS OF THE INVENTION The present invention aims to provide a solid-state imaging device that does not generate pulse noise generated in a drive system of a solid-state imaging device.

Structure of the Invention The present invention provides a phase comparator that compares the phases of a horizontal signal obtained by frequency-dividing a clock gated by a horizontal synchronizing signal and a vertical blanking signal, which operate only during the vertical retrace period, and a low-pass filter to which the output is input; a sample-and-hold circuit to which the output of the low-pass filter is input; a voltage-controlled oscillation circuit to which the output of the sample-and-hold circuit is input; and a frequency divider to which the clock output is input. and a drive circuit including a gate circuit that gates the output of the frequency divider by vertical blanking, thereby obtaining a video signal from which pulse noise has been removed.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 is a block diagram of one embodiment of the present invention. In FIG. 3, 10 is one input of the phase comparator 12, which is the horizontal synchronization signal (WHD) output from the synchronization signal generator. In this embodiment, the frequency of the clock 19 is 8 MHz, which is gated with a vertical blanking signal by a gate circuit 21, and the signal whose frequency is divided by 1/512 by a frequency divider (counter) 20 is the other input of the phase comparator 12. It becomes 11.

The above two inputs are input to the phase comparator 12.
14 is a low-pass filter that takes out the DC potential from the output 13 of the phase comparator 12. Since the phase comparison is performed only during the vertical blanking period, the output is zero during the other periods. Voltage controlled oscillation circuit 18
In order to drive, it is necessary to hold the DC potential during the phase comparison period. For this purpose, a sample-and-hold circuit 16 follows the low-pass filter 14. The output 17 of the sample and hold circuit 16 is input to a voltage controlled oscillation circuit 18, which generates pulses with a clock frequency of 8 MHz. This clock pulse is sent to the gate circuit 21,
The PLL configuration provides feedback to the phase comparator 12 through a frequency divider 20.

Next, the above operation will be explained according to the timing chart of FIG. The two inputs of the phase comparator 12 are shown in FIG. 4a and b. These two input phase difference signals 13
becomes like c. This pulse error signal is converted into an analog quantity such as d by charging and discharging the active filter. The error voltage Vd generated here is held by the sample and hold circuit 16 for a vertical period, and becomes as shown in e. This sample and hold circuit 16 can be of either digital or analog configuration.

With the above configuration, since no countdown is performed during the video period, there is in principle no possibility that countdown noise will mix into the video signal and appear as synchronous noise, degrading the image quality.

Effects of the Invention As described above, according to the present invention, it is possible to eliminate the generation of synchronous noise that degrades the image quality of a solid-state camera. Another advantage is that it can be implemented relatively easily by simply adding a gate circuit and a sample-and-hold circuit to a conventional element drive circuit.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the structure of a solid-state image sensor drive system, Fig. 2 is a block diagram of a conventional PLL circuit, Fig. 3 is a block diagram showing an example of a PLL circuit according to the present invention, and Fig. 4 is a block diagram thereof. This is a timing chart showing the operation of a PLL circuit. 12... Phase comparator, 14... Low pass filter, 16... Sample hold circuit, 18... Voltage controlled oscillation circuit, 20... Frequency divider circuit, 21...
gate circuit.

Claims (1)

[Claims] 1. A gate circuit that gates a clock pulse with a vertical blanking signal, a frequency divider that divides the output of the gate circuit, and a horizontal synchronization signal generator that uses the output of the frequency divider as a first input and generates a horizontal synchronization signal generator. a phase comparator that receives the signal as a second input; a low-pass filter that receives the output of the phase comparator;
a sample and hold circuit that receives the output of the low-pass filter and holds a DC potential during a period during which phase comparison is performed by the phase comparator;
A solid-state imaging device comprising a drive circuit including a voltage-controlled oscillation circuit that receives the output of the sample-and-hold circuit and generates a clock pulse.