JPH0614695B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a PLL (Phase-Loc) drive circuit for a solid-state image sensor.
The present invention relates to a solid-state imaging device using a ked loop) circuit.

2. Description of the Related Art In recent years, research and development of solid-state image pickup devices have been actively conducted, and video cameras using the solid-state image pickup devices have been rapidly put into practical use.

The number of pixels of the solid-state image sensor determines the resolution characteristic of the video camera, and it is considered that the solid-state image sensor having the number of pixels according to the application will be developed in the future. Therefore, a drive circuit that can handle an arbitrary number of pixels is required.

Hereinafter, a conventional solid-state imaging device will be described with reference to the drawings. FIG. 3 shows the structure of the solid-state imaging device. (11) is a sync signal oscillator, (12) is a PLL circuit that generates a clock pulse CK from the horizontal sync signal HD output from the sync signal oscillator (11), and (13) is a clock pulse that is generated by the PLL circuit (12). A logic circuit that generates a pulse necessary for driving the solid-state image pickup device by various synchronization pulses output from CK and the synchronization signal oscillator (11).
This is a drive circuit that drives (15).

FIG. 4 shows a conventional configuration example of the PLL circuit (12) in FIG. (21) is a horizontal synchronizing signal HD output from the synchronizing signal oscillator (11) in FIG. 3 and a clock pulse CK described later.
, A phase comparator for comparing the phases of pulses HD ′ obtained by frequency division, (22) outputs the output of the phase comparator (21) to both pulses HD, H.
A low-pass filter for converting into a DC voltage corresponding to the phase shift of D ', and (23) is a voltage controlled oscillator which generates a clock pulse CK having a frequency according to the DC voltage obtained from the low-pass filter (22). Reference numeral (24) is a frequency divider, which divides the frequency of the clock pulse CK generated by the voltage controlled oscillator (23) and inputs it to the phase comparator (21). The frequency division ratio N of the frequency divider (24) is the ratio between the frequency CK of the horizontal transfer pulse ΦH and the frequency _H of the horizontal synchronization signal HD, which is required according to the number of horizontal pixels of the solid-state image sensor.
By thus configuring the PLL circuit, it is possible to sequentially correct the frequency and phase of the generated clock pulse CK, and obtain the clock pulse CK that is phase-locked with the horizontal sync pulse HD.

Problems to be Solved by the Invention However, normally, the frequency divider is composed of flip-flops of which the number is different according to the frequency division ratio, and a pulse current flows when the state of each flip-flop changes. The frequency divider (24) in the PLL circuit always performs the counting operation even during the video period, and the clock pulse CK of the frequency CK of the horizontal transfer pulse ΦH of the solid-state image sensor is changed to the frequency _{H of the} horizontal synchronizing pulse HD.
Since the frequency is divided up to, the frequency of the pulsed current is in the video frequency band, and this pulsed current mixes with the video signal via the power supply, ground, etc., and becomes fixed pattern noise with vertical stripes on the monitor TV screen, Remarkably reduces the image quality. To suppress the influence of this pulsed current, the PLL
Although it can be dealt with to some extent by separating the power source of the circuit frequency divider (24), shielding, etc., it cannot be completely eliminated, which hinders the high image quality of the video camera.

In view of the above drawbacks, the present invention provides a solid-state imaging device in which pulse noise does not occur.

Means for Solving the Problems In order to solve this problem, the solid-state imaging device of the present invention is
A gate circuit that gates a clock pulse with a horizontal blanking signal, a counter that counts the output of the gate circuit, an output of the counter as a first input, and a horizontal synchronization signal generated from a synchronization signal oscillator as a second input. And a low pass filter to which the output of the phase comparator is input, a sample and hold circuit to which the output of the low pass filter is input, and the output of the sample and hold circuit, and the clock pulse It is configured to have a drive circuit including a voltage controlled oscillator that generates

Operation With this configuration, the counter is not operating during the image scanning period, the influence of the pulsating current flowing through the counter does not appear in the image, and the image quality of the video camera is not hindered.

Description of Embodiments An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a PLL circuit section of a solid-state imaging device according to an embodiment of the present invention. In FIG. 1, (31) is a phase comparator, (32) is a low pass filter, (33) is a voltage controlled oscillator, and (3)
4) is a counter, (35) is a sample hold circuit, and (36) is a gate circuit. Where phase comparator (31), low-pass filter
(32) and the voltage controlled oscillator (33) are the same as those in FIG.

The gate circuit (36) is a circuit that gates the clock pulse CK generated by the voltage controlled oscillator (33) with the horizontal blanking pulse HBLK, and the pulse CK 'output from the gate circuit (36) is input to the counter (34). The counter 34 is a counter which is reset by the horizontal blanking pulse HBLK and counts the number of input pulses CK ', and outputs a ripple carry pulse RC when counting N'.
Here, N'is the pulse width t of the horizontal synchronizing pulse HD described later.
It is a value (natural number) obtained by dividing _H by the period t _CK of the clock pulse CK having a frequency required as a horizontal transfer pulse.
Ripple carry pulse R output from the counter (34)
C serves as one input of the phase comparator (31). Phase comparator (3
The other input of 1) is the horizontal sync pulse HD output from the sync signal oscillator, the phases of these two pulse inputs are compared, and the output passes through the low pass filter (32) and the horizontal sync pulse HD is output. The ripple carry pulse RC output from the counter (34) is converted into a DC voltage corresponding to the phase shift. It is the DC voltage immediately after the phase comparison that accurately shows the phase shift data in this DC voltage.
The obtained DC voltage is applied to the sample hold circuit (3) so that the voltage controlled oscillator (33) can oscillate stably in one horizontal scanning period.
Hold sample by 5). The DC voltage obtained from the sample hold circuit (35) is the voltage controlled oscillator (33).
And a clock pulse CK is output. This clock pulse is fed back to the gate circuit (36) again.

By thus configuring the PLL circuit, the clock pulse CK that is phase-synchronized with the horizontal synchronization pulse HD can be obtained.

FIG. 2 is a timing chart showing the operation of the solid-state imaging device PLL circuit according to the embodiment of the present invention. (41) is a horizontal blanking pulse HBLK, (42) is a horizontal synchronizing pulse H
D and (43) are clock pulses CK. The clock pulse CK becomes the pulse CK 'of (44) by passing through the gate circuit (36). Further, it is obtained by the ripple carry pulse RC of (45) which passes through the counter (34). The ripple carry pulse RC and the horizontal sync pulse HD pass through a phase comparator (31), a low pass filter (32), a sample hold circuit (35),
The clock pulse CK is transmitted to the voltage controlled oscillator (33).

According to this configuration, the counter (34) is not operating during the video scanning period, the effect of the pulsating current flowing through the counter (34) does not appear in the video, and the effect is great.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to eliminate the occurrence of pulse noise that deteriorates the image quality of the solid-state imaging device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention, FIG. 2 is a timing chart showing the operation of the PLL circuit of FIG. 1, and FIG. 3 is a block diagram showing the configuration of a conventional solid-state imaging device. FIG. 4 is a block diagram of a conventional PLL circuit. (31) …… Phase comparator, (32) …… Low-pass filter, (33) ……
Voltage controlled oscillator, (34) …… Counter, (35) …… Sample hold circuit, (36) …… Gate circuit

Claims (1)

[Claims] 1. A gate synchronization circuit that gates a clock pulse with a horizontal blanking signal, a counter that counts the output of the gate circuit, and a horizontal synchronization generated by a synchronization signal generator with the output of the counter as a first input. Second signal
, A low-pass filter to which the output of the phase comparator is input, a sample-and-hold circuit to which the output of the low-pass filter is input, and the output of the sample-and-hold circuit are input, A solid-state imaging device having a drive circuit including a voltage-controlled oscillator that generates a clock pulse.