JPS6194457A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent mixing of count-down noises in video signals and to improve its picture quality by adding a gate circuit and a sample holding circuit to an element driving circuit and thereby eliminating the entire count-down in video signals. CONSTITUTION:A horizontal synchronizing signal WHD10 from the synchronizing signal generator of a solid-state image pickup element driving system is applied to the phase comparator 12 of a PLL circuit and clock 19 outputted by the circuit 12 is phase-compared with a signal made by dividing by a frequency divider 20. The cock 19 is gated by a vertical blanking signal in a gate circuit 21, and a signal only in blanking period is supplied to the comparator from the frequency divider 20 and phase-compared only for the period. An output of the comparator 12 is supplied to the sample and hold circuit 16 through an LPF14 and only the signal in the blanking period in which phase comparison is made is held. An output 17 of the circuit 16 is supplied to a voltage control type oscillating circuit 18, and count-down in the video signal is not made to prevent lowering in picture quality.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a PLL (Phass
The present invention relates to a solid-state imaging device using an e-1ocked 1oop) circuit.

Conventional Structures and Their Problems In recent years, solid-state imaging devices have been actively researched and developed as new imaging devices, and are rapidly reaching the stage of practical use.

Television cameras using solid-state image sensors have many superior characteristics, such as long life, robustness, afterimages, burn-in, and stability, compared to conventional image pickup tube type television cameras.

The position of the photoelectric conversion element is addressed in the solid-state image sensor by scanning pulses output from a CCD type or shift register for vertical and horizontal scanning, which is obtained by transferring signal charges from photoelectric conversion elements arranged two-dimensionally. MO to read out the signal
There are many types such as S type.

For the above-mentioned solid-state image sensor, a PLL has mainly been used to drive the PAL element. A conventional example will be explained below with reference to FIG. 1 in Figure 1 is a synchronization signal generator, 2 is P
A clock is generated from the horizontal synchronizing signal WHD generated by the synchronizing signal generator 1 in the LL circuit. Numeral 3 is a logic circuit that generates the timing necessary for driving the elements using a clock generated by the PLL circuit 2 and a synchronization pulse generated by the synchronization signal generator 1. Numeral 4 is a logic circuit that drives the sensor 6. 6 is a phase for comparing the phase of the horizontal synchronization signal (WHD) output from the synchronization signal generator 1 in FIG. 1 and the negative edge of the horizontal period pulse generated by dividing the clock that provides the timing necessary for horizontal drive. 8 is a voltage controlled oscillation circuit that generates a clock frequency pulse by the output of the low-pass filter 7, 9 is a clock. This is a frequency divider that counts down to the horizontal period pulse inputted to the frequency and phase comparator 6, and the above constitutes a PLL section.

Next, the operation of the above blocks will be explained.

By comparing the phases of the two negative edges of the phase comparator 6, the horizontal synchronization signal (W) generated by the synchronization signal generator 1 is determined.
HD) is ahead of the output of frequency divider 9 in phase, then ff
It outputs Hn level, and if the phase is delayed, it outputs "L" level. At timings other than the above, “○PEN”
state. In the low-pass filter, by extracting the DC component from the output of the phase comparator 6, the phase comparator 60
A voltage is generated according to the phase difference between the two human forces. In the voltage controlled oscillation circuit 8, the capacitance of the variable capacitance diode changes depending on the input voltage level, and the oscillation frequency changes. The frequency divider 9 counts down the pulses generated by the voltage controlled oscillation circuit 8 to the horizontal scanning frequency.

The above is a conventional PLL configuration, and when it is incorporated into the system shown in FIG. 1, pulse noise is generated.

This becomes a fixed pattern noise in the solid-state camera, which actually appears as a vertical striped pattern on the monitor, and is a factor that prevents the camera from increasing its sensitivity. The cause of pulse noise is PLL
When the counter in the section counts down to the horizontal scanning frequency, the frequency divider circuit also counts pulses during the video period, so a large amount of pulse current flows through the frequency divider circuit and the logic circuit connected to it, which causes the power supply and It mixes into the video signal via the ground path and degrades the image quality. Although this pulse noise can be dealt with to some extent by separating the power supply, ground, etc. around the counter of the PLL section, it is difficult to reduce it to zero in principle.

OBJECTS OF THE INVENTION The present invention aims to provide a solid-state imaging device that does not generate pulse noise generated in a drive system of a solid-state imaging device.

Structure of the Invention The present invention provides a phase comparator that compares the phases of a horizontal signal that is frequency-divided from a clock gated by a horizontal synchronization signal and a vertical blanking signal that operate only during the vertical retrace period, and a phase comparator for the phase comparator. a low-pass filter to which the output is input; a sample-and-hold circuit to which the output of the low-pass filter is input; a voltage-controlled oscillation circuit to which the output of the sample-and-hold circuit is input; and a frequency divider to which the clock output is input. and a drive circuit including a gate circuit that gates the output of the frequency divider by vertical blanking, thereby obtaining a video signal from which pulse noise has been removed.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 is a block diagram of one embodiment of the present invention. In FIG. 3, 10 is one person's power of the phase comparator 12, and the horizontal synchronization signal (
WHD). In this embodiment, the clock 190 frequency is 8 MHz and is gated with a vertical blanking signal by the gate circuit 21, and the signal whose frequency is divided by 1/512 by the frequency divider (counter) 20 is sent to the other side of the phase comparator 12. Input 11
becomes.

The above two human forces are input to the phase comparator 12.

14 is a low-pass filter that extracts the DC potential from the output 13 of the phase comparator 12. Here, phase comparison is performed only during the vertical blanking period, so the output is zero during other periods. In order to drive the voltage controlled oscillation circuit 18, it is necessary to hold the DC potential during the phase comparison period. For this purpose, a sample-and-hold circuit 16 follows the low-pass filter 14. The output 17 of the sample and hold circuit 16 is input to a voltage controlled oscillation circuit 18, which generates a pulse with a clock frequency of 8 MHz. This clock pulse is passed through the gate circuit 21 and the frequency divider 20.
It has a PLL configuration that feeds back to the phase comparator 12 through.

Next, the above operation will be explained according to the timing chart of FIG. The phase comparator 1202 is manually operated as shown in Fig. 4(a).
(b). The phase difference signal 13 generated by these two people is (C)
become that way. This pulse error signal is converted into an analog quantity as shown in (d) by charging and discharging the active filter. The error voltage Vd generated here is held by the sample and hold circuit 16 for a vertical period, and becomes as shown in (e). This sample and hold circuit 16 can be of either digital or analog configuration.

With the above configuration, since no countdown is performed during the video period, there is in principle no possibility that countdown noise will mix into the video signal and appear as synchronous noise, degrading the image quality.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the occurrence of synchronous noise that degrades the image quality of solid-state cameras can be eliminated.

Another advantage is that it can be implemented relatively easily by simply adding a gate circuit and a sample-and-hold circuit to a conventional element drive circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a solid-state image sensor drive system, FIG. 2 is a block diagram of a conventional PLL circuit, FIG. 3 is a block diagram showing an example of a PLL circuit according to the present invention, and FIG.
The figure is a timing chart showing the operation of the PLL circuit. 12... Phase comparator, 14... Ropa/(filter, 16... Sample hold circuit, 18... Voltage controlled oscillator circuit, 20...・・・
...Frequency divider circuit, 21...Gate circuit.

Claims (1)

[Claims] A gate circuit that gates a clock pulse with a vertical blanking signal, a frequency divider that divides the output of the gate circuit, and a horizontal synchronization generator that uses the output of the frequency divider as a first input and that is generated from a synchronization signal generator. a phase comparator that receives a signal as a second input; a low-pass filter that receives the output of the phase comparator; a sample-and-hold circuit that receives the output of the low-pass filter; and a sample-and-hold circuit that receives the output of the sample-and-hold circuit. A solid-state imaging device comprising a drive circuit including a voltage-controlled oscillation circuit that generates clock pulses.