JPH0746845B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a PLL (Pha) for generating a horizontal transfer pulse of a solid-state image sensor.
The present invention relates to a solid-state imaging device using a se Locked LooP) circuit.

2. Description of the Related Art In recent years, research and development of solid-state image pickup devices as new image pickup devices have been actively carried out, and they are rapidly reaching the stage of practical application. Along with this, there is an increasing demand for higher resolution or the number of pixels according to the application, and a drive circuit capable of supporting an arbitrary number of pixels is required. To achieve this purpose, a solid-state imaging device having a PLL circuit is generally used.

A conventional solid-state imaging device having a PLL circuit will be described below with reference to the drawings.

FIG. 3 shows the configuration of the solid-state imaging device. 21 is a sync signal generator, 22 is a PLL that generates a clock pulse CK from the horizontal sync pulse HD output from the sync signal generator 21.
The circuit, 23 is a clock pulse CK generated by the PLL circuit 22 and various synchronization pulses output from the synchronization signal generator 21,
A logic circuit for generating pulses φH and φV necessary for driving the solid-state image sensor, and 24 is a drive circuit for driving the solid-state image sensor 25. 26 is a part of the PLL circuit 22 and the logic circuit 23
Semiconductor integrated circuit board (hereinafter referred to as IC) on which and are arranged 27
Is an IC 2'where a part of the PLL circuit 22 is arranged.

FIG. 4 shows a configuration example of the PLL circuit 22 in FIG. Reference numeral 31 denotes a horizontal synchronizing signal HD output from the synchronizing signal generator 21 of FIG. 3, two pulses Q _N and a pulse Q _N ′ having different phases obtained by dividing a clock pulse CK described later, and a phase described later. A phase comparator for comparing the phase with a pulse HD ′ having a pulse width narrower than that of the horizontal blanking pulse obtained through the comparison pulse generation circuit 36; 32 is the output of the phase comparator 31 depending on the phase difference between both pulses HD, HD ″. Low-pass filter for converting to DC voltage, 33 is a voltage controlled oscillator, low-pass filter
A clock pulse CK having a frequency corresponding to the DC voltage output from 32 is generated.

Reference numeral 34 is a shift register, which is the frequency _φH of the horizontal transfer pulse φH of the solid-state image sensor and the frequency _{HD of the} horizontal synchronization pulse _HD.
The number of stages is N which is one half of the ratio. 35 is an inverter. A phase comparison pulse generation circuit 36 generates a pulse HD 'having a pulse width narrower than that of the horizontal blanking pulse by using the final stage output Q _N and the intermediate stage output Q _N ′ of the shift register.

37 is an IC1 in which the above-mentioned phase comparator and the above-mentioned phase comparison pulse generation circuit are arranged. The logic circuit 23 shown in FIG. 3 is also arranged on the above-mentioned IC1. Therefore, IC1 is
Same as IC1 '. 38 is an IC2 in which the shift register and the inverter are arranged. This is IC2 'in Fig. 3.
Is the same as The operation of the PLL circuit configured as above will be described below.

The horizontal synchronizing pulse HD and the output pulse HD ″ of the phase comparing pulse generating circuit 36 are input to the phase comparator 31, and a pulse φP ′ indicating the phase difference between the two pulses is output. The pulse φP ′ is the low pass filter 32. Is input into the voltage-controlled oscillator 33, converted into a DC voltage according to the phase difference between HD and HD ″,
A clock pulse CK having a frequency according to the DC voltage value is generated. This clock pulse CK becomes a transfer pulse for the shift register 34. First stage data input D1 of shift register 34
Outputs the output Q _N of the final stage of the shift register 34 to the inverter 35
It is the reverse of the theory. However, it is assumed that the flip-flops at each stage of the shift register are initialized when the power is turned on. By connecting the shift register 34 and the inverter 35 in this way, assuming that the number of stages of the shift register is N, an output pulse Q _N whose state is inverted when N clock pulses are input is obtained from the shift register 34. CK will be divided by (2 × N). The final stage output pulse Q _N and the intermediate stage output pulse Q _N ′ of this shift register are input to the phase comparator 31 with the pulse HD ″ obtained through the phase comparison pulse generation circuit 36, and the other input pulse of the phase comparator is input. The frequency and the phase of the clock pulse CK are corrected by comparing the phase with the horizontal sync pulse HD, which is a clock pulse CK that is phase-synchronized with the horizontal sync pulse HD. A horizontal transfer pulse φH is created, and Fig. 5 shows the phase relationship between the horizontal synchronizing pulse HD and the pulse Q _N pulse Q _N ′ and pulse HD ″ when the clock pulse CK is phase-synchronized. Here, the clock pulse period is t _CK
I am trying. The pulse HD ″ is a pulse having a narrower pulse width than the horizontal blanking pulse as described above, and the horizontal synchronizing pulse and the rising edge coincide with each other.

Problems to be Solved by the Invention However, in the above configuration, the N of the shift register that outputs the pulses Q _N and Q _N ′ input to the pulse generation circuit.
The output loads of the stage and N ′ stages are different from the output loads of the remaining stages of the shift register, and
When Q _N and Q _N ′ are used, pulsed current flows at the falling edges of Q _N and Q _N ′. Since the phase comparison pulse generation circuit, the phase comparator, and the logic circuit are arranged on the same IC chip, the current in the IC of the pulse nature passes through the power supply and the ground, and the phase comparator output A subtle step is generated in the portion that coincides with the timing, and this affects the DC voltage input to the voltage controlled oscillator. Moreover, a slight step is generated in the output of the logic circuit. Due to these influences, there is a drawback that a vertical stripe appears at the center of the image.

Means for Solving the Problems In order to solve the above problems, the solid-state imaging device of the present invention is provided with a frequency dividing circuit for dividing a clock of a specific frequency into a frequency of 1 / N, and the frequency dividing circuit. Using the first divided signal and the second divided signal having different phases, a phase comparison pulse located within the horizontal blanking interval of the television signal and having a narrower width than the horizontal blanking interval is generated. A phase comparison pulse generation circuit is disposed on the first integrated circuit board, and a horizontal synchronization signal of a television signal is used as a first input and the phase comparison pulse is used as a second input, the first input and the second input. And a phase comparator for detecting a phase difference between inputs of the specific frequency and outputting a phase comparison output for performing phase control of the clock of the specific frequency, and a solid-state imaging device driven from the clock of the specific frequency and the horizontal synchronization signal. Emits the necessary signals to The logic circuit to be generated is arranged on the second integrated circuit board.

Operation With this configuration, the pulsed current generated in the phase comparison pulse generation circuit does not affect the phase comparator, the DC voltage input to the voltage controlled oscillator is stabilized within the video period, and The influence on the logic circuit is also eliminated, and the vertical stripe in the center of the image does not appear.

Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a solid-state image pickup device according to an embodiment of the present invention. 1 is a sync signal generator, 2 is a PLL
3 is a logic circuit, 4 is a drive circuit, 5 is a solid-state image sensor, 6 is a phase comparator, 7 is a low pass filter, 8 is a voltage controlled oscillator, 9 is a shift register, and 10 is an inverter. And that of FIG. 11 is AN
D gate, 12 is a gate array 1 in which the phase comparator and the logic circuit are arranged, and 13 is a gate array 2 in which the shift register, the inverter and the AND gate are arranged. In this embodiment, the frequency _φH of the horizontal transfer pulse of the solid-state image sensor is _equal to the horizontal sync pulse frequency _HD .
It uses 512 times, so the number of shift register stages is 256.

The operation of the solid-state imaging device having the PLL circuit configured as described above will be described below.

The phase comparator 6 outputs the horizontal synchronizing pulse HD output from the synchronizing signal generator and the output pulse HD ′ of the AND gate 11 described later.
Is input, and a pulse φP indicating the phase difference between the two pulses is output. The pulse φP is input to the low-pass filter 7 and H
The voltage is converted into a DC voltage V _CK according to the phase difference between D and HD ′ and input to the voltage controlled oscillator 8. Clock pulse CK having a frequency corresponding to the DC voltage V _CK input the voltage controlled oscillator 8
To occur. This clock pulse CK is applied to the shift register 9
As a transfer clock of the shift register 9, the output Q ₂₅₆ of the 256th stage of the shift register 9 is logically inverted through the inverter 10 and input to the input D ₁ of the first stage of the shift register 9, so that the clock pulse CK Is divided by (256 × 2). Furthermore, the output Q of the 256th stage of the shift register 9
_256, and the output Q ₆₄ of the 64-stage shift register 9, AN
Input to D gate 11 and take the logical product of both to obtain pulse HD ′
To get This pulse HD 'is input to the phase comparator 6, the phase is compared with the horizontal synchronizing pulse HD, the same operation is repeated, and the pulse H synchronized with the horizontal synchronizing pulse HD in both frequency and phase is obtained.
Obtain D'and clock pulse CK. The clock pulse CK and the horizontal synchronizing signal H which is the output of the synchronizing signal generator 1.
A pulse φ necessary for driving the solid-state image sensor 5 by inputting D and the vertical synchronizing signal VD to the logic circuit 3.
H, φV is generated and input to the drive circuit 4,
The solid-state image sensor 5 is driven by φH ′ and φV ′. In this embodiment, the phase comparator 6 and the logic circuit 3 are arranged in the gate array 1, and the shift register 9, the inverter 10 and the AND gate 11 are arranged in the gate array 2, respectively.
It was possible to remove the influence of the pulsed current and remove the vertical streak that appeared in the center of the image.

As described above, according to this embodiment, by arranging the phase comparator, the logic circuit, the shift register, the inverter, and the AND gate in different gate arrays, the vertical stripe in the center of the image can be removed.

In this embodiment, two gate arrays are used for arranging the phase comparator, the logic circuit, the shift register, the inverter, and the AND gate on different chips, but the invention is not limited to the gate array. Anything may be used as long as it has a function of arranging on a different IC. Further, although the AND gate is used as the phase comparison pulse generation circuit, it is not limited to the AND gate, and any output having a function of obtaining a pulse thinner than the horizontal blanking pulse by using two outputs of the shift register is used. Anything is fine.

As described above, according to the present invention, by arranging the frequency dividing circuit and the phase comparison pulse generating circuit of the solid-state imaging device and the phase comparator and the logic circuit on different IC chips, the vertical stripes that significantly deteriorate the image quality are provided. Can be removed, and the effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a solid-state imaging device according to an embodiment of the present invention, and FIG. 2 is a horizontal synchronizing pulse HD and a pulse H of the device.
FIG. 3 is a configuration diagram of a conventional solid-state imaging device, FIG. 4 is a configuration diagram of a conventional PLL circuit of the solid-state imaging device, and FIG. 5 is a horizontal diagram of a conventional example. It is a timing diagram showing the phase relationship between the sync pulse HD and the pulse HD ″. 1 ... Sync signal generator, 2 ... PLL circuit, 3 ... Logic circuit, 4 ... Drive circuit, 5 ... Solid-state imaging device , 6
...... Phase comparator, 7 ... Low-pass filter, 8 ... Voltage controlled oscillator, 9 ... Shift register, 10 ... Inverter,
11 …… AND gate, 12 …… Gate array 1, 13 …… Gate array 2.

Claims (1)

[Claims] 1. A frequency dividing circuit for dividing a clock of a specific frequency into a frequency of 1 / N, and a first frequency dividing signal and a second frequency dividing signal having different phases obtained by the frequency dividing circuit. A phase comparison pulse generating circuit for generating a phase comparison pulse which is located within a horizontal blanking interval of a television signal and is narrower than the horizontal blanking interval is arranged on the first integrated circuit board. A horizontal synchronizing signal of the signal as a first input, the phase comparison pulse as a second input, and the first input and the second
And a phase comparator for detecting a phase difference between inputs of the specific frequency and outputting a phase comparison output for performing phase control of the clock of the specific frequency, and a solid-state imaging device driven from the clock of the specific frequency and the horizontal synchronization signal. A solid-state imaging device comprising: a second integrated circuit board; and a logic circuit that generates a signal necessary for performing the operation.