JP2000358197A - Generator for drive timing signal of solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a general purpose circuit which generates a drive timing signal of a solid state image pickup device. SOLUTION: This timing signal generating circuit consists of a 1st counter circuit 14 which performs repeatedly a counting operation up to the 1st count value to set a horizontal direction on the basis of the output signal of a divider 12, a 2nd counter circuit 15 which repetitively performs counting operations up to the 2nd count value to set a vertical direction on the basis of the output signal of the divider 12 and a 1st counter output signal of the circuit 14, a 1st decoding circuit 10 which outputs various synchronizing signals by means of the 1st counter output signal of the circuit 14 and a 2nd counter output signal of the circuit 15 and according to the 1st decoding value to be set and a 2nd decoding circuit 20 which outputs various drive signals to decode and drive a solid state image pickup element by means of the 1st counter output signal of the circuit 14 and the 2nd counter output of the circuit 15 and according to the 2nd decoding value to be set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device driving circuit and a synchronizing signal necessary for driving a solid-state image pickup device used in a video camera, a digital still camera and the like, and for generating a synchronizing signal for the camera. It relates to a generating circuit.

[0002]

2. Description of the Related Art Conventionally, a solid-state image pickup device driving circuit and a synchronizing signal generating circuit as shown in FIGS. FIG. 4 is a simplified version of the drawing described in JP-A-9-107497, and FIG.
FIG. 1 is a simplified version of the drawing described in Japanese Patent Publication No. 8;

FIG. 4 is a block diagram of a conventional solid-state imaging camera. In FIG. 4, when the solid-state imaging device 1 senses light, a vertical driving signal (φV1 to φV1) from a solid-state imaging device driving circuit 41 is output.
φV4) and horizontal drive signals (φR, φH1, φH2) 4
2 outputs a solid-state image sensor output signal 2 and outputs a CDS 3
(Collete Double Samplin
g; correlated double sampling circuit; which removes noise from the CCD output signal). Solid-state image sensor drive circuit 4
1 outputs a clock 44 obtained by converting the level of the oscillation output from the oscillator 4 to the synchronization signal generation circuit 43, and generates a synchronization signal (HD,
VD, SYNC, etc.) 45 and the vertical drive signals (φV1 to φV4) and the horizontal drive signals (φR, φH).
1, φH2) 42 is generated. The synchronization signal generation circuit 43 is provided with a control signal 47 from the microcomputer 46.
This makes it possible to change the timing of the synchronization signal.

FIG. 5 is a configuration diagram of a conventional solid-state imaging device driving circuit. In FIG. 5, a clock 52 obtained by receiving an oscillation output from an oscillator 4 by an oscillation circuit 51 and converting the level is divided by a frequency divider 53,
54 and 55.

The frequency dividers 53, 54 and 55 have a predetermined frequency division ratio in advance, and pass the frequency division outputs outputted in accordance with the frequency division ratio to a selector 56, and under the instruction of a clock selection 64, select the selector 56. Based on the divided output selected one by
The counter circuit 57 counts a predetermined counter value, and the counter output signal 58 is supplied to a decode circuit (1) 59 and a decode circuit (2) 60. The decode circuit (1) 59 and the decode circuit (2) 60 have a set value from the decode circuit 61 in advance, and a buffer 62 based on the set value.
, Various drive signals 63 are output. Further, the decode circuit 61 can change the set values of the decode circuit (1) 59 and the decode circuit (2) 60 by data setting from a microcomputer or the like, and can change the timing and pulse width of the drive signal.

[0006]

According to the prior art shown in FIG. 4, the synchronous signal generating circuit 42 can generate various pulse timings by setting from the microcomputer 46. Can be handled by the synchronization signal generation circuit 43 even if
It is necessary to change the solid-state imaging device drive circuit 42, and since the solid-state imaging device drive circuit 42 is individually configured with respect to the synchronization signal generation circuit 43, a phase between signals due to transmission and reception of signals between the circuits occurs. It is necessary to specify conditions. This may cause a problem that a predetermined phase condition is not satisfied because a clock frequency becomes high particularly when a multi-pixel solid-state imaging device 1 is used, and the influence of a propagation delay in an input / output unit of each circuit increases. There is.

According to the conventional example shown in FIG. 5, the solid-state image sensor driving circuit can cope with the change of the solid-state image sensor 1, but cannot cope with the synchronization signal generating circuit. According to the configuration described above, since a plurality of frequency dividers from the oscillation circuit must be provided for each solid-state imaging device 1, the circuit becomes redundant, and the frequency of the divided signal of a different frequency causes the generation of a drive signal. Since the count value of the counter circuit 57 is fixed, the solid-state image sensor 1 having a different number of pixels, such as VGA, XGA, or SXGA, or an interlaced image sensor is used. There is also a problem that it cannot be shared with the solid-state image pickup device 1 having a different driving method such as scanning and progressive reading. In any case, in the above conventional example, there is no versatility for the solid-state imaging device 1 having a different clock or a different driving method. Therefore, each time the specification of the solid-state imaging device changes, the drive circuit and the synchronization signal generation circuit are reconfigured. There is an inefficiency problem that must be done.

It is therefore an object of the present invention to provide a versatile solid-state imaging device driving and synchronizing signal generating circuit.

[0009]

According to a first aspect of the present invention, there is provided a solid-state imaging device driving timing signal generating apparatus comprising: an oscillator for generating a reference clock; and a frequency divider for dividing a clock output from the oscillator according to a frequency dividing ratio. A first counter circuit that repeats counting up to a first count value that sets a horizontal direction (H direction) based on an output signal from the frequency divider; an output signal from the frequency divider; A second counter circuit that repeats counting up to a first count value that sets a vertical direction (V direction) based on a first counter output signal from the first counter circuit, and a first counter circuit of the first counter circuit. A first counter for decoding based on a first decode value to be set and outputting various synchronization signals by using a counter output signal and a second counter output signal of the second counter circuit; A solid-state imaging device that decodes based on a second decode value set using a decode circuit, a first counter output signal of the first counter circuit, and a second counter output signal of the second counter circuit And a second decode circuit that outputs various drive signals for driving

Further, in the solid-state image pickup drive timing signal generating device according to claim 2, the first counter circuit and the second counter circuit set a dividing ratio for the divider. Connecting the first and second count values to the first decode circuit, the microcomputer interface circuit for setting the first decode value and the second decode value in the second decode circuit, and the microcomputer interface circuit. A control circuit for programmably setting a frequency division ratio, the first count value, the second count value, the first decode value, and the second decode value is provided.

According to the solid-state imaging drive timing signal generator of the present invention, the drive signal generation circuit and the synchronization signal generation circuit are the same circuit, and the circuit is applied to the solid-state imaging device having different clocks according to various settings from the control circuit. It is possible to generate a drive signal and a synchronization signal for the solid-state imaging device with the same circuit without any change.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic configuration diagram of an embodiment of the present invention, wherein 1 is a solid-state image sensor, 2 is a solid-state image sensor output signal, 5 is a solid-state image sensor drive signal synchronizing signal generation circuit, Reference numeral 6 denotes a drive signal for driving the solid-state imaging device 1, 7 denotes a double sampling signal, 8 denotes a microcomputer, and 9 denotes a data signal. In FIG. 1, a solid-state imaging device drive signal synchronization signal generation circuit 5 receives an oscillation signal oscillated by an oscillator 4.
Are φR, φH1, H2, φV1 to V4 suitable for the solid-state imaging device 1 when set by the data signal 9 from the microcomputer 8.
And the like. The solid-state imaging device 1 supplies the solid-state imaging device output signal 2 to the CDS 3 according to the driving signal 6 on the left, and the noise is removed by the double sampling signal 7.

FIG. 2 is a diagram showing the configuration of a solid-state imaging device drive signal synchronization signal generation circuit according to the present invention.
11 is a clock 2fck, 12 is a frequency divider, 13 is a divided output clock, 14 is a counter circuit 1, 15 is a counter circuit 2, and 16 is a half of a horizontal period from the counter circuit (1) 14.
2 is a 2H output signal which is output at a constant period, 17 is an output signal 1 having an n-bit width of the counter circuit (1) 14, 18 is an output signal 2 having an m-bit width from the counter circuit (2) 15,
Reference numeral 19 denotes a decoding circuit 1 which receives an output signal (1) 17 and an output signal (2) 18 and outputs a synchronizing signal 24.
The decode circuits 2 and 21 which output 5 are microcomputer interface circuits which receive a data setting signal 23 from the control circuit.

In FIG. 2, the oscillating circuit 10 which has received the oscillating signal from the oscillator outputs the level-converted clock 2fck11.
The frequency divider 12 divides the clock 2fck11 on the left in accordance with the frequency division ratio specified by the microcomputer interface circuit 21, for example, divides the frequency by two, divides by three, divides by four, etc. The clock 13 is supplied to the counter circuit (1) 14
To supply. In the counter circuit (1) 14, one-half of the horizontal period of the solid-state imaging device 1 is determined with reference to the frequency-divided clock 13 on the left.
Microcomputer interface circuit 21 to count
From the LSB of the counter circuit (1) 14 while supplying the 2H output signal 16 at a cycle of 1/2 of the horizontal period to the counter circuit (2) 15.
An output signal (1) 17 having an n-bit width up to n is output.
The counter circuit (2) 15 is preset from the microcomputer interface circuit 21 so as to count the vertical period of the solid-state imaging device 1 on the basis of the 2H output signal on the left. 1)
Similarly, an output signal (2) 18 having an m-bit width is output. When the decode circuit (1) 19 receives the output signal (1) 17 and the output signal (2) 18, the microcomputer interface circuit receives the output signal (1) 17 for the signal output every horizontal period based on the output signal (1) 17 on the left. Various signals are generated based on the decode value set for each signal, and the signals output for each vertical period are set for each signal from the microcomputer interface circuit 21 based on the output signal (2) 18 on the left. Various signals are generated based on the decoded values that are present, and for signals in which the horizontal cycle and the vertical cycle are mixed, the signals are generated by mixing the signal generated in the horizontal cycle and the signal generated in the vertical cycle. Thus, the decoding circuit (1) 19 outputs the synchronization signal 2
4 (eg, HD, VD, or CSYNC). The decoding circuit (2) 20 receives the output signal (1) 17, the output signal (2) 18, and the synchronization signal 24, and is set from the microcomputer interface circuit 21 in the same manner as the decoding circuit (1) 19 on the left. The solid-state imaging device 1 is driven based on the decoded value. For example, φR, φH1, H2 and φV1
The drive signal 25 such as V4 and the CDS3 are driven. For example, a signal composed of the double sampling signal 7 is output.

A specific example of the present invention will be described. 1288 effective pixels in horizontal direction, 96 effective pixels in vertical direction
49. When driving solid-state imaging device 1 including eight pixels
49.0 in the oscillation circuit 10 using the 09 MHz oscillator 4
A 9 MHz clock 2fck11 is output. In the microcomputer interface circuit, when the frequency division ratio is set so that the frequency divider 12 divides by four, the frequency divider 12 to 12.2
When a frequency divider output 13 of 725 MHz is output and a counter value 1 is set to the counter circuit (1) 12 so as to divide the frequency by 390, the counter circuit (1) 12 outputs twice the NTSC horizontal frequency of 31. 46KHz 2H output signal 16
Is output, and 105 is output to the counter circuit (2) 15.
When the counter value 2 is set so as to divide by 0, the counter circuit (2) 15 outputs 30H of 1/2 of the NTSC vertical frequency.
An output signal 18 of z is output. Decoding circuit (1) 19
For example, in order to generate an HD (pulse width of about 6.3 μs) of the synchronization signal, the microcomputer interface circuit 21 uses the decode value 0 and the decode value 76 (77 * 1 / 12.272).
5 specifies about 6.3 us), so that the pulse width of HD can be specified using the output signal 17 from the counter circuit (1) 14. Further, in order to generate the VD (pulse width of about 36H period) of the synchronization signal, by setting the decode value 0 and the decode value 35 from the microcomputer interface circuit 21, the output signal 18 can be used to define the pulse width of the VD. In the decoding circuit (2) 20, a signal as shown in FIG. 3, for example, a period during which the fck clock is masked to generate φH is defined by a decode value from the microcomputer interface circuit 21 or φV is generated. At the beginning of the VD, a charge pulse for reading out charges from the solid-state imaging device 1, generation of a transfer pulse for each H, setting of the pulse insertion period, and the like are performed. In the CCD output timing shown in FIG. 3, the numeral is a line number in the V direction (vertical direction), "D" is a dummy pixel output outputted in a dummy period until the CCD is stabilized, and "OB" is , A black level pixel output (Optical
Black).

Since such a setting can be performed in a programmable manner, even if the solid-state imaging device 1 having 640 horizontal pixels and 480 vertical pixels is changed, the oscillation frequency of the oscillator is changed to 24.5454 MHz and the frequency divider is changed. By resetting the frequency division ratio to divide by two, it is possible to easily cope with the generation of the drive signal of the solid-state imaging device 1 and the generation of the synchronization signal. Also, the change of NTSC and PAL can be realized by changing the setting of the count circuits 1 and 2.

Further, it is possible to easily cope with various solid-state imaging devices such as 510 horizontal pixels, 480 vertical pixels, 768 horizontal pixels, and 480 vertical pixels.

In the above example, the frequency divider and the count circuit 1,
2 is described assuming an up-counter, but it may be constituted by a down-counter or a circuit that performs another counting operation, and the same applies to a shift register. In a microcomputer interface circuit, an interface with a personal computer or a microcomputer is used. The present invention is not limited thereto.

The above description of the decode value and the count value is merely an example, and the values are not particularly defined.

[0021]

According to the present invention, the drive signal generation circuit and the synchronization signal generation circuit are made the same circuit, and the solid-state image pickup device is driven by the same circuit without changing the circuit for the solid-state image pickup device having different clocks according to various settings from the control circuit. Since it is possible to generate signals and synchronization signals, inefficiencies such as having to recreate the circuit every time the solid-state image sensor is changed are eliminated, and by using the same circuit, a multi-pixel solid-state image sensor Is driven, it is possible to cope with an increase in speed without being aware of the phase due to the propagation delay of the signal between the synchronization signal generating circuit and the driving circuit.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of an embodiment of a solid-state imaging device drive timing signal generator according to the present invention;

FIG. 2 is a configuration diagram of a solid-state imaging device drive circuit synchronization signal generation circuit according to the present invention;

FIG. 3 is a diagram showing a drive signal according to the present invention;

FIG. 4 is a diagram showing a configuration example of a conventional solid-state imaging camera.

FIG. 5 is a diagram showing a conventional drive circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Solid-state image sensor output signal 3 CDS 4 Oscillator 5 Solid-state image sensor drive signal synchronizing signal generation circuit 6 Drive signal 7 Double sampling signal 8 Control circuit 9 Data signal 10 Oscillator circuit 11 Clock 2fck 12 Divider 13 Frequency division Output clock 14 Counter circuit 1 15 Counter circuit 2 16 2H output signal 17 Output signal 1 18 Output signal 2 19 Decoding circuit 1 20 Decoding circuit 2 21 Microcomputer interface circuit 22 Division ratio 23 Data setting signal

Claims (3)

[Claims] An oscillator for generating a reference clock; a frequency divider for dividing a clock output from the oscillator; a first counter circuit for counting based on an output signal from the frequency divider; A counter circuit, and a first decoding circuit that decodes based on output signals of the first counter circuit and the second counter circuit and outputs a synchronization signal;
And a second decode circuit for outputting a drive signal for driving the solid-state imaging device. 2. A frequency divider for a frequency divider, a first counter circuit and a second counter circuit for a first count value and a second count value, respectively, and a first decode circuit and a second decode circuit. 2. The solid-state imaging device drive timing signal generating device according to claim 1, further comprising a microcomputer interface circuit for setting a first decode value and a second decode value in each of the decode circuits. 3. A control circuit connected to a microcomputer interface circuit for setting a frequency division ratio, a first count value, a second count value, a first decode value, and a second decode value in a programmable manner. The solid-state imaging device drive timing signal generator according to claim 2.