JP2976320B2 - Image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor used for reading an image of a facsimile, a copying machine, an image scanner or the like.

[0002]

2. Description of the Related Art Heretofore, a time chart of input / output signals as described in Japanese Patent Application Laid-Open No. 1-298863 has been described. FIG. 5 is a time chart of a conventional image sensor IC. Based on the time chart shown in FIG. 5, a one-channel signal is output immediately after the start signal φSI synchronized with the falling edge of the clock φCK, and the signal φSIG photoelectrically converted by the n-channel light receiving element is clocked. The signal is output during the clock Low period in synchronization with the falling of φCK, and after the n-channel signal is output, the scanning signal φSO for starting the next chip is synchronized with the rising of the clock φCK from the period T32 to T34 of the clock High.
During the output.

[0003]

However, in a conventional image sensor IC, when a cascade connection is made in a multi-chip configuration, the falling of a scanning signal for starting the next chip is delayed by a clock delay inside the IC. Therefore, the signal output period overlaps with the signal output period of one channel of the next chip.
There has been a problem that switching noise of a scanning signal is mixed into a signal output terminal and a signal output of one channel of the next chip is reduced.

Further, in a conventional image sensor IC, when a start signal is cascaded in a multi-chip configuration in order to take in a signal using a High period of a clock, a scanning signal for starting the next chip is provided. After the last n-channel signal of the previous chip is output,
The delay time T due to the delay of the clock in the IC to output for the period of the clock High in synchronization with the clock rise
The sum of the PLH and the data setup time TSU is the High period 1 / (fCLK
× [100-LDUTY (%)] / 100) or less, the operation is not performed correctly. Therefore, when the signal output period is set to be long, the High period of the clock becomes short, and the High of the scanning signal also becomes short, thus causing a problem that the maximum drive frequency becomes low. Therefore, an object of the present invention is to
In order to solve such a conventional problem, it is an object to prevent a decrease in signal output of one channel and obtain a high-speed operation.

[0005]

In order to solve the above-mentioned problems, the present invention provides an image sensor IC which outputs a signal photoelectrically converted by an n-channel light receiving element in synchronization with a falling edge of a clock. The start signal for starting is output for one clock in synchronization with the falling edge of the clock after the output of the n-1 channel signal or the final n channel signal, and the start signal is clocked low.
Data was taken during the period.

[0006]

In the image sensor IC configured as described above, when a cascade connection is made in a multi-chip configuration, a scanning signal for starting the next chip is:
Since one clock is output in synchronization with the rising of the clock, the falling of the scanning signal does not overlap with the signal output period of one channel of the next chip, so that switching noise is not added to the signal output terminal.

Further, a start signal for starting the next chip is output for one clock in synchronization with the rise of the clock after the output of the (n-1) -th channel signal, and the start signal is made using the period of the clock Low. Capture the signal. At this time, if the signal output period is made longer, the period of the clock Low becomes longer, so that the delay time TPLH and the data setup time TS due to the delay of the clock inside the IC.
There is ample room for the limitation by U, and the maximum drive frequency becomes high.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an image sensor IC according to an embodiment of the present invention. A signal from the light receiving element 1 is connected to a common signal line 3 via a switching element array 2. The clock signal terminal 4 is connected to the data flip-flop circuit 5 and the scanning circuit 6. The start signal terminal 7 is connected to the data terminal 8 of the data flip-flop circuit 5. The master output terminal 9 of the data flip-flop circuit 5 is connected to the scanning circuit 6. The data flip-flop circuit 5 uses a clock signal rising operation and takes in data using a clock Low period.

FIG. 2 shows an image sensor I according to an embodiment of the present invention.
It is a time chart of C. In the present invention, as shown in the time chart of FIG. 2, when a start signal φSI synchronized with the falling edge of the clock φCK is input to the start signal terminal 7, the output signal of the master output terminal 9 is output via the data flip-flop circuit 5 to the scanning circuit. 6 and the scanning circuit 6
The switching element 2 is sequentially turned on by the output signal of, and the output signal φSIG photoelectrically converted from the light receiving element 1 is a signal of one channel immediately after the start signal φSI is input from the signal output terminal 11 through the switching element 10 through the common signal line 3. And outputs an n-channel signal in a clock Low period in synchronization with the falling edge of the clock φCK. Also, n-
After outputting the signal of one channel, the scanning signal φSO is output from the SO terminal 13 via the scanning signal SO forming circuit 12.

FIG. 3 is a block diagram showing a multi-chip configuration of the image sensor IC according to the present invention. As shown in FIG. 3, an image sensor IC 14-1 having n-channel light receiving elements 1 arranged in the main scanning direction. In a multi-chip line sensor in which a plurality n of 14-n are arranged in the main scanning direction, the CLK of the image sensor ICs 14-1.
The terminals 4 are connected to a common CLK wiring 15 and a terminal 16, respectively. The signal output SIG terminals 11 are connected to common signal output
It is connected to the. First stage image sensor IC 14-1
The start signal SI terminal 7-1 is connected to the terminal 19. The scanning signal SO terminal 13-1 is connected to the start signal SI terminal 7-2 of the next chip via the scanning signal wiring 21, and the image sensor IC 14-2 for the second and subsequent chips.
.. Similarly connected between 14-n. When mounted on a substrate with this configuration, a parasitic capacitance 21 always exists between the signal output SIG wiring 17 and the scanning signal wiring 21.

However, as shown in the time chart of FIG. 2, the scanning signal .phi.SO for starting the next chip has a clock rising point T13 during a period of TPLH from a clock rising point T11 to T12 due to a delay of a clock in the IC. The delay of the signal φSO does not overlap with the period of the clock Low, that is, the signal φSIG output period, as compared with the conventional waveform by delaying the period from TPHL to T14, so that the scanning signal wiring 20 and the signal output SIG wiring 17 The switching noise of the scanning signal φSO is not mixed into the signal output SIG wiring 17 during the signal output φSIG output period, even if the parasitic capacitance 21 exists between them.

Further, since the scanning signal φSO is output in synchronization with the rising edge, when the scanning signal φSO is input to the start signal terminal SI of the next chip, the start signal terminal SI uses the period of the clock Low. In the case where the period of the clock Low is extended in order to lengthen the signal output period in order to take in the signal, the period in which the scanning signal φSO is taken in becomes long, and the delay time TP due to the delay of the clock inside the IC
The limitation by the LSU and the data set-up time TSU from T14 to T15 has a sufficient margin as compared with the related art, and the maximum drive frequency becomes higher.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a time chart of the image sensor IC according to the second embodiment of the present invention. In the present invention, as shown in the time chart of FIG.
A signal of one channel is output immediately after the start signal φSI synchronized with the falling edge of the clock signal, a signal φSIG photoelectrically converted by the n-channel light receiving element is output during the clock Low period in synchronization with the falling edge of the clock φCK, and the last n After outputting the channel signal, a scanning signal φSO for starting the next chip for one clock synchronized with the rising of the clock φCK is output.

Here, also in the present invention, similarly to the first embodiment, when a multi-chip configuration as shown in FIG.
The scanning signal φSO is TPLH from the clock rising point T21 to T22 due to the delay of the clock inside the IC.
In the period, the delay of the signal φSO is delayed from the conventional waveform by a period of TPHL from the clock rising point T23 to T24, so that the falling of the signal φSO does not overlap with the period of the clock Low, that is, during the signal φSIG output period. Parasitic capacitance 2 between the signal output SIG wiring 17 and
Even when 1 is present, the switching noise of the scanning signal φSO does not enter the signal output SIG wiring 17 during the signal output φSIG output period.

For convenience, the signal output is output during the clock low period in synchronization with the clock falling. However, the signal output may be output during the clock high period in synchronization with the clock rising, and the circuit can be changed accordingly. or,
For convenience, the start signal is one clock synchronized with the clock falling, but the pulse width may be 1 clock or more.
Also, the circuit may be synchronized with the rising edge of the clock, and in that case, the circuit can be changed accordingly.

Incidentally, the image sensor according to the present invention comprises:
Solid-state imaging device, image input device, facsimile, workstation, digital copier, image input device such as word processor, OCR, barcode reader, camera, video camera, photoelectric conversion subject detection device for auto focus such as 8mm etc. It can be applied to and is effective.

[0017]

As described above, the present invention prevents the noise of the scanning output signal from being added to the signal output by generating the scanning output signal during the period not overlapping with the signal output period, and further starts the operation. When a signal is taken in during a clock Low period and a multi-chip structure is used, the S / N ratio of the device is improved without changing the input signal, and the effect of the maximum drive frequency is further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image sensor IC according to an embodiment of the present invention.

FIG. 2 is a configuration diagram when an image sensor IC according to an embodiment of the present invention has a multi-chip configuration.

FIG. 3 is a diagram showing a time chart of the image sensor IC according to the embodiment of the present invention.

FIG. 4 is a diagram showing a time chart of an image sensor IC according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a time chart of a conventional image sensor IC.

[Explanation of symbols]

 Reference Signs List 1 light receiving element 4 clock CLK terminal 5 data flip-flop circuit 7 start signal SI terminal 11 signal output SIG terminal 13 scanning signal SO terminal 17 signal output SIG wiring 20 scanning signal wiring 21 parasitic capacitance

Claims (5)

(57) [Claims] 1. A line array comprising a light receiving element array and a scanning circuit.
It is formed by arranging a plurality of image sensor ICs linearly.
In the image sensor, the preceding image sensor IC is
Image signal from adjacent image sensor IC at the subsequent stage
Generate a start signal to output to the output terminal
It has a function and the end of the preceding image sensor IC.
One first light receiving element disposed at a different portion
Of the first light receiving element after the output of the image signal of
Of the image signal of the second light receiving element
Until the output starts, the image signal is not output.
During the absence period, the logic of the start signal is inverted.
Before the output of the image signal from the second light receiving element ends.
The third light receiving element disposed at a rear portion of the second light receiving element.
Until the output of the image signal from the optical element is started, the image
While the signal is not output, the logic of the start signal
The image sensor is characterized in that the image is inverted again. 2. The method according to claim 2, wherein the second light receiving element is disposed next to the first light receiving element.
2. The image sensor according to claim 1, wherein an optical element is arranged.
Sa. 3. The third light receiving element next to the second light receiving element.
3. The image sensor according to claim 2, wherein an optical element is arranged.
Sa. 4. The image forming apparatus according to claim 1, wherein the first light receiving element is an image of the former stage.
Light reception just before the last light receiving element of the di-sensor IC
And the second light receiving element is an image of the preceding stage.
The third light receiving element of the sensor IC,
An optical element is arranged at the beginning of the subsequent image sensor IC.
4. The image sensor according to claim 3, wherein said light receiving element is a light receiving element.
Sa. 5. The image forming apparatus according to claim 1, wherein the first light receiving element is an image of the former stage.
The last light receiving element of the di-sensor IC,
A light receiving element is placed at the beginning of the latter image sensor IC
4. The image sensor according to claim 3, wherein the light receiving element is a light receiving element.
Sa.