JP3086495B2 - Clock supply method for multi-chip type CCD image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply system for a multi-chip type CCD image sensor which has a wide range of uses as an image input device such as a facsimile or a digital copying machine and is a kind of a contact type image sensor.

[0002]

2. Description of the Related Art In recent years, for example, there has been an increasing demand for a compact facsimile machine, and attention has been paid to a close contact type image sensor (actual size image sensor). The contact-type image sensor reads an original image at the same magnification with a short-focus rod lens array, so that the optical path length is short and the structure can be integrated, the device can be downsized, and adjustment is unnecessary and assembly is simple. , And so on. As one type of this contact type image sensor, there is a multi-chip type that can read at high speed by using a plurality of CCD chips, and an example of the configuration is shown in FIG. FIG. 2 is a schematic configuration diagram of an essential part showing one configuration example of a conventional multi-chip type CCD image sensor.

[0003] This CCD image sensor has CCD chips 1 to 4 arranged in an in-line manner. That each C
The output sides of the CD chips 1 to 4 are directly connected and commonly connected to an amplifier 5, and a video signal is output from the output side of the amplifier 5. Further, each of the CCD chips 1 to
Reference numeral 4 includes a not-shown photodiode for photoelectric conversion, a photogate for accumulating signal charges obtained by photoelectric conversion, a CCD register, and a transfer gate for transferring signal charges from the photogate to the CCD register. A clock signal φ is commonly connected to each CCD register, and transfer pulses φ _{T1 to} φ _T4 are connected to each transfer gate.
Next, the operation will be described with reference to FIG. FIG. 3 is a diagram for explaining the operation of the apparatus shown in FIG. First, CCD chip 1
When the transfer pulse φ _T1 is input to the CCD chip 1, the signal charge stored in the photogate in the CCD chip 1 is changed to C
The data is transferred to the CCD register in the CD chip 1. CCD
The signal charge transferred to the register is carried to the output stage of the CCD register and output by the clock signal φ which is a continuous pulse as shown in FIG.

[0004] Then, the CCD chip 1, at the same time the signal charge of that number of pixels is output, entering the transfer pulse phi _T2 to CCD chip 2, CCD chip 2 same operation as CCD chip 1 To output signal charges after a predetermined timing. At that time, following the output of the signal charge of the last pixel of the CCD chip 1,
If the timing is selected so that the signal charge of the first pixel of the CCD chip 2 is output, a continuous video signal can be obtained. As a result, the signals output from the CCD chips 1 to 4 are output to the outside as continuous video signals, as shown in FIG.

[0005]

However, the multi-chip CCD image sensor having the above configuration has the following problems. Hereinafter, description will be made with reference to the drawings. FIG.
FIG. 4 is a signal waveform diagram obtained by enlarging a waveform portion A in FIG. As shown in FIG. 4, for example, when transferring signal charges from the photogate to the CCD register in the CCD chip 2, it is necessary to supply the transfer pulse φ _T2 when the clock signal φ is at the “H” level. There is. This is because the signal charge cannot be transferred from the photogate to the CCD register unless the potential of the CCD register is higher than the potential of the photodiode. The same applies to the other CCD chips 1, 3, and 4. Therefore, when the clock signal φ is operated at a high frequency in order to enable high-speed operation of the device, the on-time t of the transfer pulses φ _{T1 to T4} is inevitably shortened, so that the signal charge transfer from the photodiode to the CCD register is performed. There is a problem that the time becomes short and the afterimage becomes large.

That is, it takes a certain time to transfer all the signal charges stored in the photogate to the CCD register. However, when the clock signal φ has a high frequency and the on-time t of the transfer pulses φ _{T1 to T4} is shorter than the predetermined time, the signal charges are not completely transferred from the photogate to the CCD register, and some of the signal charges remain on the photogate. I will. This residual signal charge is output in the next cycle, and appears as a residual image phenomenon in which the immediately preceding image overlaps the current image. Therefore, in order to lengthen the on-time t of the transfer pulses φ _{T1 to T4} to avoid the afterimage phenomenon, it is necessary to temporarily stop the supply of the clock signal φ under the high frequency operation of the clock signal φ. Become. As a result, for example, an interval is generated between the output n of the last bit of the CCD chip 1 and the output of the first bit 1 of the CCD chip 2, so that a continuous video signal is not obtained. As a result, there is also a problem that external signal processing becomes complicated. An object of the present invention is to provide a multi-chip type CCD image sensor which solves the problems of the prior art as to the point that afterimages become large when operated at high speed and the point that video signals become discontinuous and external signal processing becomes complicated. Is provided.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a photodiode for converting reflected light of a light beam emitted from a light source to an original image into a signal charge, and a transfer pulse based on a transfer pulse. A multi-chip in which a plurality of CCD chips having CCD registers for transferring the signal charges transferred from the photodiodes to an output side in accordance with a predetermined clock signal are arranged, and the signal charges output from the respective CCD chips are sequentially output; Type CCD
The following measures are taken in the image sensor. That is, an odd-numbered clock and an even-numbered clock are supplied as the clock signals to be supplied to the odd-numbered and even-numbered CCD chips, respectively, from the first stage to the last stage of each CCD chip. The supply of the odd-numbered clock and the even-numbered clock is stopped for a predetermined time when each of the transfer pulses supplied to the first and even-stage CCD chips is turned on.

[0008]

According to the present invention, as described above, a multi-chip CCD
Since the image sensor is configured, the odd clock and the even clock can be separately supplied to the CCD chip. for that reason,
In order to secure a sufficient transfer time of the signal charges transferred from the photodiode to the CCD register, for example, even if the odd clock is temporarily stopped, the obtained signal is discontinuous because the even clock is still operating as in the conventional case. Does not.
That is, while the signal charge is being sent from the preceding CCD chip, the signal charge from the photodiode of the next CCD chip is transferred to the CCD register, and the signal charge for each CCD chip is sequentially and continuously output. Is done. Therefore,
The above problem can be solved.

[0009]

FIG. 1 is a schematic diagram showing a main part of a multi-chip CCD image sensor for implementing a clock supply system according to an embodiment of the present invention, and FIG. 5 is a multi-chip type CCD image sensor showing an embodiment of the present invention. 1 is a schematic configuration diagram of the entire CCD image sensor. In FIG. 5, this multi-chip CCD
The image sensor 50 includes a light source 51 such as a cold-cathode tube, a rod lens array 52 that collects reflected light of a light beam emitted from the light source 51 to a document image 51a, and further includes a timing control unit 53. ing. The timing control unit 53 is a circuit that controls the operation timing of the entire sensor 50 by inputting the input clock signal CK based on the start pulse SP. On the output side of the timing control unit 53, a rod lens array 52
55 and an amplifier 56 for photoelectrically converting a light beam from
, And a video signal Vo is output from the amplifier 56.

In FIG. 1, the sensor section 55 includes a plurality of stages of CCD chips 55a to 55d, which are arranged in an in-line manner in which they are arranged in a straight line. Transfer pulses φ _{T1 to} φ _T4 for transferring signal charges are supplied to the CCD chips 55a to 55d, respectively.
The odd-numbered CCD chips 55a and 55c among the chips 55a to 55d are supplied with an even-numbered clock φE by the even-numbered CCs.
It is supplied to the D chips 55b and 55d, respectively. Further, the output sides of the CCD chips 55a to 55d are commonly connected to an output terminal 56. FIG. 6 is a schematic configuration diagram of the CCD chip 55a in FIG. CCD
The chip 55a includes a photodiode array 61 for photoelectric conversion, a photogate 62 for storing signal charges obtained by photoelectric conversion of the photodiode array 61, and a signal in the photogate 62 based on the transfer pulse φ _T1 , as in the conventional device. A transfer gate 63 for transferring charges; a CCD register 64 for sequentially outputting signal charges transferred from the photogate 62 by the transfer gate 63 to the output side based on an odd clock φo;
And a preamplifier 65 that amplifies the output of the output terminal 4 and outputs it to the output terminal OS.

Further, other CCD chips 55b to 55d
Has almost the same configuration as the CCD chip 55a.
The difference is that the transfer pulse φ _T1
Transfer pulses φ _{T2 to} φ _T4 with different timings
Are supplied, and the CCD chips 55b,
55d is supplied with an even clock φE. Odd clock φo and even clock φE
, The transfer pulse φ _T1, φ _T3及beauty transfer path
These signals are generated by the timing control unit 53 shown in FIG. 5 so as to stop for a predetermined time when the pulses φ _T2 and φ _T4 are turned on. Next, the operation of the multi-chip CCD image sensor configured as described above will be described with reference to FIGS. 7 is an operation explanatory diagram of FIG. 1, and FIG. 8 is an enlarged waveform diagram of a portion A in FIG.

First, when a start pulse SP is input from the outside to the timing control unit 53, a clock signal CK is also supplied to the timing control unit 53 at the same time. Then
In the timing control unit 53, based on the clock signal CK,
Transfer pulses φ _{T1 to} φ _{T4 which} are turned on at predetermined timings as shown in FIG. 7 are generated, and when the transfer pulses φ _{T1 to} φ _T4 are turned on, a predetermined time is set.
Odd clock φo and even clock φ whose supply is stopped
E is generated. These transfer pulses φ _{T1 to} φ _T1
T4 , the odd clock φo and the even clock φE are supplied to the sensor unit 55 via the driver unit 54. On the other hand, the light beam emitted from the light source 51 to the original image 51a becomes strong and weak reflected light according to the density of the original image 51a, and the reflected light is transmitted through the rod lens array 52 to the photodiode array of each of the CCD chips 55a to 55d. Irradiated at 61.
As a result, the irradiated reflected light is photoelectrically converted by the photodiode 61, and the obtained signal charge is
Is accumulated in

Here, for example, if the transfer pulse φ _T1 is turned on, the photo gate 6 of the CCD chip 55a
2 is transferred to the CCD register 64. Subsequently, the signal charges are sequentially conveyed to the output side of the CCD register 64 by the odd clock φo and sent out from the output terminal OS to the output terminal 56. This CC
D while from CCD register 64 of the chip 55a the signal charges are sent out, as shown in FIG. 8, even clock φE fixed time time t1~ time t4, stops. Transfer path over the time t2~ time t3 of the suspension period
The pulse φ _T2 is turned on, and the transfer of the signal charge from the photogate of the CCD chip 55b to the CCD register is completed at time t3. On the other hand, even during the stop period of the even-numbered clock φE, the odd-numbered clock φo is operating, so that signal charges are transmitted from the CCD chip 55a, and the amplifier 56 outputs the n-th video signal Vo.

At the time t3, the CCD chip 55b, which has completed the charge transfer to the CCD register 64, turns on the even-numbered clock φE at the subsequent time t4 , so that the CCD register 64 is synchronized with the even-numbered clock φE. The signal charges therein are sent to the output terminal 56.
As a result, the signal charge of the first bit sent from the CCD chip 55b is output following the n-th signal charge which is the last bit sent from the CCD chip 55a. 8, a continuous video signal Vo is obtained. Also, the CCD chip 55
c and 55d perform the same operation as the CCD chips 55a and 55b. Thus, in the present embodiment, the odd clock φo
The even clock φE fed separately and, transfer Pal
Scan phi _T1, phi _T3 predetermined time when the turning on the odd-number clock φo is stopped, the transfer pulse phi _T2, since so as to stop the even clock φE when turned on phi _T4, the transfer pulse phi _T1 ~ the pulse width of phi _T4 can be set to any width regardless of the frequency of the even clock φE and odd clock .phi.o. As a result, the transfer time of the signal charges transferred from the photogate 62 to the CCD register 64 can be sufficiently secured, and occurrence of an afterimage can be prevented. Further, while a signal is being sent from the preceding CCD chip to the output terminal 56, the photogate 62 of the next CCD chip is turned on.
The signal charges therein can be transferred to the CCD register 64, whereby a continuous video signal Vo is obtained. Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, in the above embodiment, the timing control unit 53 is provided inside the sensor 50, and the timing control unit 53
, The odd clock φo and the even clock φE are generated, but they may be generated outside the sensor 50. By doing so, the CCD chips 55a to 55d
The present invention can be implemented by adding only one clock supply wiring connected to the power supply without significantly increasing the outer shape.

[0015]

As described in detail above, according to the present invention, the odd clock and the even clock are separately supplied to the CCD chip, and the odd clock is stopped for a predetermined time when the odd transfer pulse is turned on. Since the even-numbered clock is stopped when the even-numbered transfer pulse is turned on, the pulse width of the transfer pulse can be set to an arbitrary width regardless of the frequency of the even-numbered clock and the odd-numbered clock. As a result, a sufficient transfer time of signal charges transferred from the photodiode to the CCD register can be ensured even at a high speed operation, and afterimages can be suppressed. Further, while signals are being sent from the preceding CCD chip, signal charges on the photodiode side of the next CCD chip can be transferred to the CCD register. As a result, signals from each CCD chip are continuously obtained, and external signal processing is simplified. In addition, if the odd clock and the even clock are generated outside the sensor main body, it is possible to realize a small-sized image input device capable of high-speed reading.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part of a multi-chip CCD image sensor according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a main part of a conventional multi-chip type CCD image sensor.

FIG. 3 is an operation explanatory diagram of the device of FIG. 2;

4 is an enlarged signal waveform diagram of waveform portion A in FIG.

FIG. 5 is an overall configuration diagram of a multi-chip CCD image sensor according to an embodiment of the present invention.

FIG. 6 is a schematic configuration diagram of a CCD chip in FIG. 1;

FIG. 7 is an operation explanatory diagram of FIG. 1;

FIG. 8 is a partially enlarged waveform diagram of FIG. 7;

[Explanation of symbols]

51 light source 51a original image 55a to 55d CCD chip 61 photodiode column 64 CCD register φo odd clock φE even clock phi _T1 to [phi] _T4 transfer pulse

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/19-1/193 H04N 1/028-1/031

Claims (1)

(57) [Claims] 1. A photodiode for converting reflected light of a light beam emitted from a light source to an original image into signal charges, and outputting the signal charges transferred from the photodiodes based on a transfer pulse in accordance with a predetermined clock signal. A multi-chip CCD in which a plurality of CCD chips having a CCD register for transferring to the side are arranged, and the signal charges output from the respective CCD chips are sequentially output
In the image sensor, an odd-numbered clock and an even-numbered clock are supplied as the clock signals supplied to the odd-numbered and even-numbered CCD chips, respectively, from the first stage to the last stage of each CCD chip. A multi-chip CCD image sensor, wherein the supply of the odd clock and the supply of the even clock are stopped for a predetermined time when the transfer pulses supplied to the odd-stage and even-stage CCD chips are turned on. Clock supply system.