JPS58178674A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent generation of a flicker, and also to simplify the element constitution, by reading signals of two horizontal photosensitive element trains in order simultaneously by a vertical scanning pulse of different phase in one horizontal blanking period. CONSTITUTION:An image of an object to be photographed is photoelectrically converted, passes through a vertical readout line 306 through the first readout gate in accordance with a horizontal readout controlling line 307 and becomes conductive in the horizontal direction successively in accordance with a horizontal shift register 301, by which it is outputted to output terminals 308, 309 through the second readout gate for executing the scanning in the horizontal direction. In this case, each output terminal of a register 302 is connected in accordance with each horizontal train of the controlling line 307, a control pulse is applied to a pair of horizontal trains L1 and L2, and a pair of L3 and L4... in the first field, and signals of two trains are read out in order simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device that simultaneously scans two horizontal rows, and provides a solid-state imaging device that can eliminate phenomena such as flicker that occur due to different scanning conditions for each field. The purpose is to

A solid-state image sensor is a device in which photosensitive elements such as photodiodes are arranged two-dimensionally, and a video signal is obtained by sequentially scanning the array horizontally and vertically.

The scanning circuit for this scanning is MOS type or C
Various means are known, such as the CD type.

There are several methods of scanning, and the general design is to perform overstep scanning in accordance with NTSC. That is, as shown in FIG. 1, the photosensitive elements 101 for one image are two-dimensionally arranged, and in the first field, every other valley horizontal pixel column is scanned 11 times,
In the second field, the remaining horizontal pixel columns that were not scanned in the first field are scanned. One of the scanning methods for such a solid-state image sensor is Japanese Patent Application Laid-Open No. 51-66'1.
There is a scanning method that simultaneously scans two horizontal rows, as described in Japanese Patent No. 23. Hereinafter, this technique will be referred to as Doji 2-line Manshiki. That is, as shown in FIG. 1B, in one horizontal scan, two adjacent horizontal pixel columns are simultaneously scanned, and the scanning position in the first field and the scanning position in the second field are vertically aligned. This is a method in which the pixels are scanned so that they differ by one horizontal pixel column. Such a simultaneous two-line method has features such as better afterimage characteristics than the general scanning method described above.

FIG. 2 shows an example of the overall configuration of a solid-state imaging device using such a homogeneous two-line scanning method.

Here, the first selection gate 209 is brought into conduction according to the state of the horizontal readout line 217 (states of L+ to Ln). Further, the second selection gate 203 becomes conductive according to the output state of each stage of the horizontal shift register 201. The horizontal 7-foot register 201 is used to sequentially open the second selection gates 203 and 204 in the horizontal direction. Therefore, the output ends 216, 216 are tangent to each vertical readout line 218.

- 10,000, mark field control pulses on terminals 213, 214 JJtl. In the first field, the gates 205 and 206 connected to the terminal 213 become conductive, and in the second field, a control pulse is applied to the terminals 213 and 214 so that the gates 207 and 208 become conductive.

Therefore, in the first field, Ll and Ll
, the pair of L3 and L4, etc. are in a conductive state.
1 In the second field, the pair Ll and L3 + L4 and L
5 pairs... are in a conductive state. Here, the vertical shift register 202 is connected to the horizontal readout control line 21.
7, the first readout gates 209 and 211 are configured to sequentially send out pulses in the vertical direction to make them conductive. As a result, in the first field, the horizontal readout side (
Goods) The pair of Ll and Ll of line 217, the pair of L5 and L4...
..., the pair of Ll and L5 in the second field.

Sequential side pulses are sent to the pair L4 and L5. Thus, the photodiode 21 is
A signal of 0.212 is output to the output terminals 215 and 216. With the above configuration, scanning is performed as shown in FIG. 1B.

A simultaneous two-line type solid-state imaging device configured as described above generates flicker depending on driving conditions. (Reference: “Causes of pseudo-signal generation and its characteristics in solid-state image sensors”, Television Society of Japan 1981 National Conference, p. 63, Ando et al.). Here, the outline will be described according to Fig. 2.

The photodiodes 210 and 212 have a parasitic capacitance iC1+02 between them and the horizontal readout line 217.

In addition, a control pulse is applied to the pair of Ll and Ll in the first field, and to the pair of Ll and L5 in the second field.
Ru. As a result, each photodiode in the read state is under the following conditions. In the first field, the photodiode 210 receives a signal applied to Ll and Ll via C1 and C2, and in the second field,
Only the control pulse applied to Ll is applied via 02. Similarly, the photodiode 212 detects that in the first field, only the control pulse applied to Ll is C.
In the second field, the control pulses applied to L2rL5 are applied via CI+02. In this way, the amount of control pulse applied to the photodiode via the parasitic capacitance during readout differs. As a result, the state of the output signal changes for each field, causing flicker.

In order to eliminate such flicker, two methods can be considered. The first is the method of minimizing the parasitic capacitance mentioned above.
The second beam 4. Ll or Ll, L.

This is a method of sequentially sending control/Z pulses without sending control pulses to each set f at the same time. By the second means, n is controlled to the photodiode through C1 at the time of readout, that is, when the first readout gate 209, 211 is in a conductive state.
Just by applying a pulse, a control pulse is applied to the C2 side.
Therefore, there is no difference in read conditions between the fields. This will prevent the occurrence of 7υtsuka.

However, in the first method, due to the physical structure of the solid-state image sensor,
There are limits to countermeasures. The second means is to supply the output of the vertical shift register sequentially for each horizontal column, whereas in the conventional device configuration, one shift register output is supplied to two horizontal readout control lines by a field switching circuit. Bare@not.

In order to sequentially supply each horizontal column, for example, a common gate electrode (for example, transistors 205, 206
(gate electrode) must be taken out separately and field switching control must be performed. This results in a very complicated structure.

Therefore, in view of the above points, the present invention provides a device that can implement the above-mentioned second means with a practical element configuration.

FIG. 3 shows an example of the configuration of a solid-state imaging device according to an embodiment of the present invention. A concrete example of the vertical shift register is shown in FIG.

Since the present invention relates to vertical scanning by a vertical shift register, the operation of the vertical shift register will be explained using FIG. 4 before explaining the overall configuration.

The shift register shown in FIG. 4 is driven by driving pulses as shown in FIG. At this time, the valley waveform shown in FIG. 5 is obtained. That is, at 10 points in Fig. 5, φ1 is MOS
The transistor is placed at a potential (hereinafter referred to as H potential) that makes the transistor conductive. Further, φ2 is placed at a potential (hereinafter referred to as L potential) that turns off the MOS transistor.

Therefore, the transistor 400 becomes conductive according to φ1, and the N1 point reaches the potential of φ8, that is, the H potential. Since φ2 is at L potential, capacitor C1 is charged to H potential. At this time, transistors 401 and 402 are conductive, and transistor 403 is in a cut-off state. As a result, the output 61 is connected to φ2 via the transistor 401 and to the o potential via the transistor 402, resulting in the A and L potentials.

Next, at time 11, φ2 becomes H potential, φ becomes L potential, and φS becomes L potential. Therefore, the transistors 400, 402, and 403 are turned off, and the transistor 401 is turned on by the voltage across the terminals of the capacitor C1. Further, the transistor 404 is in a conductive state. At this time, the output d1 is passed through the transistor 401 to φ2
3, H potential appears. At the same time, transistor 4
The capacitor C2 is charged to H potential through the capacitor C2. φ2 is L
At the same time as the potential, 01 also becomes the L potential, but at this time, the transistor 404 is cut off, so the voltage between the terminals of C2 is kept at the H potential. At this time, both φS and φ1 are at the L potential, so the charging potential of the capacitor @c+ is discharged through the transistor 400. As a result, the transistor 401 is cut off, and the transistor 61 is kept at the L potential. on the other hand,
The voltage between the terminals of the capacitor C2 causes the transistor 405 to conduct, and the transistors 408 and 407 to be in the cutoff state, so the transistor 62 becomes the conductive state according to φ1, and the capacitor C3 is charged to H potential via the transistor 40B. Ru. 0. Similarly, when φ1 becomes L potential, 62 becomes L potential, but at this time, since transistor 408 is cut off, the potential between the terminals of capacitor C5 is maintained at H potential.

Next, at time 15, the transistor 409 becomes conductive according to the charging potential of the capacitor C5, and the transistors 410 and 411 are in a cut-off state. Therefore, 63 is the transistor 409
Connected to φ2 via tl, an H potential appears. At this time,
Transistor 403 becomes conductive according to the potential of 65, and transistor 404 becomes conductive according to φ2. φ1 is at L potential, and one side of transistor 403 is at 0
Therefore, the charging potential of the capacitor C2 is the same as that of the transistor 4.
03. 4 Q nl ) keeps the transistor 405 in the cut-off state. At the same time, 05 charges capacitor C4 via transistor 412.

By repeating the above operations, the pulse potential f input to φSt becomes φ1. 61°02 according to the driving pulse of φ2.
06... are brought to H potential one after another.

When the /ft register explained above is driven as shown in FIG. 6 in the first field as M and in the second field as B, 01+02+o5
The timing of the pulse appearing at '''°°'' is as shown in FIG.

As can be seen from the explanation in FIGS. 4 and 5 above, this shift register inputs φ8a with the φ1 pulse, and
With 2 pulses, 1,05+ o,... terminal nymph outputs φST pulse, and with φ1 pulse it outputs 62+
04+... A 7-foot φST pulse is output to the terminal.

In this case, as shown in Fig. 6, φ is synchronized with vertical scanning.
φ1 for 13T pulse. In the first field, the phase relationship of the φ2 pulse is φ2. in the order of φ1, and in the second field φ1. Add in the order of φ2. in this way,
When driven, in the first field, the signal is taken into the shift register with the φ1 pulse and output to 61 with the φ2 pulse after one horizontal scan. Next, it is outputted to 62 at the point where the φ2 pulse is added. By this, dl
and 62 pairs, 63 and 64 pairs, etc. are output in this order for each horizontal scan. In the second field, the φS pulse taken into the shift register at φ1 becomes 6 pulses at φ2.
The pairs t, -horizontal scan and 65 are sequentially output for each horizontal scan.

The solid-state imaging device of this embodiment shown in FIG. 3 uses the shift register described below as a vertical 7-foot register.

This will be explained below with reference to FIG.

FIG. 3 shows the overall configuration of the solid-state imaging device. Here, the subject image is photoelectrically converted by the photodiode 305, and the photoelectrically converted electrical signal is passed through the vertical readout line 306 via the first readout gate 2o4 according to the horizontal readout control line 307 and then to the second readout line 306. The signals are output to output terminals 308 and 309 via read gates. Here, the second read gate performs horizontal scanning by sequentially turning on in the horizontal direction according to the horizontal shift register 301. The above is the same as the case of the conventional solid-state image sensor explained in FIG.

Here, as a vertical shift register, for example, the shift register shown in FIG. 4 is driven with a drive pulse as shown in FIG. 6. At this time, each output terminal of the shift register is 0.
．． ．． 02,05... is horizontal reading system (goods)
Each horizontal row of line 307, Ll, L5...
・Connect according to 7.1. From the previous description of the shift register, the control pulses applied to the horizontal readout control line 307 are the pair of L+ and Ll in the first field.

It is applied to the pair of L5 and L4. Also, in the second field, the pair r of Ll, Ll and L5, L4 and L5
It is applied to the pair of... That is, the simultaneous two-line vertical scan described above is obtained.

Furthermore, since the horizontal control line 307 is directly connected to the vertical shift register, each pair of scans described above is
For example, a control pulse is applied to Ll, and then a control pulse is applied to Ll.

Therefore, as mentioned earlier, the fringe caused by the parasitic capacitance between the horizontal readout control line and the photodiode can be prevented by sequentially setting the two horizontal columns that are scanned at the same time into the readout state. There is.

As described above, in the present invention, the problem of flicker in simultaneous 24-inch scanning can be solved by driving the solid-state image pickup device configuration with a special drive pulse. Furthermore, in the case of non-invention, it is possible to eliminate the circuit for switching between feed and lead, thereby simplifying the element configuration. The φ1 potential appears at ns 02. This point is as explained above. For this reason,
The output of each stage of the conventional shift register V is bl.

o,, 05...or use 02+"
'4+... was either used.

That is, either the output γ determined by φ1 is used, or the output n determined by φ2 is used. If this is not done, n control pulses added for each horizontal scan will be φ1. This is because, since it changes according to φ2, a pseudo 1 signal (line density) occurs on the screen for each horizontal scan.

However, in the present invention, unless two lines are scanned simultaneously, two adjacent horizontal scan columns are always added together and are not used. Therefore, even if the previous pseudo signal occurs between two adjacent rows, the average is n, so there is no effect on the reproduced image.
L. As shown in the embodiment, the output terminals 02+04+ are affected by φ1, and the output terminals 0, 05, . . . are affected by φ2. . . . joins the adjacent read-out (goods) line. Therefore, no pseudo signals appear in the reproduced image, and they cannot be used with conventional solid-state imaging devices. All output terminals of soft registers can be used. As a result of the above, the invention can be implemented with the same number of vertical shift register stages as in the prior art, and overall, the element configuration can be simplified in that there is no circuit for field switching.

[Brief explanation of the drawing]

Figures 1 and 'B are schematic diagrams illustrating a simultaneous 2-line scanning type M-gymography imaging device, Figure 2 is a configuration diagram of an example of a solid-state imaging device using a conventional simultaneous 2-line scanning type, and Figure 3 is a diagram illustrating the present invention. FIG. 4 is a block diagram of a solid-state imaging device according to an embodiment of the present invention, and FIG. 4 is a waveform diagram of the vertical shift register. 301...Horizontal shift register, 302...
...Vertical/foot register, 303, 304...
・Mos transistor, 3Q6...Photodiode, 306...-Vertical readout line, 307...
...Horizontal readout @ line, 308, 309...
...output end. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure fθI 01 Eihei Jun Figure 2 Figure 3 Figure 4 Figure 2 Figure 5 Figure 6

Claims (2)

[Claims] (1) Two-dimensionally arranged photosensitive elements are grown, the photosensitive elements are sequentially scanned, and a photographing output signal is output from a vertical readout line via a gate circuit, and during one horizontal blanking period, For vertical scanning pulses with different phases,
C. A solid-state imaging device characterized in that signals from two horizontal photosensitive element rows are sequentially read out at the same time. (2) It has two-dimensionally arranged photosensitive elements and a scanning circuit that sequentially scans the photosensitive elements, each of the photosensitive elements is connected to a vertical readout line via a gate circuit, and the gate circuit is connected to at least two types of It is configured by connecting to each stage of a 7-foot register driven by drive pulses of different phases, inputting pulses synchronized with vertical scanning to the shift register, and using the manually generated pulses to shift 2 of the shift registers during each horizontal scanning period. A solid-state imaging device characterized in that the driving is performed by shifting the driving pulses by stages and changing the phase relationship of the driving pulses of different phases corresponding to each field.