JP3315457B2 - Saw wave generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sawtooth wave generating circuit for CRT deflection. More specifically, the present invention relates to a semiconductor integration technology of a circuit for generating a sawtooth wave for vertical deflection.

[0002]

2. Description of the Related Art In an electronic image display device such as a television and a high-resolution monitor, a phase locked loop circuit (hereinafter referred to as a phase locked circuit) is used.
(PLL circuit) and a method of generating a sawtooth wave by synchronizing with an input synchronization signal is often used. At this time, if a state synchronized with the input synchronization signal is a synchronization state, a state in which the input synchronization signal is not input and a sawtooth wave is generated is defined as a self-running state. The sawtooth wave output in the self-propelled state is
It is unstable and the phase is not guaranteed.

If the synchronization state and the self-propelled state can be determined,
In a self-propelled state, industrial benefits such as a blue screen can be expected. Conventionally, the following circuit has been used as a synchronization / self-running determination circuit. (See Fig. 3) NM
In the OS 10, a VSS 11 is connected to the source side and the substrate. An input synchronization signal 3 is input to the gate side. On the drain side, one end of the capacitor 13 and the resistor 1
4 is connected to one end, and outputs a synchronization / self-running determination signal 15. The other end of the capacitor 13 is connected to VSS16. The other end of the resistor 14 is connected to VDD17.

This circuit utilizes the fact that the synchronization state and the self-running state can be determined by setting the time constant of CR to the maximum period of the input synchronization signal 12. However, the vertical deflection frequency is generally as low as 50 Hz to 120 Hz, and the C
Since the time constant of R needs to be sufficiently lower than the vertical deflection frequency, the capacitance value of the capacitor 13 is 0.01
A large capacitance value of about μF to 1 μF is required, and it is difficult to incorporate the capacitance in an integrated circuit.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to detect that an input synchronization signal is interrupted and a self-running state is detected in a logical manner without using the CR time constant.

[0006]

The present invention employs the following means in order to solve the above-mentioned object. In the counter section, the number of bits of the counter reset by the input synchronization signal is added by n bits from the number of input bits of the D / A converter, so that the number of sawtooth waves can be counted after the input synchronization signal is interrupted.

Further, by using an RS flip-flop, if a set number of sawtooth waves are counted after the input synchronization signal is interrupted, the synchronization / self-running discrimination signal is set. When the input synchronization signal is input again, the synchronization / self-running determination signal is reset.

[0008]

Normally, in a PLL circuit, one sawtooth wave is divided by a number obtained by fully decoding the number of input bits of the D / A converter. Therefore, in the sawtooth wave generating circuit configured as described above, the number of sawtooth waves of 2 nth power can be counted for n bits added to the MSB side.

Further, in order to determine the self-running mode, if the frequency band of the input synchronization signal is set to λmin to λmax, the input synchronization signal is interrupted, and at most λmax / λmin (when there is a decimal part, the integer is used. It can be determined by counting the number of sawtooth waves (for the number of parts + 1).

More specifically, the frequency band for vertical deflection of a television or the like is usually 50 to 120 Hz (λmax / λ
min = 2.4 times), and if three sawtooth waves appear after the input synchronizing signal is interrupted, it is sufficient to switch to the self-running mode.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings, taking a vertical input frequency as an example. In FIG.
The output of the voltage controlled oscillator 1 whose oscillation frequency can be controlled by the control voltage is input to the counter 2 as a clock. The counter 2 has two bits added to the MSB side.
The input synchronization signal 3 is a reset input of the counter 2.
As the output of the counter 2, the output from the LSB to the MSB is input to the D / A converter 4, and the output of the added MSB + 1 and MSB + 2 is input to the synchronization / self-running determination means 5. The input synchronization signal 3 is reset input to the synchronization / self-running determination means 5. The output of the synchronization / self-running determination means 5 is input to the switch means 6. The output of the D / A converter 4 and the input synchronization signal 3 are input to the phase comparator 7. The output of the phase comparator 7 is input to the switch means 6. The output of the switch means 6 is input as a control voltage of the voltage controlled oscillator 1.

In the synchronization / self-running determination means 5, the MSB +
1 and MSB + 2 are input to an AND gate 8 functioning as a decoder. The output of the AND gate 8 is input as a set signal of the RS flip-flop 9. The input synchronization signal 3 is input as a reset signal of the RS flip-flop 9. The output of the RS flip-flop 9 is the output of the synchronization / self-running determination means 5 and is input to the switch means 6.

FIG. 2 shows operation timings and input / output waveforms of the circuit of FIG. Hereinafter, the circuit operation will be described with time. If the input synchronization signal 3 keeps outputting a synchronization pulse within the set period (less than three waves), the counter 2 counts according to the clock output of the voltage controlled oscillator 1. However, since the input synchronization signal 3 is reset within the set period (less than 3 waves), MSB + 1 and MSB + 1
Both +2 do not become “H”. Therefore, the RS flip-flop 9 of the synchronization / self-running determination means 5 is not set. (During this time, the input synchronizing signal 3 keeps resetting the RS flip-flop 9 at a certain period.) Therefore, the output signal of the synchronizing / self-running discriminating means 5 indicates the "L" synchronizing state, and the switching means 6 The output of the phase comparator 7 is connected to the voltage control circuit 1.

At this time, the sawtooth wave output from the D / A converter is synchronized with the rising edge of the input synchronization signal 3.
If the input synchronization signal 3 is interrupted, that is, if no synchronization pulse is output outside the range of the set period (three or more waves), the counter 2 does not reset the input synchronization signal 3, and both MSB + 1 and MSB + 2 are set to “H”. Count until "". Accordingly, the RS flip-flop 9 of the synchronization / self-running determination means 5 is set. (During this period, the input synchronization signal 3 does not reset the RS flip-flop 9.) Therefore, the output signal of the synchronization / self-running determination means 5 is
The switch means 6 switches the input to the voltage-controlled oscillator 1 from the output of the phase comparator 7 to the control voltage set in advance.

[0015]

According to the present invention, as described above, the self-running state (interruption of the input synchronizing signal) is detected in a logical manner without using the time constant of CR. There is an effect that the chip size can be reduced without having to incorporate a capacitor.

Furthermore, the configuration in which the sawtooth wave is counted after the input synchronizing signal is interrupted has an effect that it can be applied to any frequency band without any complicated circuit design.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit example of a vertical input frequency band as an embodiment.

FIG. 2 is a diagram showing the timing of a vertical input frequency band as an example.

FIG. 3 is an explanatory diagram of a conventional method for determining self-running and synchronization in a PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Voltage controlled oscillator 2 Counter 3 Input synchronization signal 4 D / A converter 5 Synchronization / free-running discrimination means 6 Switching means 7 Phase comparator 8 AND gate 9 RS flip-flop 10 NMOS 11, 16 VSS 12 Input synchronization signal 13 Capacitor 14 Resistor 15 Synchronization / self-running discrimination signal 17 VDD

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 4/08 H04N 3/00 G09G 1/00 H03L 7/00

Claims (1)

(57) [Claims] A voltage-controlled oscillator capable of controlling an oscillation frequency by a control voltage; a counter for counting an output of the voltage-controlled oscillator; a D / A converter for converting an output of the counter into an analog signal; A phase comparator for comparing a saw-tooth wave output from the A converter with an input synchronization signal; a synchronization / free-running determination unit to which the input synchronization signal is input; an output of the phase comparator and the synchronization / free-running determination unit Switch means to which an output of the voltage-controlled oscillator is inputted, and an output of the switch means being the control voltage of the voltage-controlled oscillator.
In a sawtooth wave generating circuit having an op circuit, an output of the counter reset by an input synchronization signal and further added by n bits to the MSB side is input to a decoder, set by an output of the decoder, and set by an input synchronization signal. A saw-tooth wave generating circuit comprising a synchronous / self-running discriminating circuit for outputting a synchronizing / self-running discriminating signal in an RS flip-flop to be reset.