JP2500507B2 - Temperature detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a temperature detecting circuit.

[0002]

2. Description of the Related Art Conventionally, when performing temperature compensation of a crystal oscillator, for example, a ring oscillator or a thermistor is used as a temperature detecting circuit.

[0003]

When a ring oscillator is used as the temperature detecting circuit, CMOS inverters must be connected in multiple stages or a capacitive element must be connected in order to suppress the oscillation frequency and reduce the current consumption. I won't. Therefore, when integrated, there is a drawback that the area becomes large or an external element is required.

Further, when the thermistor is used, there is a drawback that it cannot be integrated and must be externally attached.

An object of the present invention is to provide a temperature detecting circuit which can be integrated within a small area and consumes a small amount of current.

[0006]

According to the present invention, a fundamental frequency signal generated by a signal generating means is delayed by a delay means whose delay time changes according to temperature, and the delayed signal and the fundamental frequency signal are The above-mentioned object is achieved by detecting the temperature based on the output of the comparing means for comparing.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to an embodiment shown in the drawings.

In FIG. 1, reference numeral 1 is a signal generating circuit which constitutes a signal generating means and comprises a crystal oscillating circuit 2 and a frequency dividing circuit 3, and a reference frequency signal outputted from the crystal oscillating circuit 2 is predetermined by the frequency dividing circuit 3. The fundamental frequency signal of is divided and output. Reference numeral 4 denotes a delay circuit which constitutes a delay means, which constitutes a charge / discharge circuit comprising three stages of inverters 5 to 5 and capacitors 6 and 6, and the threshold value Vth of the inverter 5 changes in accordance with the temperature change. Therefore, the delay time t changes as the charge / discharge time changes. In this example, the ambient temperature is T1
Set so that the delay time is t1 at ℃. Since the required delay time is sufficiently small, the capacitance of the capacitors 6 and 6 may be about several pF, and the delay circuit 4 can be integrated. Reference numeral 7 is a counter, 8 is a NAND gate forming a comparing means, and 9 and 10 are inverters. 11 and 12 are AN
The D gate, 13 is a temperature data conversion unit, which is composed of a P-channel transistor 14, an N-channel transistor 15, a resistor 16 (resistance value R) and a capacitor 17 (capacitance Ca), and outputs a pulse of the output signal d from the NAND gate 8. The width t (temperature data) is converted into a voltage. An A / D conversion circuit 18 converts the analog input from the temperature data conversion unit 13 into digital data. Reference numeral 19 is a latch circuit, and when the output signal e of the AND gate 12 falls, the A / D conversion circuit 18
Latch data from. Reference numeral 20 denotes a ROM that stores temperature compensation data in advance and outputs data according to the output of the latch circuit 19. A D / A conversion circuit 21 converts the digital output signal of the ROM 20 into an analog signal. Reference numeral 22 is a resistor, and 23 is a variable capacitance diode, the capacitance of which changes according to the output of the D / A conversion circuit 21.

The above structure is integrated except for the resistor 22 and the variable capacitance diode 23.

Next, the operation will be described with reference to FIG.
a, b, c, d, e, f, g are a, b, c, d, in FIG.
The output signals of e, f, and g are shown.

The operation when the ambient temperature is T1 ° C. is as follows.

The signal generating circuit 1 produces the pulse P1 of FIG. 2a. This pulse P1 is output by the delay circuit 4 from FIG.
Pulse P1 'is level-inverted and delayed. The counter 7 counts the output signals of the signal generating circuit 1 and produces an output as in FIG. 2c. Therefore, when the pulse P1 is generated, the pulse P2 of FIG.
It will come from the ND gate 8. Since the pulse width of this pulse P2 is the delay time of the delay circuit 4 which changes according to the change in temperature, the pulse width of this pulse P2 becomes temperature data. In this example, the ambient temperature is T1 ℃, so pulse P
The pulse width of 2 is t1. While the pulse P2 is being output, the P-channel transistor 14 is turned on. At this time, since the N-channel transistor 15 is turned off, the capacitor 17 is charged and the voltage Vg at the terminal g rises. This voltage Vg is Vg = Vdd (1-e
^{-tn / CaR} ) and changes according to the pulse width t (temperature data) of the output signal d from the NAND gate 8.
That is, the temperature data conversion unit 13 converts the temperature data into P2.
The pulse width of will be converted to voltage. n is the number of counts, and in this example, n = 3 is set by setting the counter 7. This voltage Vg is converted into digital data by the A / D conversion circuit 18 and supplied to the latch circuit 19. Then, when the pulse P3 and the pulse P4 of FIG. 2a are generated, these pulses P3 and P4 are delayed by the delay circuit 4 like the pulse P2 ′ P3 ′ of FIG.
5, P6 arise from NAND gate 8 and capacitor 17 is charged as above. In this way, the capacitor 17 is charged to the voltage Vg1, which is converted into digital data by the A / D conversion circuit 18 and supplied to the latch circuit 19. Then, when the counter c is triggered by the falling edge of the pulse P4 and its output c becomes "0", the output of the AND gate 12 becomes "1" as shown in FIG. 2e, and the signal generation circuit 1 outputs the pulse P7 as shown in FIG. 2a. Occurs, A
The output of the ND gate 12 becomes "0" as shown in FIG. 2e.
The fall of the output e triggers the latch circuit 19 to latch the temperature data from the A / D conversion circuit 18, and this data becomes the address signal of the ROM 20. R
The OM 20 outputs the temperature compensation data stored in advance according to the output of the latch circuit 19 and converts it into an analog signal by the D / A conversion circuit 21 to output it, thereby changing the voltage applied to the variable capacitance diode 23. To do. The oscillation frequency of the crystal oscillation circuit 2 is adjusted by the change of the capacitance of the variable capacitance diode 23 to perform temperature compensation.

Further, when the pulse P7 is generated, AND
A pulse P8 is output from the gate 11 as shown in FIG. 2f, and the output of this pulse P8 turns on the N-channel transistor 15. At this time, the P-channel transistor 14 is turned off. The charging voltage is instantly discharged. Thereafter, the same operation as described above is repeated to perform temperature compensation of the signal generating circuit 1.

The waveform of the latter half of FIG. 2 shows the waveform of each part when the temperature changes. The longer the delay time of the delay circuit 4 is, the higher the charging voltage of the capacitor 17 becomes. Temperature compensation is performed.

In the above embodiment, the counter 7 is used to convert the voltage into a voltage by adding the delay times of the three fundamental frequency signals, but this number can be set arbitrarily.

An example in which the above temperature compensation operation is performed every time one pulse of the fundamental frequency signal is generated will be described with reference to FIG.

In the figure, reference numeral 24 is an inverter for level-inverting the basic frequency signal from the frequency dividing circuit 3 and supplying it to the N-channel transistor 15.

Next, the operation will be described with reference to FIG. The same reference numerals as those in FIG. 1 denote the same components, and a, b, h, and g in FIG. 4 represent the output signals of a, b, h, and g in FIG.

When the pulse P9 of FIG. 4a is generated from the signal generating circuit 1, the pulse P9 'of FIG. 4b is generated from the delay circuit 4, and the pulse P10 (FIG. 2h) of the width corresponding to the delay time t1 is generated. Will result from While the pulse P10 is being output, the P-channel transistor 14 is turned on, and the capacitor 1 is turned on as shown in FIG. 4g.
7 is charged. This charging voltage is converted into digital data by the A / D conversion circuit 18, and this data supplied to the latch circuit 19 is latched in the latch circuit 19 at the rising edge of the pulse P10. Based on the latched data, temperature compensation of the signal generating circuit 1 is performed in the same manner as in the above embodiment. Then, the signal generating circuit 1 outputs the pulse P9.
Is output and becomes "0" as shown in FIG. 4a, the N-channel transistor 15 is turned on and the P-channel transistor 14 is turned off at this time, so that the charging voltage of the capacitor 17 is discharged. Thereafter, the same operation as described above is repeated to perform temperature compensation of the signal generating circuit 1.

[0020]

As described above in detail, according to the present invention, the temperature is detected from the phase difference between the fundamental frequency signal and its delayed signal, so that integration in a small area is possible. Moreover, the current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a block circuit diagram of another embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of FIG. 3;

[Explanation of symbols]

 1 signal generating means 4 delay means 8 comparing means

Claims (1)

(57) [Claims] 1. A signal generating means for generating a basic frequency signal, a delay means for delaying the basic frequency signal, and a delay time of which changes according to temperature, an output signal from the delay means and the basic signal. A temperature detecting circuit, comprising: a comparing means for comparing with a frequency signal, and detecting a temperature based on an output from the comparing means.