JP3010708B2 - Pulse generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator that generates pulses having a constant period and a constant width.

[Conventional technology]

FIG. 3 shows a configuration of a circuit generally used for a light emitting circuit of a conventional photoelectric switch.

In FIG. 3, the inverters 1 and 2 in the pulse generation circuit 100 are shown.
2,3, tri-state output buffer (hereinafter buffer) 4,
The resistors 6 and 8 are cascaded in a loop, and a capacitor 5 is provided between the output of the inverter 2 and a connection point between the resistors 6 and 8.

The resistor 7 is connected between the output of the output buffer 4 and the reference potential, and the control terminal of the buffer 4 is connected to the output of the inverter 3. An LED driving circuit 50 composed of a series circuit of a light emitting element (LED) 12, a resistor 11, and a transistor 10 is connected between a circuit power supply Vcc and a reference potential, and the transistor 10 is driven by an inverter 3.

In such a circuit configuration, when the output level of the inverter 2 first changes from "H" to "L", the potential at the point (a) becomes substantially -1/2 Vcc (timing T1 in FIG. 4).
The output of inverter 3 is at level "H". Since the control terminal of the buffer 4 also has the level “H”, the output level of the buffer 4 becomes “H”.

As a result, the capacitor 5 is charged through the resistor 6 and a
When the potential at the point rises and the input voltage of the inverter 1 reaches the threshold value, the output of the inverter 1 goes to level "L" and the output of the inverter 2 goes to level "H" (timing T2 in FIG. 4). Therefore, the voltage at the point (a) rises by almost Vcc and at the same time becomes the output level "L" of the inverter 3 and the control terminal of the buffer 4 becomes "L".
Is in a high impedance state.

Accordingly, the capacitor 5 discharges by the series resistance of the resistor 6 and the resistor 7, and when the voltage at the point (a) decreases and reaches the threshold voltage of the inverter 1 (timing T in FIG. 4).
3) The output of inverter 1 is at level "H" and inverter 2
Output is at level "L" and the output of inverter 3 is at level "H"
Becomes As a result, since the control terminal of the buffer 4 is at the level "H", the output of the buffer 4 is again at the level "H".

Hereinafter, this operation is repeated, and the transistor 10 is turned on through the resistor 9 when the output of the inverter 3 is at the level “H”, and supplies a current to the series circuit of the LED 12 and the resistor 11.
Since the resistor 6 is sufficiently smaller than the resistor 7, the LED 12 has a sufficient non-lighting time for the lighting time.

[Problems to be solved by the invention]

In the pulse generator used in the conventional light emitting circuit of the photoelectric switch, the pulse width and the cycle are affected by the threshold voltage of the inverter 1 in addition to the capacitance of the capacitor 5, the component constants of the resistors 6, 7, and 8, and the like. Therefore, if there is a variation in the threshold voltage of the inverter 1 or a change in temperature, the pulse width and the period greatly fluctuate, and there is a problem that the sensitivity and the response time of the photoelectric switch become unstable.

Therefore, an object of the present invention is to provide a pulse generator that can maintain a constant pulse width and a constant generation period even in a pulse generator that generates a pulse by comparing a threshold value of a voltage caused by charging and discharging of a capacitor. It is in.

[Means for solving the problem]

In order to achieve such an object, the present invention provides a pulse generation circuit that generates a pulse by comparing a voltage change caused by charging and discharging of a capacitor with a threshold, and a pulse generation circuit that generates a pulse by one pulse. A pulse is generated from the pulse generating circuit by an output of the frequency dividing circuit, and a frequency dividing circuit that generates a pulse of a fixed cycle by dividing by two, and two types of charge / discharge time constants having different sizes in the capacitor. And a control circuit for alternately switching and setting each time the operation is performed.

(Operation)

The present invention focuses on the fact that the charging / discharging time of the capacitor is always constant, and alternately sets different charging / discharging time constants for the capacitor of the conventional pulse generator. At this time, the time from the rise of the first pulse to the rise of the next second pulse is defined by the first charge / discharge time constant. The time from the rise of the second pulse to the rise of the next first pulse is defined by the second charge / discharge time constant. Further, since the two types of time are always constant, even if the comparison threshold value varies, the peak portion of the output pulse is obtained by dividing the first pulse by 1/2. The valley portion of the output pulse is created by dividing the second pulse by 1/2. For this reason, the output pulse created in this manner is always constant in both pulse width and cycle.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a light emitting circuit in a photoelectric switch according to an embodiment of the present invention.

The same parts as those in the conventional example shown in FIG. 3 are denoted by the same reference numerals, and detailed description will be omitted.

In FIG. 1, the point different from the conventional point in FIG. 3 is that two buffers 13, 14 are connected in parallel instead of the buffer 4 in FIG. 3, and the buffers 13, 14 are opened and closed alternately by flip-flops 20. It is in the point which did. The flip-flop 20 receives the clock of the output of the inverter 2 and outputs a frequency-multiplied clock of the input clock. The flip-flop 20 forms a part of the control circuit of the present invention and operates as the frequency dividing circuit of the present invention. In this example, the Q output of flip-flop 20 is
It becomes a drive pulse for the LED drive circuit 50.

In such a circuit configuration, the voltage at the point (a) initially exceeds the threshold value of the inverter 1 (substantially 1/2 of Vcc in a CMOS circuit) from the state where the output of the inverter 2 is at the level "L".
When the output of the inverter 2 is inverted to the level “H” (second
At the timing T11), the voltage at the point (a) is almost Vcc × 1.
It is 5. At this time, assuming that the Q output of the flip-flop 20 is at the level “H”, the control terminal of the buffer 13 is at the level “H”.

The buffer 13 outputs the output of the inverter 3, that is, the level "L". Since the control terminal of the buffer 14 is at the level “L”, the output of the buffer 14 becomes high impedance. Therefore, a current flows to the output of the buffer 13 through the resistor 6, the capacitor 5 is discharged, and the voltage at the point (a) decreases. When the voltage at the point (a) falls below the threshold value of the inverter 1 (timing T12 in FIG. 2), the output of the inverter 1 is at the level "H", the output of the inverter 2 is at the level "L", and the output of the inverter 3 is Turns to level "H". The voltage at the point (a) is approximately -1/2 Vcc.

Therefore, the output of the buffer 13 becomes "H" level this time, charges the capacitor 5 through the resistor 6, and raises the potential at the point (a). (A) When the potential at the point exceeds the threshold value of the inverter 1 (timing T13 in FIG. 2), the inverter 1
Is at level "L", the output of inverter 2 is at level "H", and the output of inverter 3 is at level "L". When the output of the inverter 2 changes from the level “L” to the level “H”, the flip-flop 20 outputs the Q output (the voltage at the point d) so that the output pulse of the inverter 2 becomes a double pulse.
Is set to the level “L” (timing T13 in FIG. 2).

Therefore, the control terminal signals of the buffers 13 and 14 become "L" and "H", respectively. The buffer 13 becomes high impedance, and the buffer 14 outputs the same level signal as the output of the inverter 3. This is because the same operation is repeated between the timings T13 and T14 in FIG. 2 except that the resistor 6 is replaced by the resistor 7 as compared with the case where the flip-flop 20 is "H". By setting it larger than 6, the output of the flip-flop 20 is set in advance so that the time of "L" is longer than the time of "H".

The transistor 10 conducts while the output of the flip-flop 20 is “H” (timing T11 to T13 in FIG. 2), and causes a pulse current to flow to the LED 12.

In this way, the resistors 6 and 7, the buffers 13 and 14 and the flip-flop 20 alternately set two kinds of charge / discharge time constants for the capacitor 5 as the control circuit of the present invention. First and second two types of pulses are generated alternately. The time from the rise of the first pulse to the rise of the next second pulse is defined by the first charge / discharge time constant. The time from the rise of the second pulse to the rise of the next first pulse is defined by the second charge / discharge time constant. In addition, the above 2
Since the seed time is always constant, even if the comparison threshold value varies, the first pulse
The peak of the output pulse is created by dividing the frequency by half, and the trough of the output pulse is created by dividing the frequency of the second pulse by half. For this reason, the output pulse created in this manner is always constant in both pulse width and cycle.

 The following examples are given in addition to this embodiment.

1) The series circuit configured as the inverter 1 and the inverter 2 in the present embodiment can be replaced by one Schmitt circuit.

2) The buffers 13 and 14 of this embodiment can be replaced by analog switch circuits.

〔The invention's effect〕

As described above, according to the present invention, even if the threshold (voltage) for pulse generation varies, a constant period,
Since a pulse having a constant width is generated, an effect is obtained that the operation accuracy of a device using the pulse generator can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of an embodiment of the present invention, FIG. 2 is a waveform diagram showing signal waveforms in the circuit of FIG. 1, FIG. 3 is a circuit diagram showing a circuit configuration of a conventional example, FIG. The figure is a waveform diagram showing signal waveforms in the circuit of FIG. 1-3,15 ... Inverter, 5 ... Capacitor, 14,15 ... (tristate output) buffer, 20 ... Flip-flop.

Claims (1)

(57) [Claims] 1. A pulse generation circuit for generating a pulse by comparing a voltage change caused by charging and discharging of a capacitor with a threshold value, and a fixed period by dividing a pulse generated by the pulse generation circuit by 1/2. And a charging / discharging time constant having different sizes in the capacitor are alternately switched and set every time a pulse is generated from the pulse generating circuit by an output of the frequency dividing circuit. A pulse generator comprising: a control circuit;