JPH06350421A - Photodetector - Google Patents

Abstract

PURPOSE:To finely set the time from power-on to load operation start by properly selecting the capacitance of a capacitor. CONSTITUTION:A second reference voltage Vref2 starts rising when a power source V1 is turned on, and a terminal voltage (b) of a capacitor 21 starts rising with a specific time constant in accordance with this rise of the voltage Vref2. Since the second reference voltage Vref2 is higher than the terminal voltage (b) of the capacitor 21 until a prescribed time elapses after power-on, the output of a second comparator 22 goes to the high level, and a cut-off transistor TR 41 is turned on. In this case, the voltage between the base and the emitter of the cut-off TR 41 is clearly lower than the threshold voltage of an inverter 27. Consequently, the cutoff TR 41 is turned on earlier before the inverter 27 outputs the low level in the process of the rise to the high level of the output of the second comparator 22. Thus, an AND gate 26 falls to the low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photodetector having both a load initialization circuit and an overcurrent protection circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a general photodetector. In FIG. 3, (1) is a light emitting diode (light emitting element),
The anode is connected to the power supply V1 (5V), and the cathode is grounded via the collector-emitter path of the switching transistor (2). (3) is a light emitting diode (1)
Is a drive circuit for turning on or off. The drive circuit (3)
Is to periodically generate a drive pulse that becomes a high level for 5 μsec in 120 μsec. That is, when a high-level drive pulse is generated, the switching transistor (2) becomes conductive, and accordingly, the light emitting diode (1) is turned on to emit an optical signal. (4) is a light receiving diode (light receiving element), the cathode is connected to the power supply V1, and the anode is grounded via the resistor (5).
(6) is a capacitor, which is connected to the connection point of the light receiving diode (4) and the resistor (5),
The DC component of the current flowing through is removed. (7)
Is an amplifier that amplifies the AC component that has passed through the capacitor (6). Reference numeral (8) is a variable resistor for adjusting the output voltage of the amplifier (7) so that signal processing can be appropriately performed in the subsequent stage. Reference numeral (9) is a capacitor, which is connected to the tap point of the variable resistor (8) and removes a DC component appearing at the tap point of the variable resistor (8). (10)
Is an amplifier, which amplifies the AC component that has passed through the capacitor (9). (11) is a load such as a relay, one end of which is connected to the power supply V2 (12V). (1
2) is a switching transistor, the collector is connected to the other end of the load (11), and the emitter is a resistor (13).
Grounded through. Reference numeral (14) is a signal processing circuit, which applies signal processing to the output voltage of the amplifier (10) so that the load (11) can be driven. Specifically, the signal processing circuit (14) is formed by connecting a plurality of T flip-flops in series, and extends the high level period of 5 μsec of the output voltage of the amplifier (10) to several hundred μsec, so that the load (11) is It is designed so that it can follow and operate sufficiently.

FIG. 4 shows a circuit for detecting that the load (11) has become overloaded. In FIG. 4, (15)
Reference numeral (16) is a resistor connected in series between the power source V1 and the ground, and the first reference voltage Vref1 (1.5 V) is generated at the voltage dividing point of the resistors (15) and (16). (17) is a first comparator, the first reference voltage Vref1 is applied to the non-inverting input terminal, and the base voltage of the switching transistor (12) is applied to the inverting input terminal. The load (11)
Is operating in the normal state, the first comparator (17) outputs a high level. (18) is a constant current source, which is supplied with a power source V1 and supplies a constant current of several μA. That is, the constant current source (18) is equivalent to having an extremely large resistance value of several MΩ. (1
9) is a transistor forming a discharge path, the base of which is connected to the output terminal of the first comparator (17) through an inverter (20), and the collector-emitter path of which is a constant current source (1).
8) and ground. The ON resistance between the collector and the emitter when the transistor (19) is conducting is about 100Ω. (21) is a constant current source (1
8) and a capacitor connected between ground. The capacitor (21) is slowly charged according to the time constant T determined by the resistance value of the constant current source (18) and the capacity of the capacitor (21), and the on-resistance of the transistor (19) and the capacitor (21). Time constant T'determined by the capacity of
According to (<T), the discharge is performed rapidly. Reference numeral (22) is a second comparator, and a second reference voltage Vref2 (1.3V or 3.7V) having a hysteresis described later on the non-inverting input terminal.
Is applied, and the terminal voltage of the capacitor (21) is applied to the inverting input terminal. (23) and (24) are resistors connected in series between the power source V1 and the ground, and the second reference voltage Vref2 having hysteresis is generated at the voltage dividing point. (2
5) is a resistor connected between the non-inverting input terminal and the output terminal of the second comparator (22). That is, the second comparator (2
2) is outputting a low level, the second reference voltage Vre
f2 is 1.3 V obtained by dividing the resistance (23) alone and the parallel combination of the resistances (24) and (25), and the second comparator (2
2) is outputting a high level, the second reference voltage Vre
f2 is 3.7V obtained by dividing the parallel body of the resistors (23) and (25) and the single body of the resistor (24). (26) is an AND gate, the output SP of the signal processing circuit (14) is applied to one input terminal, and the output of the second comparator (22) is applied to the other input terminal via an inverter (27). Applied. (28) and (29) are transistors for supplying a constant current, the base of the transistor (28) is connected to the output terminal of the AND gate (26), and the collector is connected to the power supply V2. That is, when the AND gate (26) outputs a high level, the transistor (28) generates a constant current from the emitter. Reference numerals (30) and (31) are resistors connected in series between the emitter of the transistor (28) and the ground, and the divided voltage value is applied to the base of the switching transistor (12). The resistance (30)
(31) is set to a value such that the divided voltage value is less than the first reference voltage Vref1 when the load (11) is operating normally,
Furthermore, the emitter current of the transistor (28) is set to such a value that it is almost applied to the base of the switching transistor (12). Then, at the time t0 in FIG. 5, when the load (11) is short-circuited due to factors such as incorrect connection and aging, the base voltage of the switching transistor (12) is increased due to the overcurrent of the load (11). Is the first
Detecting that the reference voltage Vref1 has been exceeded, load (11)
And the signal path of the switching transistor (12) is periodically cut off.
The conduction time of 2) is limited to prevent the transistor (12) from being destroyed.

FIG. 6 is a diagram showing a part of a photodetector having both an initial setting circuit for the load (11) and an overcurrent protection circuit. The same elements in FIGS. 4 and 6 are designated by the same reference numerals. In FIG. 6, reference numeral (32) is an oscillator that generates an oscillation clock CK1. (3
3) is a frequency divider, which is formed by connecting a plurality of T flip-flops (not shown) in series, and which divides the oscillation clock CK1 by a predetermined frequency to generate a frequency-divided clock CK2. The number of the plurality of T flip-flops determines the time from when the power source V1 is turned on to when the load (11) starts to operate, and is selected according to the wish of the user who uses the photodetector. It is a thing. The oscillator (32) and the frequency divider (33) are composed of CMOS transistors.
Reference numeral (34) is a reference voltage generating circuit, which is the third reference voltage Vre.
f3 is generated. (35) and (36) are the power source V1
And a resistor connected in series between the ground and the ground. (37) is a third comparator, the third reference voltage V
ref3 is applied and the resistance (35) (3
The connection point voltage of 6) is applied. Here, as shown in FIG. 7, the connection point voltage of the resistors (35) and (36) has a characteristic that it rises so as to exceed the third reference voltage Vref3 at time t ′ when the power source V1 is turned on. is doing. That is, the third comparator (37) outputs a high level before time t'and a low level after time t '. (38) is an RS flip-flop, the divided clock CK2 is applied to the S (set) terminal, and the output of the third comparator (37) is applied to the R (reset) terminal. That is, the RS flip-flop (38) is reset until the time t ′ after the power source V1 is turned on, and then the divided clock CK2.
Is set at the rising edge of. Reference numeral (39) denotes an overcurrent detection block, which corresponds to the portion surrounded by the broken line in FIG. Reference numeral (40) is a NOR gate, to which the inverted output * Q of the RS flip-flop (38) is applied to one input terminal and the overcurrent detection block (39) to the other input terminal.
Output c is applied. That is, the AND gate (26) is closed regardless of the output state of the overcurrent detection block (39) until the time t ′ after the power source V1 is turned on,
The load (11) is set to an initial state in which it does not operate. Further, after the time t ′, the AND gate (26) changes from the open state to the closed state when the overcurrent detection block (39) detects the overcurrent of the load (11), and at this time, the load (11) stops operating. To do.

As described above, the conventional photodetector has both an initial setting circuit including a CMOS transistor and a bipolar transistor and an overcurrent protection circuit.

[0006]

However, even if the number of flip-flops inside the frequency divider (33) is appropriately selected,
The time from turning on the power to starting the operation of the load (11) can only be roughly set (for example, 5, 10, 20, 40 msec, etc.). In particular, until the divided clock CK2 is obtained,
Since the error time until the oscillator (32) starts to oscillate is included,
The operation start time of the load (11) desired by the user could not be set accurately. Moreover, since the initial setting circuit and the overcurrent detection circuit of the load (11) are independent in a state where CMOS transistors and bipolar transistors are mixed,
When integrating the photodetectors, there are problems that the pattern design becomes complicated and the chip area becomes large.

Therefore, an object of the present invention is to provide a photodetector suitable for integration in which the time from power-on to operation release of a load can be finely set.

[0008]

The present invention has been made to solve the above problems, and is characterized in that when a light receiving element receives an optical signal emitted from the light emitting element. , An amplifier that amplifies the current flowing through the light receiving element and extracts it as a voltage, a signal processing circuit that performs signal processing so that the load can be controlled to the output voltage of the amplifier, and an output voltage of the signal processing circuit A photodetector comprising: a switching transistor that switches in accordance with the present invention and supplies a current to the load; a first comparator that compares an input voltage of the switching transistor and a first reference voltage;
A charge / discharge circuit for charging or discharging according to the output voltage of the first comparator, and a second comparator for comparing the charge / discharge voltage of the charge / discharge circuit and a second reference voltage having hysteresis,
A gate that connects or disconnects the signal paths of the signal processing circuit and the switching transistor according to the output voltage of the second comparator, and the gate according to the output voltage of the second comparator at the time of initial setting after power-on. And a cutoff transistor forcibly cutting off the output path of the gate.

[0009]

According to the present invention, after the power is turned on, the cutoff transistor is made conductive in accordance with the output voltage of the second comparator until the charge / discharge voltage of the charge / discharge circuit reaches a predetermined value, forcing the output path of the gate. Then, the load is set to the initial state in which the load does not operate.

[0010]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a photodetector of the present invention. Incidentally, FIG.
Also, in FIG. 4, the same elements are designated by the same reference numerals. In FIG. 1, (41) is a cutoff transistor, the base is connected to the output terminal of the second comparator (22), the collector is connected to the output terminal of the AND gate (26), and the emitter is grounded. In FIG. 2, when the power supply V1 is turned on, the second reference voltage Vref2 starts to rise (dashed line), and following this, the terminal voltage b of the capacitor (21) starts to rise at the time constant T (solid line). ). Since the second reference voltage Vref2 is higher than the terminal voltage b of the capacitor (21) from the time when the power is turned on to the time t, the output of the second comparator (22) becomes high level and the cutoff transistor is turned on. (41) turns on. Here, the base-emitter voltage of the cutoff transistor (41) is obviously lower than the threshold voltage of the inverter (27). Therefore, in the process of the output of the second comparator (22) rising to the high level, the cut-off transistor (41) turns into the inverter (2).
It turns on early before 7) outputs low level. As a result, the AND gate (26) falls to the low level regardless of the indefinite output of the inverter (27), and the load (11)
Is set to an initial state in which it does not operate at an earlier timing than before after power is turned on. After the time t, the second reference voltage Vref2 becomes lower than the terminal voltage b of the capacitor (21), so that the output of the second comparator (22) becomes low level and the output of the inverter (27) becomes high level. Then, the cutoff transistor (41) is turned off. As a result, the AND gate (26) rises to a high level according to the output SP of the signal processing circuit (14), and the load (11) starts operating.

The operation after the initial setting of FIG. 1 will be described below with reference to the waveform chart of FIG. At time t0, the load (11)
Occurs and an overcurrent is generated, the voltage across the resistor (13) rises according to the overcurrent, and the base voltage of the switching transistor (12) becomes higher than the first reference voltage Vref1. Then, the output of the first comparator (17) becomes low level, and the transistor (19) is turned on. Therefore, the capacitor (21) discharges with a time constant T'determined by the on-resistance of the transistor (19) and the capacitance of the capacitor (21). At time t1, the capacitor (2
When the voltage across both ends of 1) drops to the second reference voltage Vref2 which is low, the output of the second comparator (22) becomes high level and A
The ND gate (26) is closed. Therefore, regardless of the output SP of the signal processing circuit (14), the transistor (2
8) (29) is turned off and the switching transistor (1
2) is also turned off. At this time, since the base voltage of the switching transistor (12) becomes 0V, the first comparator (1
The output of 7) becomes high level and the transistor (19)
Turns off. Therefore, the capacitor (21) is charged with the time constant T determined by the resistance value of the constant current source (18) and the capacity of the capacitor (21). At time t2, when the voltage across the capacitor (21) rises to the high second reference voltage Vref2, the output of the second comparator (22) becomes low level, and the AND gate (26) is opened. Therefore,
According to the output SP of the signal processing circuit (14), the transistors (28) and (29) are turned on, and the switching transistor (12) is also turned on. At this time, since the base voltage of the switching transistor (12) becomes higher than the first reference voltage Vref1, the output of the first comparator (17) becomes low level and the transistor (19) is turned on. Therefore, the capacitor (21) starts discharging again with the time constant T '.
Incidentally, this operation is repeated intermittently until the overcurrent of the load (11) is eliminated.

From the above, the time from power-on to the start of operation of the load (11) can be finely set as desired by the user who uses the photodetector, simply by appropriately selecting the capacitance of the capacitor (21). . Also, since it is composed of bipolar transistors while also having most of the overcurrent protection function and the initial setting function, when integrating the photodetector, the chip area becomes large and the pattern design becomes complicated. It will solve the problem.

[0013]

According to the present invention, the time from power-on to the start of load operation can be finely set as desired by the user who uses the photodetector, simply by appropriately selecting the time constant of the charge / discharge circuit. become. Also, since it is composed of bipolar transistors while also having most of the overcurrent protection function and the initial setting function, when integrating the photodetector, the chip area becomes large and the pattern design becomes complicated. The advantage is that the problem can be solved.

[Brief description of drawings]

FIG. 1 is a diagram showing a photodetector of the present invention.

FIG. 2 is a diagram showing an input waveform of a second comparator of FIGS. 1 and 4.

FIG. 3 is a diagram showing an entire photodetector.

FIG. 4 is a diagram showing a conventional overcurrent protection function.

FIG. 5 is a diagram showing waveforms at various points in FIGS. 1 and 4.

FIG. 6 is a diagram showing a conventional overcurrent protection function and an initial setting function.

FIG. 7 is a diagram showing the waveforms of FIG. 6;

[Explanation of symbols]

 (1) Light emitting diode (4) Light receiving diode (7) (10) Amplifier (11) Load (12) Switching transistor (14) Signal processing circuit (17) First comparator (19) Transistor (21) Capacitor (22) Second comparator (26) AND gate (41) Cutoff transistor

Claims (2)

[Claims] 1. An amplifier for amplifying a current flowing through the light receiving element and extracting the voltage as a voltage when the light receiving element receives an optical signal emitted from the light emitting element, and a state in which a load can be controlled by an output voltage of the amplifier. A signal processing circuit that performs signal processing, and a switching transistor that switches according to an output voltage of the signal processing circuit and supplies a current to the load, the input voltage of the switching transistor and A first comparator for comparing a first reference voltage; a charging / discharging circuit for charging or discharging according to an output voltage of the first comparator; a second reference voltage having a charging / discharging voltage of the charging / discharging circuit and hysteresis; And a second comparator for comparing the signal paths of the signal processing circuit and the switching transistor according to the output voltage of the second comparator. Over DOO and the photodetector, wherein the blocking transistor to forcibly shut off the output path of the gate in accordance with the output voltage of the second comparator in the initial setting after power, further comprising: a. 2. The output of the gate of the cutoff transistor according to the output voltage of the second comparator only during a period from when the power is turned on until the charge / discharge voltage of the charge / discharge circuit reaches the second reference voltage. The photodetector according to claim 1, wherein the photodetector blocks a path.