JP2004304334A - Semiconductor device and reset signal transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device (a regulator+a reset IC) by which the number of part items is reduced. <P>SOLUTION: The semiconductor device comprises: a constant voltage output circuit (a regulator circuit) formed on a semiconductor chip and outputting a specified voltage; and a reset circuit outputting a reset releasing signal when a power voltage reaches a set voltage. An issue mentioned above is achieved by using the semiconductor device having operation monitoring means (comparators 14, 15) monitoring the operation of the constant voltage output circuit (the regulator circuit) and a reset releasing signal generation means (a NAND gate 16) generating the reset releasing signal based on the monitoring result. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a reset signal sending method.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there is a semiconductor device (IC) using both a regulator circuit used for a power supply circuit of an AV device or the like and a reset circuit having a built-in delay circuit. In such a reset circuit of the IC, a reset is performed so that the microcomputer does not operate until the power supply voltage of the regulator circuit rises normally, and the reset is released after a certain time after the rise of the power supply voltage. I have.
[0003]
FIG. 10 shows a circuit diagram of an example of a conventional regulator circuit + reset circuit IC (hereinafter abbreviated as regulator + reset IC).
[0004]
In FIG. 10, this regulator + reset IC is configured as an integrated circuit in which a regulator circuit and a reset circuit are formed on the same semiconductor chip.
[0005]
The regulator circuit outputs a stable constant voltage _VOUT from an input voltage _VDD equal to or higher than a certain voltage. The input voltage V _DD is input to the reference voltage source V _REF 11 via the constant current source 4, and the output of the reference voltage source V _REF 11 is connected to the inverting input terminal (−) of the operational amplifier 1. A power supply voltage of _VDD is connected to one non-inverting input terminal (+) of the operational amplifier 1 via resistors R2 and R3 and a capacitor C1. The operational amplifier 1 multiplies the difference input voltage between the reference voltage source _VREF11 and the power supply voltage _VDD by the amplification factor A and outputs the result to the gate terminal of the P-channel MOS transistor 7b. Then, the voltage input to the gate terminal of the P-channel MOS transistor 7b is output from the V _OUT terminal as an output voltage.
[0006]
The operational amplifier 1 is connected to a grounded GND terminal, while being connected to the inverters 2 and 3 and the resistor R1. A CE terminal (chip enable input) is an ON / OFF control terminal for an output voltage. When the input voltage of the CE terminal is at a high level, the output voltage V _OUT is turned on, and when the input voltage is at a low level, the output voltage V _OUT is turned off. Become. When the input voltage at the CE terminal goes low, all circuit blocks are disabled and fall to the ground potential.
[0007]
In addition, a current limiting circuit (current limiter) 12 for suppressing a current at a set value is connected to an output of the operational amplifier 1 so that an overcurrent can be suppressed.
[0008]
The reset circuit includes a constant current source 15, a reference voltage source V _REF13 , a comparator 14 having hysteresis characteristics, and resistors R4 and R5 connected to a non-inverting input terminal (+) of the comparator 14, and one of the inverting input terminals ( − _REF is connected to V _REF 13. The output of the comparator 14 is connected to an inverter 6 for inverting the output voltage, and the output from the inverter 6 is connected to the gate of the P-channel MOS transistor 7c and the N-channel MOS transistor 7d. Further, the transmission delay time (TD) of the reset release signal can be set by the resistor Ra and the external capacitor CD connected to the _VDD terminal. The transmission delay time (TD) of the reset release signal is determined by the time constant of the resistance value of the resistor Ra and the capacitance value of the external capacitor, and can be arbitrarily varied.
[0009]
The comparator 14 monitors the power supply voltage V _DD , which is the input voltage of the regulator circuit, and when the potential difference V between the power supply voltage V _DD and V _REF (see the following equation (1)) reaches the threshold of the inverter 6, a P-channel MOS transistor 7c is turned on, and the high level of the power supply level (output of the reset release signal) is output from the RESET terminal. Conversely, when the potential difference V has not reached the threshold of the inverter 6, the N-channel MOS transistor 7d is turned on, and the output from the RESET terminal is at the ground level.
[0010]
V = V _DD e (t / CR) (1)
In the above equation (1), t (time until the threshold is reached) is
t = CRInV / V _DD [s]
Represented by
V _DD is the power supply voltage,
C is an external capacitor CD,
R is the resistance Ra,
V is the threshold potential,
Represents
[0011]
When a high-level reset release signal is output from the RESET terminal to, for example, the microcomputer, the reset is released on the microcomputer side and the microcomputer enters an operation state. In many cases, a coupling capacitor C _OUT for phase correction is connected to the terminal of V _OUT .
[0012]
In the above-mentioned conventional reset circuit, the transmission delay time (TD) of the reset release signal is determined by the time constant of the resistance value of the resistor Ra and the capacitance value of the external capacitor. There are more. For example, a method has been proposed in which a pulse transmission circuit for generating a delay time is built in and a reset signal is released when the number of pulses reaches a predetermined value (for example, see Patent Document 1).
[0013]
[Patent Document 1]
JP-A-6-301452
[Problems to be solved by the invention]
However, the reset circuit in the conventional regulator + reset IC described above has the following problems. That is, an external capacitor CD must be provided to set the delay time of the reset release signal. Since the setting of the delay time depends on the charging time of the external capacitor CD, when the delay time is set to be large, there is a problem that the capacity of the capacitor also increases and the circuit scale increases.
[0015]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device (regulator + reset IC) capable of reducing the number of components.
[0016]
[Means for Solving the Problems]
In order to solve the above problem, the present invention provides a constant voltage output circuit formed on a semiconductor chip for outputting a predetermined voltage, and a reset release when a power supply voltage reaches a set voltage. A semiconductor device comprising a reset circuit for outputting a signal, comprising: an operation monitoring means for monitoring the operation of the constant voltage circuit; and a reset release signal generating means for generating a reset release signal based on the monitoring result. It is characterized by:
[0017]
Further, the semiconductor device according to the present invention is the semiconductor device, wherein the operation monitoring means has a voltage monitoring means for monitoring an input voltage and an output voltage of the constant voltage circuit; When the input voltage and the output voltage are equal to or higher than a predetermined voltage, a reset release signal is generated.
[0018]
Further, the semiconductor device according to the present invention is the semiconductor device, wherein the operation monitoring means monitors a signal level of a control terminal connected to the constant voltage circuit and an input voltage or an output voltage of the constant voltage circuit. It is characterized by doing.
[0019]
Further, in the semiconductor device according to the present invention, preferably, the reset release signal generating unit includes a logical determination unit that logically determines a monitoring result output from the operation monitoring unit, A reset release signal is generated based on the
[0020]
According to the present invention, since the operation of the constant voltage circuit is monitored and the reset release signal is output when the operation state is good, the reset can be released at the same time when the load rises. As a result, the delay time until the reset release signal is output can be reduced, and external components for setting the delay time can be eliminated.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
FIG. 1 is a circuit diagram showing an example of a semiconductor device (regulator + reset IC) of the present invention.
[0023]
In this figure, this regulator + reset IC is composed of a regulator circuit and a reset circuit, and these are formed on the same semiconductor chip as an integrated circuit.
[0024]
The regulator circuit has a configuration and a function similar to those of FIG. 10 described above. The reset circuit has a comparator 15 that monitors the output voltage of the regulator circuit and a comparator 15 that monitors the output voltage of the regulator circuit in addition to the configuration of FIG. A NAND gate 16 is provided which performs a NAND operation on the monitoring result and the monitoring result of the output voltage from the comparator 15. The outputs from the comparators 14 and 15, that is, the input voltage of the regulator (the output of the comparator 14) and the output voltage (the output of the comparator 15) are input to the NAND gate 16 as described above. When both voltages are equal to or higher than the set voltage (both inputs are at high level), the output of the NAND 16 gate goes to low level, the P-channel MOS transistor 7c turns on, and the high level of the power supply level is output from the RESET terminal. . When a high level is output from the RESET terminal in this manner, the reset of the microcomputer power supply on the load side is released, and the microcomputer enters an operating state.
[0025]
FIG. 2 is a diagram showing the relationship between the input voltage-output voltage characteristics and the output timing of the reset release signal when the power is turned on at normal temperature (Ta = 25 ° C.) in the reset circuit.
[0026]
As shown in the figure, the reset release signal is output when both the input voltage and the output voltage of the regulator circuit rise, and as a result, the output of the reset release signal has a predetermined delay time from the rise of the input voltage. (This delay time is determined by the rise time of the regulator).
[0027]
The delay time (t) is represented, for example, by the following equation (2).
[0028]
t = C _OUT · V _OUT / Imax [s]
Here, C _OUT represents the output capacitance V _OUT of the coupling capacitor for phase correction, and represents the output voltage.
Imax represents a current limit current.
[0029]
In this example, the delay time from the rise of the input voltage to the output of the reset release signal is about 156 μs.
[0030]
FIG. 3 is a diagram showing the input voltage-output voltage characteristics and output timing of the reset release signal when the power is turned on in the reset circuit at a high temperature (Ta = 125 ° C.) and at a low temperature (Ta = −40 ° C.) in the reset circuit. FIG. As shown in the figure, even at high and low temperatures, the reset release signal is output when both the input voltage and the output voltage of the regulator rise. Incidentally, the delay time from the rise of the input voltage at the time of high temperature to the output of the reset release signal is about 100 μs, and at the time of low temperature, it is 224 μs.
[0031]
As described above, according to the reset circuit of the present invention, the input voltage and the output voltage of the regulator circuit are monitored, and when both voltages rise, the reset release signal is output. In other words, since the reset release signal is output after confirming that the V _OUT output voltage for turning on the microcomputer has risen reliably, only the input voltage is monitored, and after the input voltage has risen and a certain time has elapsed. The operation of the microcomputer can be further stabilized as compared with a conventional regulator circuit that outputs a reset release signal.
[0032]
Further, the resistor Ra and the external capacitor CD for setting the delay time until the reset release signal is output become unnecessary, and the mounting area can be reduced and the cost can be reduced by reducing the number of components.
[0033]
Further, when the output voltage of the regulator rises, the reset release signal output is reliably output, so that it is not necessary to secure a fixed time after the input voltage rises, unlike a conventional reset circuit, and as a result, The start-up time of the microcomputer can be reduced.
[0034]
(Modification)
The present invention is not limited to the above embodiment, and various modifications are possible.
[0035]
(1) In the above embodiment, the input voltage and the output voltage of the regulator circuit are monitored, and the output logic of the reset release signal is determined by the logic of the NAND gate 16 that takes the NAND of them. Embodiments of the invention are not limited to this, and may have modified logic. For example, an OR gate 17 can be used instead of the NAND gate circuit 16 (see FIG. 5). In this case, if the inputs to the OR gate 17 are A and B, A is the input voltage, and B is the output voltage, when A is the normal input voltage and B is the normal output voltage (A = 1, B = 1), the logical output of the OR gate is "1", that is, goes to a high level, the N-channel MOS transistor 7d turns on, and the RESET terminal goes to the high level of the power supply level.
[0036]
(2) The output logic of the reset release signal may be an open-drain output type in which the drain electrode of the N-channel MOS transistor 7e is directly exposed, as shown in FIG.
[0037]
(3) Further, as shown in FIG. 7, the current limit and the _VOUT voltage may be detected, and the output logic of the reset release signal may be determined based on the detection result.
[0038]
(4) As shown in FIG. 8, the reset release is detected by detecting the level of the output voltage on / off control signal from the CE terminal and the _VDD voltage, and taking the NAND of these (NAND gate 16). The output logic of the signal may be determined.
(5) Also, as shown in FIG. 9, the reset release is detected by detecting the level of the output voltage on / off control signal from the CE terminal and the V _OUT voltage and taking the NAND of these (NAND gate 16). The output logic of the signal may be determined.
[0039]
【The invention's effect】
As described above, according to the present invention, the input voltage and the output voltage of the regulator circuit are monitored, and when both voltages rise, the reset release signal is output. That is, the reset release signal is output after confirming that the _VOUT output voltage for turning on the microcomputer has definitely risen, so that the reset can be released simultaneously with the rise of the microcomputer. As a result, the delay time until the reset release signal is output can be reduced, external components for setting the delay time can be eliminated, and the mounting area and cost can be reduced by reducing the number of components. .
[0040]
In the above example, the regulator circuit corresponds to the constant voltage output circuit, the functions of the comparators 14 and 15 correspond to the operation monitoring unit and the voltage monitoring unit, and the logic determination function of the NAND gate 16 corresponds to the reset release signal generation unit. The function of the comparator 15 corresponds to the control terminal output level monitoring means. Further, the logical operation function of the NAND gate 16 and the OR gate 17 corresponds to a logical determination unit.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an example of a semiconductor device (regulator + reset IC) of the present invention.
FIG. 2 is a diagram showing a relationship between an input voltage-output voltage characteristic and an output timing of a reset release signal when power is turned on at a normal temperature (Ta = 25 ° C.) in a reset circuit.
FIG. 3 is a diagram illustrating a relationship between an input voltage-output voltage characteristic and a reset release signal output timing when power is turned on at a high temperature (Ta = 125 ° C.) in a reset circuit.
FIG. 4 is a diagram showing a relationship between an input voltage-output voltage characteristic and a reset release signal output timing when power is turned on at a low temperature (Ta = −40 ° C.) in the reset circuit.
FIG. 5 is a view showing a modification (No. 1) of the embodiment of the semiconductor device according to the present invention.
FIG. 6 is a view showing a modification (No. 2) of the embodiment of the semiconductor device according to the present invention.
FIG. 7 is a diagram showing a modification (3) of the embodiment of the semiconductor device according to the present invention.
FIG. 8 is a diagram showing a modification (4) of the embodiment of the semiconductor device according to the present invention.
FIG. 9 is a view showing a modification (5) of the embodiment of the semiconductor device according to the present invention.
FIG. 10 is a circuit diagram of a conventional semiconductor device (regulator + reset IC).
[Explanation of symbols]
R1, R2, R3, R4, R5, R6, R7, Ra Resistance C1 Capacitor CD Delay time generation capacitor C _OUT coupling capacitor 1 Operational amplifier 2, 3, 6 Inverter 4, 5 Constant current source 7a-7e MOS transistor 11, 13 V _REF (reference voltage source)
12 Current limiter 14, 15 Comparator 16 NAND gate 17 OR gate

Claims (5)

In a semiconductor device including a constant voltage output circuit formed on a semiconductor chip and outputting a predetermined voltage, and a reset circuit that outputs a reset release signal when a power supply voltage reaches a set voltage,
Operation monitoring means for monitoring the operation of the constant voltage circuit,
A reset release signal generating means for generating a reset release signal based on the monitoring result. The semiconductor device according to claim 1,
The operation monitoring means,
Having voltage monitoring means for monitoring the input voltage and the output voltage of the constant voltage circuit,
The reset release signal generating means includes:
A semiconductor device, wherein a reset release signal is generated when the input voltage and the output voltage are equal to or higher than predetermined voltages. The semiconductor device according to claim 1,
The operation monitoring means,
A signal level of a control terminal connected to the constant voltage circuit,
A semiconductor device monitoring an input voltage or an output voltage of the constant voltage circuit. The semiconductor device according to claim 1, wherein:
The reset release signal generating means includes:
Logic determining means for logically determining a monitoring result output by the operation monitoring means,
A semiconductor device, which generates a reset release signal based on a result of the logical determination. A reset signal sending method in a semiconductor device, comprising: a constant voltage output circuit formed on a semiconductor chip and outputting a predetermined voltage; and a reset circuit outputting a reset release signal when a power supply voltage reaches a set voltage.
Monitor the input voltage and output voltage of the constant voltage circuit,
A reset signal sending method, wherein a reset release signal is generated when the input voltage and the output voltage are equal to or higher than predetermined voltages.

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