JP2002323518A - Voltage detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage detecting circuit capable of performing measurement using a binary research technique. SOLUTION: At the time of detecting reset voltage, a first test signal TS1 is set to high-level and a second test signal TS2 is set to low level, NMOS transistor QN2 is kept from turning on, and NAND circuits 29, 31, 32 are respectively operated as an inverter, and an output end of the inverter 22 is connected to an output terminal OUT through five inverters. At the time of detecting the reset release voltage, both the first test signal TS1 and the second test signal TS2 are set to high level, NMOS transistor QN1 is turned on, and NAND circuit 28 and NAND circuit 31 are respectively operated as an inverter. The output end of the inverter 21 is connected to an output terminal OUT through three inverters.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage detecting circuit for detecting a voltage value of an input voltage, generating and outputting a binary signal corresponding to the detected voltage value, and more particularly to a voltage detecting circuit for performing an operation test. The present invention relates to a voltage detection circuit including a test circuit.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an example of a conventional voltage detection circuit. 4 outputs a low-level reset signal when an input voltage Vin input from an input terminal IN falls below a predetermined reset voltage, and outputs the reset signal when the input voltage Vin exceeds a predetermined reset release voltage. And outputs a high-level reset release signal for releasing the reset operation. When detecting the power supply voltage Vdd, the input voltage Vin is the power supply voltage Vdd.

In FIG. 4, a predetermined reference voltage Vr is compared with a divided voltage Vfb obtained by dividing an input voltage Vin by resistors 102 to 104 by a voltage comparator 105 formed by an operational amplifier. A voltage corresponding to the comparison result is output from the voltage comparator 105. Note that the reference voltage Vr may be externally input, or the voltage detection circuit 100
May be provided by providing a reference voltage generation circuit section inside the.

When the divided voltage Vfb becomes equal to or lower than the reference voltage Vr, the output of the voltage comparator 105 goes high, turning on an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) 106 to further reduce the divided voltage Vfb. By lowering it, oscillation of the voltage comparator 105 is prevented. When the output terminal of the voltage comparator 105 becomes high level, the P-channel MOS transistor (hereinafter, referred to as PMOS transistor) 107 turns off and the NMOS transistor 109 turns on. For this reason, the capacitor 1 in which the electric charge is stored
10 starts discharging via the connection terminal CD and the NMOS transistor 109, and the voltage Va at the point a decreases.

Here, threshold value α of inverter 111 is higher than threshold value β of inverter 112, and a
When the voltage Va at the point decreases and β <Va ≦ α, only the output terminal of the inverter 111 rises from a low level to a high level. At this point, the output terminal of the inverter 112 remains at the low level. An output signal of the inverter 111 is input to an input terminal of a NAND circuit 114 which is one input terminal of a reset set flip-flop (hereinafter, referred to as an RS flip-flop) 116 formed by the NAND circuits 114 and 115. . The output signal of the inverter 112 is input via the inverter 113 to the input terminal of the NAND circuit 115, which is the other input terminal of the RS flip-flop 116.

[0006] From this, the RS flip-flop 11
6, the input terminals of the RS 6 become high level, the RS flip-flop 116 enters the latch state, and the non-inverting output terminal Q of the RS flip-flop 116 remains at high level. Therefore, the high-level signal is output from the inverter 11
It is output from the output terminal OUT via 7 and 118.
When the voltage Va at the point a further decreases and Va ≦ β, the output terminal of the inverter 112 also rises from a low level to a high level. Therefore, the non-inverting output terminal Q of the RS flip-flop 116 falls to a low level, and the low-level signal is output from the output terminal OUT via the inverters 117 and 118.

Next, when the divided voltage Vfb exceeds the reference voltage Vr, the output of the voltage comparator 105 goes low,
The NMOS transistor 106 turns off and enters a cutoff state. When the output terminal of the voltage comparator 105 becomes low level, the PMOS transistor 107 is turned on and NM
The OS transistor 109 turns off. Therefore, the capacitor 110 is composed of the PMOS transistor 107 and the resistor 1
08, the power supply voltage Vdd is applied to start charging, and the voltage Va at the point a increases.

When the voltage Va at the point a rises and β ≦ Va <α, only the output terminal of the inverter 112 falls from the high level to the low level. At this point, inverter 1
The output terminal of No. 11 remains at the high level. Therefore, each input terminal of the RS flip-flop 116 is at a high level, the RS flip-flop 116 is in a latching state, and the non-inverting output terminal Q of the RS flip-flop 116 remains at a low level. Therefore, the low-level signal is output from the output terminal OUT via the inverters 117 and 118. Further, when the voltage Va at the point a rises and α ≦ Va, the output terminal of the inverter 111 rises from a high level to a low level. For this reason, RS
The non-inverting output terminal Q of the flip-flop 116 rises to a high level, and the high-level signal
The signal is output from the output terminal OUT via 17 and 118.

[0009]

When such a voltage detection circuit 100 is manufactured as a product, a reset voltage value, a reset release voltage value, and a hysteresis width value are usually provided as product standards. Has been tested to see if it meets the standard. However, in the voltage detection circuit as described above, the power supply voltage Vdd
Since the hysteresis exists in the change of the signal level of the output terminal OUT with respect to the fluctuation of the output terminal OUT, that is, the reset voltage value and the reset release voltage value, accurate measurement is performed by using the binary search method as shown in FIG. I couldn't do that. For this reason, the measurement is performed by using the forward voltage sweep method for measurement as shown in FIG. 6, but there is a problem that the test time becomes long.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can measure a reset voltage value and a reset release voltage value in response to an external test signal without being affected by hysteresis. An object of the present invention is to provide a voltage detection circuit capable of performing a measurement using a binary search technique by providing a test circuit having such a configuration.

[0011]

A voltage detecting circuit according to the present invention detects an input voltage, and generates and outputs a binary signal corresponding to the detected voltage value. A voltage comparison between a divided voltage obtained by dividing the voltage and a predetermined reference voltage is performed, and the comparison result is output. When the divided voltage falls below the reference voltage, the divided voltage of the input voltage is changed to change the divided voltage. The charge and discharge control for a predetermined capacitor is performed in accordance with a comparison result from the input voltage detection unit that reduces the charge voltage, and the capacitor is charged with a predetermined time constant to discharge the charge time. A delay time control unit for delaying the delay time so as to be longer than a time, and a charge / discharge voltage of a capacitor of the delay time control unit is input to each logic circuit having a different threshold value, and each output of each logic circuit is output. A hysteresis control unit that outputs a signal through a flip-flop and forms a hysteresis with respect to the charge / discharge voltage. When a predetermined first test signal is input from the outside during an operation test, the input voltage detection unit The hysteresis control unit exclusively outputs the signal from one of the logic circuits input to the flip-flop, while keeping the voltage division ratio of the input voltage constant irrespective of the value of the divided voltage.

Further, at the time of an operation test, a predetermined second
When a test signal is further input, the input voltage detection unit changes the division ratio of the input voltage to reduce the divided voltage regardless of the value of the divided voltage, and the hysteresis control unit inputs the signal to the flip-flop. The signal from the other logic circuit is exclusively output.

[0013] Specifically, the flip-flop has 3
It constitutes an RS flip-flop formed by an input logic circuit.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a circuit diagram illustrating an example of a voltage detection circuit according to an embodiment of the present invention. During normal operation, the voltage detection circuit 1 of FIG. 1 outputs a low-level reset signal when the input voltage Vin input from the input terminal IN falls below a predetermined reset voltage, and outputs the reset signal when the input voltage Vin exceeds a predetermined reset release voltage. It outputs a high-level reset release signal for releasing the reset operation by the signal. When detecting the power supply voltage Vdd, the input voltage Vin is the power supply voltage Vdd.

In FIG. 1, a voltage detection circuit 1 includes an input voltage detection section 2 for detecting a state of an input voltage Vin input to an input terminal IN with respect to a preset reset voltage and a reset release voltage, Detector 2
The delay time control unit 3 that outputs the detection result by delaying only when the input voltage Vin is equal to or higher than the reset release voltage with respect to the detection result of And a hysteresis control section 4 for providing hysteresis.

The input voltage detector 2 includes a voltage comparator 12 composed of an operational amplifier, a NOR circuit 13, an inverter 14,
It is composed of channel type MOS transistors (hereinafter referred to as NMOS transistors) QN1 and QN2 and resistors R1 to R3. Between the input terminal IN and the ground, resistors R1 to R1
R3 is connected in series, the connection between the resistors R1 and R2 is connected to the non-inverting input terminal of the voltage comparator 12, and the input voltage Vi
The divided voltage Vfb obtained by dividing n is input to the non-inverting input terminal of the voltage comparator 12. A predetermined reference voltage Vr is input to an inverting input terminal of the voltage comparator 12.
Performs a voltage comparison between the reference voltage Vr and the divided voltage Vfb and outputs the comparison result. The reference voltage Vr may be input from the outside, or may be generated by providing a reference voltage generation circuit inside the voltage detection circuit 1.

The output signal of the voltage comparator 12 is output to one input terminal of a NOR circuit 13 and the output signal of the inverter 1
4 is output to the delay time control unit 3 via the NOR circuit 1
3 is connected to an external first test signal TS1.
Is entered. NMOS transistors QN1 and QN2 are connected in parallel between the connection between the resistors R2 and R3 and the ground, and a second test signal TS2 is input to the gate of the NMOS transistor QN1 from the outside.
The output signal of the NOR circuit 13 is input to the gate of the NMOS transistor QN2.

Next, the delay time control section 3 supplies the power supply voltage Vd
P-channel MOS transistor (hereinafter referred to as a PMOS transistor) QP1 connected between d and ground.
And a series circuit of a resistor R4 and an NMOS transistor QN3, and a capacitor C1 connected between the connection terminal CD and the ground. PMOS transistor QP1
And the gates of the NMOS transistor QN3 are connected to each other.
2 is input. Further, a capacitor C1 is connected between a connection point p between the resistor R4 and the NMOS transistor QN3 and the ground via a connection terminal CD.

Next, the hysteresis control unit 4 includes inverters 21 to 27, three-input NAND circuits 28 and 29 forming a reset set flip-flop (hereinafter, referred to as RS flip-flop) 30, and two-input NAND circuits 28 and 29. NAND
It is composed of circuits 31, 32 and a NOR circuit 33. The connection part p is connected to the corresponding input terminal of the NAND circuit 28 via the inverter 21 and to the corresponding input terminal of the NAND circuit 29 via the inverters 22 and 23. The output signal of the NAND circuit 28 is output from the corresponding input terminal of the NAND circuit 29 and the NAND
Input to one input terminal of the circuit 31,
An output signal of the circuit 29 is input to a corresponding input terminal of the NAND circuit 28 and one input terminal of the NAND circuit 32, respectively.

A first external test signal TS1 is input to one input terminal of a NOR circuit 33 via an inverter 26, and a second external test signal TS2 is input to the other input terminal of the NOR circuit 33. Have been. Further, the second test signal TS2 is input to the corresponding input terminal of the NAND circuit 29 via the inverter 25. The output signal of the NOR circuit 33 is input to the corresponding input terminal of the NAND circuit 28 via the inverter 24 and to the other input terminal of the NAND circuit 32. The output signal of the NAND circuit 32 is input to the other input terminal of the NAND circuit 31, and the output signal of the NAND circuit 31 is output from the output terminal OUT via the inverter 27. In addition,
In FIG. 1, each element except the capacitor C1 is an IC.
, The capacitor C1 is connected via the connection terminal CD.

In such a configuration, the operation of each section during the normal operation in which the first test signal TS1 and the second test signal TS2 are both at the low level will be described. When the divided voltage Vfb becomes equal to or lower than the reference voltage Vr, the output terminal of the voltage comparator 12 becomes low level. First test signal TS
Since the first and second test signals TS2 are both at the low level, the NMOS transistor QN1 is turned off and cut off, and the output terminal of the NOR circuit 13 is at the high level.

As a result, the NMOS transistor QN2 is turned on and becomes conductive, and the divided voltage Vfb is reduced by the following (1).
The oscillation of the voltage comparator 12 is prevented by further reducing the equation to the equation (2). Vfb = {(R2 + R3) / (R1 + R2 + R3)} × Vin (1) Vfb = {R2 / (R1 + R2)} × Vin (2) Note that the above equation (1) and In the formula (2), R1 to R3
Indicates the resistance values of the corresponding resistors R1 to R3.

When the output terminal of the voltage comparator 12 goes low and the output terminal of the inverter 14 goes high, PM
The OS transistor QP1 turns off and the NMOS transistor QN3 turns on. For this reason, the capacitor C1 in which the charge has been accumulated starts discharging via the NMOS transistor QN3, and the voltage Vp at the point p decreases.

Here, since both the first test signal TS1 and the second test signal TS2 are at low level, NO
The output terminal of the R circuit 33 goes low, the other input terminal of the NAND circuit 32 goes low, and the output terminal of the inverter 24 goes high. Therefore, the three-input NAND circuit 28 operates as a two-input NAND circuit including an input terminal to which the output terminal of the inverter 21 is connected and an input terminal to which the output terminal of the NAND circuit 29 is connected.
Similarly, since the output terminal of the inverter 25 is at a high level, the three-input NAND circuit 29 includes an input terminal connected to the output terminal of the inverter 23 and an input terminal connected to the output terminal of the NAND circuit 28. It operates as an input NAND circuit.

On the other hand, threshold value Vth1 of inverter 21
Is higher than the threshold value Vth2 of the inverter 22, and the voltage Vp at the point p decreases to Vth2 <Vp ≦ Vth
When it becomes 1, only the output terminal of the inverter 21 rises from the low level to the high level. At this point, the output terminal of the inverter 22 remains at the low level. Inverter 2
The output signal of “1” is input to a corresponding input terminal of the NAND circuit 28 which forms one input terminal of the RS flip-flop 30. The output signal of the inverter 22 is input via the inverter 23 to the corresponding input terminal of the NAND circuit 29 which is the other input terminal of the RS flip-flop 30.

From this, the RS flip-flop 30
, Both input terminals of the NAND circuit 28 forming the non-inverted output terminal Q of the RS flip-flop 30 are at a high level, and the inverted output of the RS flip-flop 30 is at a high level. The output terminal of the NAND circuit 29 forming the terminal / Q remains at the low level. Therefore, a high-level signal at the output terminal of the NAND circuit 28 is output to one input terminal of the NAND circuit 31, and a low-level signal at the output terminal of the NAND circuit 29 is output to one input terminal of the NAND circuit 32. Is output.

Therefore, the output terminal of the NAND circuit 32 goes high, the input terminals of the NAND circuit 31 go high, the output terminal of the NAND circuit 31 goes low, and the output terminal of the inverter 27 That is, a high-level reset release signal is output from the output terminal OUT, and at this time, a low-level reset signal is not yet output from the output terminal OUT.

Further, the voltage Vp at the point p decreases and Vp ≦ V
At th2, the output terminal of the inverter 22 also rises from a low level to a high level. For this reason, the NAND circuit 28 forming the non-inverting output terminal Q of the RS flip-flop 30
Falls to a low level, and the output terminal of the NAND circuit 29 forming the inverted output terminal / Q of the RS flip-flop 30 rises to a high level. From this, N
The output terminal of the AND circuit 31 rises to a high level,
A low-level reset signal is output from the output terminal OUT via the inverter 27.

FIG. 2 shows the input voltage V due to such an operation.
FIG. 3 is a diagram showing waveform examples of a voltage Vp at points in and p and a voltage Vo at an output terminal OUT. As can be seen from FIG. It can be seen that when the voltage Vfb falls below the reference voltage Vr, a low-level reset signal is immediately output from the output terminal OUT.

Next, when the divided voltage Vfb exceeds the reference voltage Vr, the output terminal of the voltage comparator 12 goes high, the output terminal of the inverter 14 goes low, and the PMO
The S transistor QP1 turns on and the NMOS transistor QN3 turns off. Therefore, the power supply voltage Vdd
Charging of the capacitor C1 is started via the OS transistor QP1 and the resistor R4, and the voltage Vp at the point p slowly increases.

When the voltage Vp at the point p satisfies Vp ≦ Vth2, the low-level reset signal is output from the output terminal OUT as described above. When the voltage Vp at the point p rises and becomes Vth2 <Vp ≦ Vth1, the inverter 22
Only the output end of the device falls from the high level to the low level. At this point, the output terminal of the inverter 21 remains at the high level. Therefore, the corresponding input terminal of the NAND circuit 28 forming one input terminal of the RS flip-flop 30 is at the high level, and the corresponding input terminal of the NAND circuit 29 forming the other input terminal of the RS flip-flop 30 is at the low level. Rises to a high level.

From this, the RS flip-flop 30
Is in a latch state, the output terminal of the NAND circuit 28 forming the non-inverted output terminal Q of the RS flip-flop 30 is at a low level, and the output terminal of the NAND circuit 29 forming the inverted output terminal / Q of the RS flip-flop 30 is at the high level. Remains. Therefore, a low-level signal at the output terminal of the NAND circuit 28 is output to one input terminal of the NAND circuit 31, the output terminal of the NAND circuit 31 becomes high level, and a low-level reset signal is output from the output terminal OUT. It remains as it was.

The voltage Vp at the point p further rises and Vth1 <
When the voltage becomes Vp, the output terminal of the inverter 21 also falls from the high level to the low level. For this reason, the output terminal of the NAND circuit 28 that forms the non-inverted output terminal Q of the RS flip-flop 30 rises from low level to high level,
NAND forming inverted output terminal / Q of flip-flop 30
The output terminal of the circuit 29 falls from the high level to the low level. A high-level signal at the output terminal of the NAND circuit 28 is output to one input terminal of the NAND circuit 31.
The low-level signal at the output terminal of the NAND circuit 29 is output to one input terminal of the NAND circuit 32,
The output terminal of the ND circuit 32 is at a high level. As described above, each input terminal of the NAND circuit 31 is at a high level, the output terminal of the NAND circuit 31 is at a low level, and a high-level reset release signal is output from the output terminal OUT.

FIG. 3 shows the input voltage V due to such an operation.
FIG. 5 is a diagram illustrating waveform examples of a voltage Vp at points in and p and a voltage Vo at an output terminal OUT. As can be seen from FIG. 3, it takes time to charge the capacitor C1, and the input voltage Vin
Rises and the divided voltage Vfb exceeds the reference voltage Vr, a high-level reset release signal may be output from the output terminal OUT after a lapse of time according to the time constant of the capacitor C1 and the resistor R4. I understand.

Next, the operation during the test operation will be described. First, a case where the first test signal TS1 is at a high level and the second test signal TS2 is at a low level will be described. When the first test signal TS1 goes high, the output of the NOR circuit 13 goes low regardless of the signal level of the output of the voltage comparator 12. Therefore, the NMOS transistor QN2 is turned off and cut off, and the divided voltage Vfb does not decrease in accordance with the output level of the voltage comparator 12.

When the first test signal TS1 goes high, the input ends of the NOR circuit 33 go low, so that the output ends go high. Therefore, one input terminal of the NAND circuit 32 goes high, the output terminal of the inverter 24 goes low, and the output terminal of the NAND circuit 28
It goes to a high level irrespective of the signal level of each output terminal of 1 and 23. That is, the NAND circuit 29, the NAND circuit 31, and the NAND circuit 32 each operate as an inverter, and the output terminal of the inverter 22 is connected to the output terminal OUT via the five inverters. From these facts, by detecting the change in the signal level of the output terminal OUT by varying the input voltage Vin,
The detection of the threshold value Vth2 of the inverter 22, that is, the detection of the reset voltage can be performed without being affected by the hysteresis.

Next, the case where both the first test signal TS1 and the second test signal TS2 are at the high level will be described. The operation of each circuit when the first test signal TS1 goes to a high level is as described above, but when the second test signal TS2 goes to a high level, the NMO
The S transistor QN1 is turned on to be in a conductive state, and the output terminals of the inverter 25 and the NOR circuit 33 are each at a low level. Therefore, the NMOS transistor QN
1 is an NMOS transistor QN2 during normal operation.
And the output terminal of the NAND circuit 29 is
It goes to a high level irrespective of the signal level of each output terminal of the inverters 21 and 23.
Also goes high.

That is, the NAND circuit 28 and the NAND circuit
Each of the circuits 31 operates as an inverter, and the output terminal of the inverter 21 is connected to the output terminal OUT via three inverters. From these facts, by detecting the change in the signal level of the output terminal OUT by varying the input voltage Vin, the threshold value Vth1 of the inverter 21 can be detected without being affected by the hysteresis, ie, the reset release voltage can be detected. It can be performed.

As described above, by adding only a circuit that performs logic signal processing as a test circuit, the reset voltage and the reset release voltage can be easily detected without being affected by hysteresis. A binary search method can be used for detecting the reset release voltage. In a system LSI in which a digital circuit and an analog circuit are mixed, a control terminal for test setting in another block already exists, and can be dealt with only by adding a test circuit without newly providing a test terminal. . For these reasons, there is no influence on chip cost such as an increase in chip area, the test time can be shortened, and the cost for performing an operation test can be reduced.

[0040]

As apparent from the above description, according to the voltage detection circuit of the present invention, when a predetermined first test signal is input from the outside during an operation test, the input voltage detection section
The voltage dividing ratio of the input voltage is kept constant irrespective of the value of the divided voltage, and the hysteresis control section exclusively outputs the signal from one of the logic circuits input to the flip-flop. From this, it is possible to easily detect the voltage set for detection without being affected by hysteresis at the time of an operation test by simply adding a simple circuit. Can be used, the operation test time can be shortened, and the cost can be reduced.

Further, at the time of an operation test, a predetermined second
When the test signal is further input, the input voltage detection unit changes the division ratio of the input voltage regardless of the value of the divided voltage to reduce the divided voltage, and the hysteresis control unit is input to the flip-flop. The signal from the other logic circuit is exclusively output. From this, by simply adding a simple circuit, it is possible to easily detect each voltage set for performing detection without being affected by hysteresis during an operation test, and to detect each set voltage. Since the binary search method can be used, the operation test time can be greatly reduced, and the cost for performing the operation test can be further reduced.

Specifically, the flip-flop has 3
Since the RS flip-flop formed by the input logic circuit is used, each voltage set to perform detection without being affected by hysteresis can be easily detected only by adding a simple logic circuit. can do.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a voltage detection circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of waveforms of respective units when the input voltage Vin in the voltage detection circuit illustrated in FIG. 1 is reduced.

FIG. 3 is a diagram showing an example of waveforms of respective units when the input voltage Vin in the voltage detection circuit shown in FIG. 1 rises.

FIG. 4 is a circuit diagram showing an example of a conventional voltage detection circuit.

FIG. 5 is a diagram showing an example of a measurement result using a binary search method.

FIG. 6 is a diagram illustrating an example of a measurement result using a voltage sweep method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 voltage detection circuit 2 input voltage detection unit 3 delay time control unit 4 hysteresis control unit 30 RS flip-flop

Continued on the front page F term (reference) 2G035 AA00 AB02 AC01 AC17 AD00 AD03 AD10 AD13 AD20 AD23 AD25 AD27 5H410 CC02 DD02 EA11 EA12 EB16 EB37 FF03 5J055 AX40 BX42 CX00 DX01 EX23 EY01 EY10 EZ07 EZ09 EZ10 G01 EZ25

Claims (3)

[Claims] 1. A voltage detecting circuit for detecting an input voltage and generating and outputting a binary signal corresponding to the detected voltage value, wherein a divided voltage obtained by dividing the input voltage and a predetermined voltage An input voltage detection unit that performs voltage comparison with a reference voltage, outputs the comparison result, and changes the division ratio of the input voltage to reduce the divided voltage when the divided voltage is equal to or less than the reference voltage; A delay time control unit that performs charge / discharge control on a predetermined capacitor in accordance with the comparison result from the unit, charges the capacitor with a predetermined time constant, and delays the charge time to be longer than the discharge time. And inputting the charge / discharge voltage of the capacitor of the delay time control unit to each logic circuit having a different threshold value, and outputting each output signal of each logic circuit via a flip-flop. A hysteresis control unit for forming a hysteresis with respect to a discharge voltage, wherein when a predetermined first test signal is input from the outside during an operation test, the input voltage detection unit inputs the signal regardless of the value of the divided voltage. A voltage detection circuit, wherein the voltage division ratio is made constant, and the hysteresis control section exclusively outputs a signal from one of the logic circuits input to the flip-flop. 2. When a predetermined second test signal is further input from the outside during an operation test, the input voltage detector changes the divided voltage ratio of the input voltage regardless of the value of the divided voltage to change the divided voltage. 2. The voltage detection circuit according to claim 1, wherein the hysteresis control unit exclusively outputs the signal from the other logic circuit input to the flip-flop while reducing the voltage. 3. The voltage detection circuit according to claim 1, wherein the flip-flop is an RS flip-flop formed of a three-input logic circuit.