JP2009044434A - Reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce circuit scale of a reset circuit. <P>SOLUTION: The present invention relates to a reset circuit which outputs a reset signal indicating a reset instruction or reset cancel to a circuit using a power supply voltage in accordance with a voltage level of the power supply voltage, including: a voltage detection circuit for detecting whether the power supply voltage is higher than a predetermined first threshold level; a charging/discharging circuit which charges a capacitor in a case where the power supply voltage is higher than the first threshold level, and discharges the capacitor in a case where the power supply voltage is lower than the first threshold level, based on a detection result of the voltage detection circuit; and an MOS inverter circuit which changes the reset signal to one logic level indicating the reset instruction in a case where a voltage of the capacitor is lower than a predetermined second threshold level, and changes the reset signal to another logic level indicating the reset cancel in a case where the voltage of the capacitor is higher than the second threshold level. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a reset circuit.

  When driving a circuit such as a microcomputer using a power supply voltage generated by a regulator, a reset circuit may be used to perform a reset instruction or reset release to the circuit such as the microcomputer according to the voltage level of the power supply voltage. It is common (for example, patent document 1).

  FIG. 4 is a diagram illustrating a configuration example of a general reset circuit. The reset circuit 100 is a circuit that outputs a reset signal RESET indicating a reset instruction or reset release to the microcomputer 120 driven by the power supply voltage Vdrv generated by the regulator 110 according to the voltage level of the power supply voltage Vdrv. .

  For example, when the power is turned on and the regulator 110 starts operating, the power supply voltage Vdrv starts to rise. While the voltage obtained by dividing the power supply voltage Vdrv by the resistors R11 and R12 is lower than the reference voltage Vref1 output from the power supply 132, the output signal of the comparator 130 is at the H level. When the output signal of the comparator 130 is H level, the NPN transistor Q11 is turned on, the constant current I generated by the NPN transistor Q12, the PNP transistors Q13, Q14, and the resistor R13 flows into Q11, and the capacitor C11 is not charged. Therefore, the reset signal RESET output from the comparator 131 is at an H level indicating a reset instruction, and the microcomputer 120 is maintained in the reset state.

  Thereafter, when the power supply voltage Vdrv reaches a predetermined level corresponding to the reference voltage Vref1, the output signal of the comparator 130 becomes L level, and the NPN transistor Q11 is turned off. As a result, when the capacitor C11 starts to be charged by the constant current I and the voltage of the capacitor C11 reaches the reference voltage Vref2 output from the power supply 133, the reset signal RESET output from the comparator 131 becomes L level indicating reset release. The reset of the microcomputer 120 is released. If the reset is released immediately after the power supply voltage Vdrv reaches a predetermined level corresponding to the reference voltage Vref1, the reset of the microcomputer 120 may be illegally released due to noise. For this reason, the reset circuit 100 does not change the reset signal RESET immediately after the power supply voltage Vdrv reaches a predetermined level corresponding to the reference voltage Vref1, but instead has a delay time until the voltage of the capacitor C11 reaches the reference voltage Vref2. Provided.

In addition, after the reset is released, the power supply voltage Vdrv may be lower than a predetermined level corresponding to the reference voltage Vref1 due to some influence. In this case, the output signal of the comparator 130 becomes H level, and the NPN transistor Q11 is turned on. When the NPN transistor Q11 is turned on, the capacitor C11 is discharged, the reset signal output from the comparator 131 changes to H level, and the microcomputer 120 is reset.
JP-A-6-29807

As described above, in the reset circuit 100, in order to provide a delay time, a constant current is generated by the NPN transistors Q11 and Q12, the PNP transistors Q13 and Q14, and the resistor R13, and the voltage determination is performed by the comparator 131 including about 10 elements. Has been done. That is, in the reset circuit 100, the number of elements necessary for providing the delay time is large, which causes a cost increase.
The present invention has been made in view of the above problems, and an object thereof is to provide a reset circuit having a small circuit scale.

  In order to achieve the above object, a reset circuit of the present invention is a reset circuit that outputs a reset signal indicating a reset instruction or reset release to a circuit driven by the power supply voltage in accordance with the voltage level of the power supply voltage. A voltage detection circuit for detecting whether the power supply voltage is higher than a predetermined first threshold level; and a capacitor when the power supply voltage is higher than the first threshold level based on a detection result of the voltage detection circuit. A charge / discharge circuit for charging and discharging the capacitor when the power supply voltage is lower than the first threshold level; and when the voltage of the capacitor is lower than a predetermined second threshold level, the charge level is set to one logic level indicating a reset instruction. When the reset signal is changed and the voltage of the capacitor is higher than the second threshold level, the other logic level indicating reset release is displayed. The fact that and a MOS inverter circuit for changing a reset signal to.

  A reset circuit with a small circuit scale can be provided.

  FIG. 1 is a diagram showing a configuration of a reset circuit according to an embodiment of the present invention. The reset circuit 10 is a circuit that outputs a reset signal RESET indicating a reset instruction or reset release to the microcomputer 12 in accordance with the voltage level of the power supply voltage Vdrv generated by the regulator 11. For example, the reset signal RESET has a level for resetting the microcomputer 12 when the power supply voltage Vdrv is lower than a predetermined level, and becomes a level for releasing the reset of the microcomputer 12 when the power supply voltage Vdrv is higher than the predetermined level.

  The regulator 11 is a circuit that generates a power supply voltage Vdrv for driving the microcomputer 12 and the like. For example, when the power supply is turned on and the regulator 11 starts to operate, the power supply voltage Vdrv rises to a target level (for example, about 3.3V).

  The microcomputer 12 is a circuit driven by the power supply voltage Vdrv generated by the regulator 11, and the power supply voltage Vdrv is lower than a predetermined level (for example, about 3.1 V) according to the reset signal output from the reset circuit 10. The reset is released when the power supply voltage Vdrv is higher than a predetermined level.

  The reset circuit 10 includes a comparator 20, a power source 21, resistors R1 to R3, P channel MOSFETs Q1 and Q2, N channel MOSFETs Q3 and Q4, and a capacitor C1. When the reset circuit 10 is integrated, for example, the resistors R1 to R3 and the capacitor C1 can be external components of the integrated circuit.

  The comparator 20 (voltage detection circuit) compares the voltage obtained by dividing the power supply voltage Vdrv output from the regulator 11 with the resistors R1 and R2 with the reference voltage Vref output from the power supply 21. In the present embodiment, when the voltage obtained by dividing the power supply voltage Vdrv is lower than the reference voltage Vref, the output signal of the comparator 20 becomes H level, and when the voltage obtained by dividing the power supply voltage Vdrv is higher than the reference voltage Vref, The output signal becomes L level. That is, the output signal of the comparator 20 indicates whether or not the power supply voltage Vdrv is higher than a predetermined level (first threshold level).

  In the P-channel MOS transistor Q1 (first MOS transistor), the voltage Vcc is applied to the source (input electrode), the drain (output electrode) is connected to one end of the resistor R3, and the output signal of the comparator 20 is input to the gate. . In the N-channel MOS transistor Q3 (second MOS transistor), the drain (input electrode) is connected to the other end of the resistor R3, the source (output electrode) is grounded, and the output signal of the comparator 20 is input to the gate. The capacitor C1 has one end connected to the other end of the resistor R3 and the drain of the N-channel MOS transistor Q3, and the other end grounded. Therefore, when the output signal of comparator 20 is at the H level, P channel MOS transistor Q1 is turned off, N channel MOS transistor Q3 is turned on, and capacitor C1 is discharged. When the output signal of the comparator 20 is at L level, the P channel MOS transistor Q1 is turned on, the N channel MOS transistor Q3 is turned off, and the capacitor C1 is charged. The P channel MOS transistor Q1 and the N channel MOS transistor Q3 correspond to the charge / discharge circuit of the present invention.

  In the P-channel MOS transistor Q2, the voltage Vcc is applied to the source, the drain is connected to the drain of the N-channel MOS transistor Q4, and the voltage Vc of the capacitor C1 is applied to the gate. The N channel MOS transistor Q4 has a drain connected to the drain of the P channel MOS transistor Q2, a source grounded, and a voltage Vc of the capacitor C1 applied to the gate. A signal output from the connection point of the P channel MOS transistor Q2 and the N channel MOS transistor Q4 is a reset signal RESET. That is, the P-channel MOS transistor Q2 and the N-channel MOS transistor Q4 use the voltage Vcc as a power source, and change the signal level of the reset signal RESET according to the voltage level of the voltage Vc of the capacitor C1 (CMOS inverter circuit). ).

  In this embodiment, since the voltage Vcc is applied to the source of the P channel MOS transistor Q2 and the source of the N channel MOS transistor Q4 is grounded, the MOS inverter circuit by the P channel MOS transistor Q2 and the N channel MOS transistor Q4. The threshold voltage (second threshold level) is Vcc / 2. Therefore, when voltage Vc of capacitor C1 is lower than Vcc / 2, P channel MOS transistor Q2 is turned on, N channel MOS transistor Q4 is turned off, and reset signal RESET is at H level. When voltage Vc of capacitor C1 is higher than Vcc / 2, P channel MOS transistor Q2 is turned off, N channel MOS transistor Q4 is turned on, and reset signal RESET is at L level.

  FIG. 2 is a diagram illustrating an example of changes in the power supply voltage and the reset signal. First, at time T0, the regulator 11 has not started operation, and the power supply voltage Vdrv is, for example, 0V. At this time, since the output signal of the comparator 20 is at the H level, the P-channel MOS transistor Q1 is turned off, the N-channel MOS transistor Q3 is turned on, and the capacitor C1 is in a discharged state. Therefore, the reset signal RESET is at the H level, and the microcomputer 12 is in a reset state.

  When the regulator 11 starts operating and the power supply voltage Vdrv rises and the power supply voltage Vdrv becomes higher than the voltage Vth at time T1, the voltage obtained by dividing the power supply voltage Vdrv by the resistors R1 and R2 becomes higher than the reference voltage Vref, and the comparator 20 output signals become L level. As a result, the P-channel MOS transistor Q1 is turned on and the N-channel MOS transistor Q3 is turned off, and a current through the resistor R3 flows into the capacitor C1 to charge the capacitor C1. When the voltage Vc of the capacitor C1 becomes higher than Vcc / 2 at time T2, the reset signal RESET becomes L level, and the reset of the microcomputer 12 is released. As described above, in the reset circuit 10, the resistor R3 and the capacitor C1 form a time constant circuit, and the delay time from when the power supply voltage Vdrv exceeds the voltage Vth until the reset signal RESET changes to the L level. It is possible to provide Td. When the reset circuit 10 is an integrated circuit, the resistor R3 may be built in the integrated circuit or may be an external circuit of the integrated circuit. When the resistor R3 is an external circuit, the delay time Td can be adjusted by changing the resistance value of the resistor R3.

  Thereafter, when the power supply voltage Vdrv decreases and the power supply voltage Vdrv becomes lower than the voltage Vth at time T3, the voltage obtained by dividing the power supply voltage Vdrv by the resistors R1 and R2 becomes lower than the reference voltage Vref, and the output signal of the comparator 20 becomes H Become a level. As a result, P-channel MOS transistor Q1 is turned off, N-channel MOS transistor Q3 is turned on, capacitor C1 is discharged, reset signal RESET goes to H level, and microcomputer 12 is reset.

FIG. 3 is a diagram illustrating an example of a change in voltage Vc charged in the capacitor. It is assumed that P channel MOS transistor Q1 is on and N channel MOS transistor Q3 is off. Here, assuming that the resistance value of the resistor R3 is R, the capacitance of the capacitor C1 is C, and the elapsed time after the capacitor C1 starts to be charged is t, the voltage Vc of the capacitor C1 is expressed by the following equation (1).

Since the threshold voltage of the CMOS inverter constituted by the P channel MOS transistor Q2 and the N channel MOS transistor Q4 is Vcc / 2, the following equation (2) is established.

From this equation (2), the delay time Td can be obtained as in the following equation (3).

  As apparent from the equation (3), the delay time Td does not depend on the voltage Vcc, and is a fixed time corresponding to the resistance value R and the capacitance C.

  The reset circuit 10 of the present embodiment has been described above. In the reset circuit 10, the voltage of the capacitor C1 is determined using a MOS transistor including a P-channel MOS transistor Q2 and an N-channel MOS transistor Q4. For this reason, the number of elements is smaller than in the case where a comparator is used for determining the voltage Vc of the capacitor C1, and the circuit scale can be reduced. The MOS inverter circuit that determines the voltage Vc of the capacitor C1 is not limited to a CMOS inverter circuit. For example, an NMOS inverter circuit in which a resistor and an N channel MOS transistor are connected in series may be used.

  In the reset circuit 10, a P channel MOS transistor Q1 and an N channel MOS transistor Q3 are used as circuits for charging and discharging the capacitor C1. Therefore, the number of elements can be reduced as compared with the case where a constant current circuit is used as a circuit for charging and discharging the capacitor C1. Further, when the capacitor C1 is not charged, no current for charging flows, so that current consumption can be reduced.

  In the reset circuit 10, a CMOS inverter circuit driven by the voltage Vcc is used as a MOS inverter circuit for determining the voltage Vc of the capacitor C1. Therefore, as shown in the equation (3), the dependency of the delay time Td on the voltage Vcc can be eliminated.

  In addition, the said Example is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

It is a figure which shows the structure of the reset circuit which is one Embodiment of this invention. It is a figure which shows an example of the change of a power supply voltage and a reset signal. It is a figure which shows an example of the change of the voltage charged to a capacitor. It is a figure which shows the general structural example of a reset circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Reset circuit 11 Regulator 12 Microcomputer 20 Comparator 21 Power supply R1-R3 Resistance Q1, Q2 P channel MOSFET
Q3, Q4 N-channel MOSFET
C1 capacitor

Claims (3)

A reset circuit that outputs a reset signal indicating a reset instruction or reset release to a circuit driven by the power supply voltage according to a voltage level of the power supply voltage,
A voltage detection circuit for detecting whether the power supply voltage is higher than a predetermined first threshold level;
A charge / discharge circuit that charges a capacitor when the power supply voltage is higher than the first threshold level and discharges the capacitor when the power supply voltage is lower than the first threshold level based on a detection result of the voltage detection circuit. When,
When the voltage of the capacitor is lower than a predetermined second threshold level, the reset signal is changed to one logic level indicating a reset instruction, and when the voltage of the capacitor is higher than the second threshold level, the other indicating reset release A MOS inverter circuit that changes the reset signal to a logic level of
A reset circuit comprising: The reset circuit according to claim 1,
The charge / discharge circuit is
The input electrode is connected to the power supply side, the output electrode is connected to the other end of the resistor connected to one end of the capacitor, and the power supply voltage is set to the first threshold value based on the detection result of the voltage detection circuit. A first MOS transistor which is turned on when higher than a level;
A second MOS that is turned on when the input electrode is connected to one end of the capacitor, the output electrode is connected to the ground side, and the power supply voltage is lower than the first threshold level based on the detection result of the voltage detection circuit A transistor,
A reset circuit comprising: The reset circuit according to claim 2,
The MOS inverter circuit is a CMOS inverter circuit driven by the same power source as the first MOS transistor;
A reset circuit characterized by.

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