CN114264869B - EFT detection device and method - Google Patents

EFT detection device and method Download PDF

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Publication number
CN114264869B
CN114264869B CN202111489393.3A CN202111489393A CN114264869B CN 114264869 B CN114264869 B CN 114264869B CN 202111489393 A CN202111489393 A CN 202111489393A CN 114264869 B CN114264869 B CN 114264869B
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inverter
module
eft
output
output voltage
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CN114264869A (en
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袁中平
郑明德
邹伯均
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Shenzhen Hisu Core Technology Co ltd
Wuxi Haisuxinye Electronic Technology Co ltd
Haisuxin Hangzhou Technology Co ltd
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Shenzhen Hisu Core Technology Co ltd
Wuxi Haisuxinye Electronic Technology Co ltd
Haisuxin Hangzhou Technology Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses an EFT detection device and method, comprising three groups of inverters and a capacitor C1, wherein the three groups of inverters comprise an inverter I1 module, an inverter I2 module and an inverter I3 module; the inverter I1 module is used for shorting its own input terminal and output terminal and outputting voltage V a The method comprises the steps of carrying out a first treatment on the surface of the The inverter I2 module is used for judging the output voltage V when EFT interference occurs a Relationship with the threshold voltage in the inverter I2 module, and the variation of the inverter I2 module output voltage DH; the inverter I3 module is used for judging the output voltage V when EFT interference occurs a Relationship with the threshold voltage in the inverter I3 module, and the variation of the output voltage DL of the inverter I3 module; the EFT detection device and the EFT detection method integrate three groups of inverters in a single IC chip, and when the chip suffers EFT interference, the device can quickly respond to inform the chip to start protection measures so as to avoid subsequent misoperation.

Description

EFT detection device and method
Technical Field
The invention relates to the technical field of detection, in particular to an EFT detection device and method.
Background
EFT, i.e. the electrical fast transient burst, is the electromagnetic interference generated by switching an inductive load. There are numerous mechanical switches typically occurring in the grid of a server, such as: and a relay switch, wherein interference is generated in the switching process of opening and closing when other inductive loads are switched off and on. The interference wave of the electric fast transient pulse group has the characteristics of narrow pulse breakthrough, high pulse group repetition frequency, steep rising edge, multiple breakthrough of a single pulse group, general amplitude of the interference wave reaching KV level and the like. Because of the relatively large destructive nature of the electrical fast transient bursts, the connections that are typically broken are primarily power ports and network ports.
The network port of the information technology equipment is also a test port of the electric rapid transient pulse group, and has relatively high test sensitivity, and the network port chip is easy to break down after being interfered by the electric rapid transient pulse group burst wave, so that the function of the network port is lost.
Disclosure of Invention
The present invention is directed to an EFT detection device and method for solving the above-mentioned problems.
In order to solve the technical problems, the invention provides the following technical scheme: the EFT detection device is characterized by comprising three groups of inverters and a capacitor C1, wherein the three groups of inverters comprise an inverter I1 module, an inverter I2 module and an inverter I3 module;
the inverter I1 module is used for shorting its own input terminal and output terminal and outputting voltage V a The method comprises the steps of carrying out a first treatment on the surface of the The inverter I2 module is used for judging the output voltage V when EFT interference occurs a Relationship with the threshold voltage in the inverter I2 module, and the variation of the inverter I2 module output voltage DH; the inverter I3 module is used for judging the output voltage V when EFT interference occurs a Relationship with the threshold voltage in the inverter I3 module, and the variation of the output voltage DL of the inverter I3 module.
Further, the inverter I1 module comprises an inverter I1, the output end of the inverter I1 is respectively connected with the inverter I2 module and the inverter I3 module, the power end of the inverter I1 is connected with the power supply VDD, the grounding end of the inverter I1 is grounded GND, the input end of the inverter I1 is connected with the first end of the capacitor C1, the second end of the inverter capacitor C1 is grounded, and the first end of the inverter capacitor C1 is connected with the output end of the inverter I1.
Further, the inverter I2 module comprises an inverter I2, the input end of the inverter I2 is connected with the inverter I1 module, the input end of the inverter I2 is connected with the first end of the capacitor C1, the power end of the inverter I2 is connected with the power supply VDD, the grounding ground GND of the inverter I2, the output end of the inverter I2 outputs a high level or a low level, and the output end of the inverter I2 is used for measuring the output voltage.
Further, the inverter I3 module comprises an inverter I3, the input end of the inverter I3 is connected with the inverter I1 module, the power end of the inverter I3 is connected with the power supply VDD, the grounding of the inverter I3 is grounded, the output end of the inverter I3 outputs a high level or a low level, and the output end of the inverter I3 is used for measuring the output voltage.
The EFT detection method comprises the following steps:
step S1: integrating the three groups of inverters with a capacitor C1 and a power supply VDD to form an EFT detection device; the three groups of inverters comprise an inverter I1, an inverter I2 and an inverter I3; the power supply VDD is electrically connected with the inverter I1, the inverter I2 and the inverter I3, and the capacitor C1 is electrically connected with the inverter I1 and the inverter I2;
step S2: analyzing the relation between the output voltage of the inverter I1 and the threshold voltage of the inverter I2 and the threshold voltage of the inverter I3 respectively in a steady state, wherein the threshold voltage is a critical value of the internal voltage of the inverter;
step S3: based on the data of step S2, it is analyzed whether the inverter I2 and the inverter I3 detect EFT when the power supply VDD changes.
Further, step S1 includes:
the power supply end of the inverter I1 is connected with the power supply VDD, the grounding end of the inverter I1 is grounded, the input end of the inverter I1 is connected with the first end of the inverter capacitor C1, the first end of the inverter capacitor C1 is connected with the output end of the inverter, the second end of the inverter capacitor C1 is grounded, and the output end of the inverter I1 is connected with the input end of the inverter I2 and the input end of the inverter I3;
the input end of the inverter I2 is connected with the output end of the inverter I1 and the input end of the inverter I3, the power end of the inverter I2 is connected with the power supply VDD, the grounding end of the inverter I2 is grounded, and the output end of the inverter I2 outputs the level DH;
the input end of the inverter I3 is connected with the output end of the inverter I1 and the input end of the inverter I2, the power end of the inverter I3 is connected with the power supply VDD, the grounding end of the inverter I3 is grounded, and the output end of the inverter I3 outputs the level DL.
Further, step S2 includes:
judging whether the output end and the input end of the inverter I1 are short-circuited, and outputting a voltage V if the output end and the input end are short-circuited a ；
Based on the output voltage V a Judging the output voltage V at this time a A magnitude relation with a threshold voltage difference value of the inverter I2; if output voltage V a Less than the threshold voltage of inverter I2, inverter I2 is in a steady state;
based on the output voltage V a Judging the output voltage V at this time a A magnitude relation with a threshold voltage difference value of the inverter I3; if output voltage V a Greater than the threshold voltage of inverter I3, inverter I3 is in a steady state.
And outputting voltage V to three groups of inverters a Is illustrated by the comparison of the output voltage V in the steady state a Lower than the threshold voltage of the inverter I2, DH at the output of the inverter I2 is high; output voltage V a Above the threshold voltage of the inverter I3, the DL output from the inverter I3 is low, and the output level of the inverter in steady state provides for dynamic contrast analysis of the threshold voltage of the inverter and the output level during subsequent EFT disturbances.
Further, step S3 includes:
when detecting that the power supply VDD is reduced within the preset time range, calculating the threshold voltage and the output voltage V of the inverter I2 a If the difference between the threshold voltage of the inverter I2 and the output voltage V a If the difference of the first and second signals is less than 0, determining that the inverter I2 detects the EFT;
when the rise of the power supply VDD is detected within the preset time range, the threshold voltage and the output voltage V of the inverter I3 are calculated a If the difference between the threshold voltage of the inverter I3 and the output voltage V a If the difference is greater than 0, the determination inverter I3 detects EFT.
When the power supply VDD is at a preset levelThe falling or rising in the time range represents the instantaneous falling or rising of the power supply VDD, the instantaneous time is within 5ns, and the input end of the inverter I1 arranged in the circuit is connected with the capacitor C1, so that the output voltage V a Because the capacitor C1 remains unchanged temporarily because of the output voltage V a Will not be changed by EFT interference, so will output voltage V a For comparison with the threshold voltages of inverter I2 and inverter I3, such that the inverter I2 and inverter I3 detect an EFT disturbance;
the threshold voltage of the inverter I2 decreases with the power supply VDD, and the threshold voltage within the inverter I2 is lower than the output voltage V a Inverter I2 outputs DH, and DH changes from high level at steady state to low level; the threshold voltage of the inverter I3 increases with the power supply VDD, and the threshold voltage within the inverter I3 is higher than the output voltage V a The inverter I3 outputs DL, and DL changes from low level at steady state to high level;
when VDD decreases instantaneously, the capacitor C1 is added into the circuit to make voltage V a Unchanged, but in this case the threshold voltage within inverter I2 changes, DH changes from high to low with a decrease in VDD, indicating that inverter I2 detects the occurrence of EFT disturbance; when VDD rises instantaneously, the capacitor C1 is added into the circuit to make voltage V a The change of the threshold voltage in the inverter I3 in this case, however, with the increase of VDD, the change of DL from low to high, indicates that the inverter I3 detects the occurrence of EFT disturbance.
Compared with the prior art, the invention has the following beneficial effects: according to the EFT detection device and the EFT detection method, three groups of inverters are integrated in a single IC chip, when the chip suffers from EFT interference, the device can quickly react, no matter whether the VDD value under the EFT interference is instantaneously raised or instantaneously lowered, the corresponding inverters can accurately monitor the change of the value and react, so that the device can accurately inform the chip to start protection measures, and subsequent misoperation is avoided; and the connection port of the circuit is not easy to be damaged, the chip is protected from breakdown, and the network port function is well preserved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a schematic diagram of an EFT detection device according to the present invention;
FIG. 2 shows the threshold voltage and the output voltage V of the inverter at steady state in the EFT detection apparatus and method of the present invention a A relationship diagram;
FIG. 3 shows the threshold voltage and the output voltage V of the inverter when the VDD is instantaneously reduced due to the EFT disturbance in the EFT detection apparatus and method of the present invention a A relationship diagram;
FIG. 4 shows the threshold voltage and the output voltage V of the inverter when the VDD is momentarily raised due to the EFT disturbance in the EFT detection apparatus and method of the present invention a A relationship diagram.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-4, the present invention provides the following technical solutions: the EFT detection device is characterized by comprising three groups of inverters and a capacitor C1, wherein the three groups of inverters comprise an inverter I1 module, an inverter I2 module and an inverter I3 module;
the inverter I1 module is used for shorting its own input terminal and output terminal and outputting voltage V a The method comprises the steps of carrying out a first treatment on the surface of the The inverter I2 module is used for judging the output voltage V when EFT interference occurs a Relationship with the threshold voltage in the inverter I2 module, and the variation of the inverter I2 module output voltage DH; the inverter I3 module is used for judging the output voltage V when EFT interference occurs a Relationship with the threshold voltage in the inverter I3 module, and the variation of the output voltage DL of the inverter I3 module.
The inverter I1 module comprises an inverter I1, the output end of the inverter I1 is respectively connected with the inverter I2 module and the inverter I3 module, the power end of the inverter I1 is connected with a power supply VDD, the grounding end of the inverter I1 is grounded GND, the input end of the inverter I1 is connected with the first end of the capacitor C1, the second end of the inverter capacitor C1 is grounded, and the first end of the inverter capacitor C1 is connected with the output end of the inverter I1.
The inverter I2 module comprises an inverter I2, the input end of the inverter I2 is connected with the inverter I1 module, the input end of the inverter I2 is connected with the first end of the capacitor C1, the power end of the inverter I2 is connected with the power supply VDD, the grounding ground GND of the inverter I2, the output end of the inverter I2 outputs a high level or a low level, and the output end of the inverter I2 is used for measuring the output voltage.
The inverter I3 module comprises an inverter I3, the input end of the inverter I3 is connected with the inverter I1 module, the power end of the inverter I3 is connected with the power supply VDD, the grounding end of the inverter I3 is grounded, the output end of the inverter I3 outputs a high level or a low level, and the output end of the inverter I3 is used for measuring the output voltage.
The EFT detection method comprises the following steps:
step S1: integrating the three groups of inverters with a capacitor C1 and a power supply VDD to form an EFT detection device; the three groups of inverters comprise an inverter I1, an inverter I2 and an inverter I3; the power supply VDD is electrically connected with the inverter I1, the inverter I2 and the inverter I3, and the capacitor C1 is electrically connected with the inverter I1 and the inverter I2;
the specific process of step S1 is as follows:
the power supply end of the inverter I1 is connected with the power supply VDD, the grounding end of the inverter I1 is grounded, the input end of the inverter I1 is connected with the first end of the inverter capacitor C1, the first end of the inverter capacitor C1 is connected with the output end of the inverter, the second end of the inverter capacitor C1 is grounded, and the output end of the inverter I1 is connected with the input end of the inverter I2 and the input end of the inverter I3;
the input end of the inverter I2 is connected with the output end of the inverter I1 and the input end of the inverter I3, the power end of the inverter I2 is connected with the power supply VDD, the grounding end of the inverter I2 is grounded, and the output end of the inverter I2 outputs the level DH;
the input end of the inverter I3 is connected with the output end of the inverter I1 and the input end of the inverter I2, the power end of the inverter I3 is connected with the power supply VDD, the grounding end of the inverter I3 is grounded, and the output end of the inverter I3 outputs the level DL.
Step S2: and analyzing the relation between the output voltage of the inverter I1 and the threshold voltage of the inverter I2 and the threshold voltage of the inverter I3 respectively in a steady state, wherein the threshold voltage is a critical value of the internal voltage of the inverter.
The step S2 includes:
judging whether the output end and the input end of the inverter I1 are short-circuited, and outputting a voltage V if the output end and the input end are short-circuited a ；
Based on the output voltage V a Judging the output voltage V at this time a A magnitude relation with a threshold voltage difference value of the inverter I2; if output voltage V a Less than the threshold voltage of inverter I2, inverter I2 is in a steady state;
based on the output voltage V a Judging the output voltage V at this time a A magnitude relation with a threshold voltage difference value of the inverter I3; if output voltage V a Greater than the threshold voltage of inverter I3, inverter I3 is in a steady state.
For example, as shown in FIG. 2, in steady state, the output voltage V corresponding to the curve of the inverter I1 a In the middle of the graph, the curve of the inverter I2 is positioned at the upper right of the curve of the inverter I1, and the threshold voltage represented by the curve of the inverter I2 is greater than the output voltage V a Is DH high level; the curve position of the inverter I3 is the left lower part of the curve of the inverter I1, and the threshold voltage represented by the curve of the inverter I3 is smaller than the output voltage V a Is DL low.
And outputting voltage V to three groups of inverters a Is illustrated by the comparison of the output voltage V in the steady state a Lower than the threshold voltage of the inverter I2, DH at the output of the inverter I2 is high; output voltage V a Above the threshold voltage of the inverter I3, the DL output by the inverter I3 is low, and the output level of the inverter in steady state is dynamic with respect to the threshold voltage and the output level of the inverter in the subsequent EFT disturbance generationIs prepared for comparative analysis of (c).
Step S3: based on the data of step S2, it is analyzed whether the inverter I2 and the inverter I3 detect EFT when the power supply VDD changes.
The step S3 comprises the following steps:
when detecting that the power supply VDD is reduced within the preset time range, calculating the threshold voltage and the output voltage V of the inverter I2 a If the difference between the threshold voltage of the inverter I2 and the output voltage V a If the difference of the first and second signals is less than 0, determining that the inverter I2 detects the EFT;
when the rise of the power supply VDD is detected within the preset time range, the threshold voltage and the output voltage V of the inverter I3 are calculated a If the difference between the threshold voltage of the inverter I3 and the output voltage V a If the difference is greater than 0, the determination inverter I3 detects EFT.
When the power supply VDD is reduced or increased within the preset time range, the power supply VDD is instantaneously reduced or increased within 5ns, and the input end of the inverter I1 is connected with the capacitor C1 in the circuit so as to output the voltage V a Because the capacitor C1 remains unchanged temporarily because of the output voltage V a Will not be changed by EFT interference, so will output voltage V a For comparison with the threshold voltages of inverter I2 and inverter I3, such that the inverters I2 and I3 detect EFT disturbances.
Such as shown in fig. 3: the VDD decreases instantaneously so that the curve position of the inverter I2 changes from the upper right side of the curve of the inverter I1 to the lower left side of the curve of the inverter I1, i.e. the threshold voltage represented by the curve of the inverter I2 is smaller than the output voltage V a ；
The threshold voltage of the inverter I2 decreases with the power supply VDD, and the threshold voltage within the inverter I2 is lower than the output voltage V a Inverter I2 outputs DH, and DH changes from high level at steady state to low level; when VDD decreases instantaneously, the capacitor C1 is added into the circuit to make voltage V a Unchanged, but in this case the threshold voltage within inverter I2 changes, DH changes from high to low with a decrease in VDD, indicating that inverter I2 detects the occurrence of EFT disturbance;
such as shown in fig. 4: the VDD momentarily rises to change the curve position of the inverter I3 from the lower left of the curve of the inverter I1 to the upper right of the curve of the inverter I1, i.e. the threshold voltage represented by the curve of the inverter I3 is larger than the output voltage V a ；
The threshold voltage of the inverter I3 increases with the power supply VDD, and the threshold voltage within the inverter I3 is higher than the output voltage V a The inverter I3 outputs DL, and DL changes from low level at steady state to high level; when VDD rises instantaneously, the capacitor C1 is added into the circuit to make voltage V a The change of the threshold voltage in the inverter I3 in this case, however, with the increase of VDD, the change of DL from low to high, indicates that the inverter I3 detects the occurrence of EFT disturbance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

  1. An eft detection method, comprising the steps of:
    step S1: integrating the three groups of inverters with a capacitor C1 and a power supply VDD to form an EFT detection device; the three groups of inverters comprise an inverter I1, an inverter I2 and an inverter I3; the power supply VDD is electrically connected with the inverter I1, the inverter I2 and the inverter I3, and the capacitor C1 is electrically connected with the inverter I1 and the inverter I2;
    the step S1 includes:
    the power supply end of the inverter I1 is connected to a power supply VDD, the grounding end of the inverter I1 is grounded, the input end of the inverter I1 is connected with the first end of the capacitor C1, the first end of the capacitor is connected with the output end of the inverter, the second end of the capacitor C1 is grounded, and the output end of the inverter I1 is connected with the input end of the inverter I2 and the input end of the inverter I3;
    the input end of the inverter I2 is connected with the output end of the inverter I1 and the input end of the inverter I3, the power end of the inverter I2 is connected with the power supply VDD, the grounding end of the inverter I2 is grounded, and the output end of the inverter I2 outputs the level DH;
    the input end of the inverter I3 is connected with the output end of the inverter I1 and the input end of the inverter I2, the power end of the inverter I3 is connected with the power supply VDD, the grounding end of the inverter I3 is grounded, and the output end of the inverter I3 outputs the level DL;
    step S2: analyzing the relation between the output voltage of the inverter I1 and the threshold voltage of the inverter I2 and the threshold voltage of the inverter I3 respectively in a steady state, wherein the threshold voltage is a critical value of the internal voltage of the inverter;
    step S3: based on the data in step S2, when the power supply VDD is analyzed to generate a change, whether the inverter I2 and the inverter I3 detect EFT or not;
    the step S3 includes:
    when detecting that the power supply VDD is reduced within the preset time range, calculating the threshold voltage and the output voltage V of the inverter I2 a If the difference between the threshold voltage of the inverter I2 and the output voltage V a If the difference of the first and second signals is less than 0, determining that the inverter I2 detects the EFT;
    when the power supply VDD is detected to be in the preset time rangeAt internal rising, the threshold voltage and output voltage V of the inverter I3 are calculated a If the difference between the threshold voltage of the inverter I3 and the output voltage V a If the difference is greater than 0, the determination inverter I3 detects EFT.
  2. 2. The EFT detection method as claimed in claim 1, wherein: the step S2 includes:
    judging whether the output end and the input end of the inverter I1 are short-circuited, and outputting a voltage V if the output end and the input end are short-circuited a ；
    Based on the output voltage V a Judging the output voltage V at this time a A magnitude relation with a threshold voltage difference value of the inverter I2; if output voltage V a Less than the threshold voltage of inverter I2, inverter I2 is in a steady state;
    based on the output voltage V a Judging the output voltage V at this time a A magnitude relation with a threshold voltage difference value of the inverter I3; if output voltage V a Greater than the threshold voltage of inverter I3, inverter I3 is in a steady state.
  3. 3. The EFT detecting apparatus using the EFT detecting method as claimed in any one of claims 1 to 2, comprising three sets of inverters and a capacitor C1, wherein the three sets of inverters comprise an inverter I1 module, an inverter I2 module and an inverter I3 module;
    the inverter I1 module is used for shorting its own input terminal and output terminal and outputting voltage V a The method comprises the steps of carrying out a first treatment on the surface of the The inverter I2 module is used for judging the output voltage V when EFT interference occurs a Relationship with the threshold voltage in the inverter I2 module, and the variation of the inverter I2 module output voltage DH; the inverter I3 module is used for judging the output voltage V when EFT interference occurs a Relationship with the threshold voltage in the inverter I3 module, and the variation of the output voltage DL of the inverter I3 module.
  4. 4. The EFT detecting apparatus according to claim 3, wherein: the inverter I1 module comprises an inverter I1, wherein the output end of the inverter I1 is respectively connected with the inverter I2 module and the inverter I3 module, the power end of the inverter I1 is connected with a power supply VDD, the grounding end of the inverter I1 is grounded GND, the input end of the inverter I1 is connected with the first end of a capacitor C1, the second end of the capacitor C1 is grounded, and the first end of the capacitor C1 is connected with the output end of the inverter I1.
  5. 5. The EFT detecting apparatus according to claim 4, wherein: the inverter I2 module comprises an inverter I2, the input end of the inverter I2 is connected with the inverter I1 module, the input end of the inverter I2 is connected with the first end of the capacitor C1, the power end of the inverter I2 is connected with a power supply VDD, the grounding end of the inverter I2 is grounded GND, the output end of the inverter I2 outputs a high level or a low level, and the output end of the inverter I2 is used for measuring the output voltage.
  6. 6. The EFT detecting apparatus according to claim 4, wherein: the inverter I3 module comprises an inverter I3, the input end of the inverter I3 is connected with the inverter I1 module, the power end of the inverter I3 is connected with a power supply VDD, the grounding end of the inverter I3 is grounded, the output end of the inverter I3 outputs a high level or a low level, and the output end of the inverter I3 is used for measuring the output voltage.
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