CN108073259A - A kind of electrification reset circuit of super low-power consumption highly resistance EFT - Google Patents
A kind of electrification reset circuit of super low-power consumption highly resistance EFT Download PDFInfo
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- CN108073259A CN108073259A CN201611004112.XA CN201611004112A CN108073259A CN 108073259 A CN108073259 A CN 108073259A CN 201611004112 A CN201611004112 A CN 201611004112A CN 108073259 A CN108073259 A CN 108073259A
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- 230000005611 electricity Effects 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 4
- 230000036039 immunity Effects 0.000 abstract description 4
- 230000007257 malfunction Effects 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009510 drug design Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The invention discloses the electrification reset circuits of super low-power consumption highly resistance EFT of reset circuit technical field a kind of, including capacitance C1, the top port of the capacitance C1 and the S ports for being connected to VDD and the first PMOS tube P1, the bottom port of the capacitance C1 is simultaneously connected to the G ports of the first PMOS tube P1, D the and G ports of the first NMOS tube N1, the circuit either power supply fast powering-up still powers at a slow speed, can effectively export reset signal；And the structure is after completion is resetted, there is no the DC channel of electric current, so the power consumption of the resetting structure can be preferably minimized；And increased R1 resistance and inv0 are designed to schmitt inverter in the resetting structure, it can ensure in the case of supply voltage poor quality, reseting module is avoided to malfunction, improves the eft immunity of reset circuit, greatly improves the reliability of reset circuit.
Description
Technical field
The present invention relates to reset circuit technical fields, are specially a kind of electrification reset circuit of super low-power consumption highly resistance EFT.
Background technology
It is well known that power-on reset signal is a vital signal in integrated circuit, reset signal it is reliable
It is that the basis of guarantee system steady operation, minority electrons equipment, chip etc. is provided by external special electrification reset chip
Reset signal, most of is built-in electrification reset circuit to provide reset signal, with the development of society, portable, wearing class electricity
In order to ensure the stabilization of the electronic product, work long hours, higher is proposed to electrification reset circuit for sub- product extensive use
Requirement, but in current scheme, such as three kinds of power-on-reset circuit with low power consumption structure diagrams that Fig. 3,4 and 5 propose,
Electrification reset structure wherein shown in Fig. 3, after electrification reset is completed, there is no DC channel, the power consumption of reset circuit is extremely low,
But the structure easily to extremely slowly powering on failure, causes resetting structure not work；Electrification reset structure shown in Fig. 4, is above replied by cable
After position is completed, there are DC channel, circuit power consumption can be only sustained at relatively low level, and the structure is easily to fast powering-up
Failure, causes resetting structure not work；Electrification reset structure shown in Fig. 5, the advantages of combining above-mentioned two, but circuit power consumption
It is still unable to reach minimum, and in the case where power quality is bad, is easily interfered, the action resetted by mistake occurs, i.e.,
Circuit eft immunity is poor, can seriously affect the reliability of electrification reset circuit, for this purpose, I proposes that a kind of super low-power consumption is high
The electrification reset circuit of anti-EFT.
The content of the invention
It is an object of the invention to provide a kind of electrification reset circuit of super low-power consumption highly resistance EFT, to solve above-mentioned background
Itd is proposed in technology extremely slowly power on Problem of Failure and fast powering-up Problem of Failure and the eft immunity of circuit is poor, it is impossible to ensure
The steady operation in the case where power quality is bad, and circuit does not have the problem of ultralow power consumption.
To achieve the above object, the present invention provides following technical solution：A kind of electrification reset electricity of super low-power consumption highly resistance EFT
Road, including capacitance C1, the top port of the capacitance C1 and the S ports for being connected to VDD and the first PMOS tube P1, the capacitance C1's
Bottom port is simultaneously connected to the G ports of the first PMOS tube P1, D the and G ports of the first NMOS tube N1, the S of the first NMOS tube N1
Port and the bottom port for being connected to ground wire and capacitance C2, the top port of the capacitance C2 is simultaneously connected to resistance R1 and inV0, described
The other end of resistance R1 is connected with the D ports of the first PMOS tube P1, and the other end of the inV0 is serially connected with inV1, the inV1's
The other end is serially connected with RSTB output ports, and the inV0 includes PMOS tube P0, and the S ports of the PMOS tube P0 are serially connected with VDD, institute
It states the G ports of PMOS tube P0 and is connected to input port, the G ports of the second PMOS tube P1, the G ports of NMOS tube N0 and the 2nd NMOS
The G ports of pipe N1, the D ports of the PMOS tube P0 and the S ports for being connected to the second PMOS tube P1 and PMOS tube P2, the PMOS tube
The D ports ground connection of P2, the D ports of the second PMOS tube P1 are simultaneously connected to the G ports of PMOS tube P2, output port, NMOS tube N2
G ports and NMOS tube N0 D ports, the S ports of the NMOS tube N0 and D ports and the NMOS tube for being connected to the second NMOS tube N1
The S ports of N2, the S ports ground connection of the second NMOS tube N1, the D ports concatenation VDD of the NMOS tube N2.
Preferably, the capacitance C1 and C2 is ceramic condenser.
Preferably, the resistance R1 is fixed carbon resister.
Compared with prior art, the beneficial effects of the invention are as follows：It is ceramic condenser by capacitance C1 and C2, has and use
Temperature is higher, and specific capacity is big, and moisture resistance is good, and dielectric loss is smaller, capacitance temperature factor can in a wide range of the characteristics of selection,
The stability of circuit can be improved, resistance R1 is fixed carbon resister, and the cost of fixed carbon resister is low, performance is stable, Standard resistance range is wide, warm
It spends coefficient and voltage coefficient is low, the circuit either power supply fast powering-up still powers at a slow speed, can effectively export reset letter
Number；And the structure is after completion is resetted, there is no the DC channel of electric current, so the power consumption of the resetting structure can drop to most
It is low；And increased R1 resistance and inv0 are designed to schmitt inverter in the resetting structure, can ensure in supply voltage
In the case of poor quality, reseting module is avoided to malfunction, improve the eft immunity of reset circuit, greatly improve reset
The reliability of circuit.
Description of the drawings
Fig. 1 is electrification reset basic circuit diagram of the present invention；
Fig. 2 is inv0 electrical block diagrams of the present invention；
Fig. 3 is the first existing electrification reset circuit figure；
Fig. 4 is existing second of electrification reset circuit figure；
Fig. 5 is the third existing electrification reset circuit figure.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment belongs to the scope of protection of the invention.
- 5 are please referred to Fig.1, the present invention provides a kind of technical solution：A kind of electrification reset circuit of super low-power consumption highly resistance EFT,
Including capacitance C1, the top port of the capacitance C1 and the S ports for being connected to VDD and the first PMOS tube P1, the bottom of the capacitance C1
Portion port is simultaneously connected to the G ports of the first PMOS tube P1, D the and G ports of the first NMOS tube N1, the S ends of the first NMOS tube N1
Mouth is simultaneously connected to the bottom port of ground wire and capacitance C2, and the top port of the capacitance C2 is simultaneously connected to resistance R1 and inV0, the electricity
The other end of resistance R1 is connected with the D ports of the first PMOS tube P1, and the other end of the inV0 is serially connected with inV1, and the inV1's is another
One end is serially connected with RSTB output ports, and the inV0 includes PMOS tube P0, and the S ports of the PMOS tube P0 are serially connected with VDD, described
The G ports of PMOS tube P0 are simultaneously connected to input port, the G ports of the second PMOS tube P1, the G ports of NMOS tube N0 and the second NMOS tube
The G ports of N1, the D ports of the PMOS tube P0 and the S ports for being connected to the second PMOS tube P1 and PMOS tube P2, the PMOS tube P2
D ports ground connection, the D ports of the second PMOS tube P1 are simultaneously connected to the G ports of PMOS tube P2, output port, the G of NMOS tube N2
Port and the D ports of NMOS tube N0, the S ports of the NMOS tube N0 are simultaneously connected to the D ports of the second NMOS tube N1 and NMOS tube N2
S ports, the second NMOS tube N1 S ports ground connection, the NMOS tube N2 D ports concatenation VDD.
Wherein, the capacitance C1 and C2 is ceramic condenser, and higher with temperature in use, specific capacity is big, and moisture resistance is good,
Dielectric loss is smaller, and capacitance temperature factor can be in a wide range of the characteristics of selection, and the resistance R1 is fixed carbon resister, fixed carbon resister
Cost it is low, performance is stable, Standard resistance range is wide, temperature coefficient and voltage coefficient are low.
Operation principle：NMOS tube N1 connects into diode, in vdd voltage power up, when vdd voltage is less than
During the threshold voltage of NMOS tube N1, NMOS tube N1 is closed, node A due to C1 capacitances coupling be equal to VDD,
PMOS tube P1 is closed, and node B is exported since the coupling of C2 capacitances is equal to VSS by inv0, inv1 and RSTB
Low level, chip reset；
When vdd voltage is more than the threshold voltage value of NMOS tube N1, NMOS tube N1 conductings, the electricity that node A is coupled by C1
It is discharged over the ground by NMOS tube N1, when node A voltage is less than the threshold voltage of PMOS tube P1, PMOS tube P1 conductings, VDD passes through
P1, R1 charge to C2 capacitances, node B voltage rise, when node B voltage is increased to the overturning point of inv0, inv0 overturnings, and RSTB
High level is exported, chip reset terminates, and RC discharges since the resetting structure exists all the way, and RC charges all the way, so low level is answered
Position signal can maintain the sufficiently long time, ensure that chip is stablized and reset；
If power vd D power-up speeds, than very fast, node A is since the coupling of C1 capacitances is equal to VDD, and node A
Electricity can only be discharged by NMOS tube N1, as long as so the size of rational design NMOS tube N1, that is, can guarantee that node A is slow
Electric discharge, to meet chip reset；Even if node A is discharged into rapidly the threshold value less than PMOS tube P1, the second level is still remained
The process that RC charges, node B voltage still can only slowly rise, so the resetting structure can ensure power vd D power-up speeds
It, can steady operation when fast；Long raceway groove NMOS tube may be employed to realize, to reduce the velocity of discharge of node A in NMOS tube N1；
It when supply voltage rising, is finally reached after stablizing, the voltage of node A, discharges through NMOS tube N1, eventually stablize
In the near threshold voltage of NMOS tube N1, PMOS tube P1 is in the state fully opened at this time, and node B, C voltage charge through RC,
Eventually stablize near vdd voltage.And all there is no direct currents by the way that the voltage of node B will not be led for branch 1, branch 2 at this time
Inv0 is caused to occur ganging up electric current, so the resetting structure, after completion is resetted, power consumption is extremely low；
If it during supply voltage poor quality, is illustrated with occurring a spike declined on supply voltage, at this time
The voltage of node C can be higher than vdd voltage, and the parasitic PN diodes of PMOS tube P1 can be in forward conduction state, the voltage of node B
R1, node C, the parasitic PN diode pairs VDD of PMOS tube P1 can be passed through to discharge, due to increased R1 electricity in the reset circuit
Resistance, the velocity of discharge of the node B slowed down after supply voltage recovers, will not cause node B voltage degradation, and triggering misses
Reset, while the Schmidt phase inverter inv0 being followed by of node B also further improve the Ability of Resisting Disturbance of node B.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
Understanding without departing from the principles and spirit of the present invention can carry out these embodiments a variety of variations, modification, replace
And modification, the scope of the present invention is defined by the appended.
Claims (3)
1. a kind of electrification reset circuit of super low-power consumption highly resistance EFT, including capacitance C1, it is characterised in that：The top of the capacitance C1
Portion port and the S ports for being connected to VDD and the first PMOS tube P1, the bottom port of the capacitance C1 are simultaneously connected to the first PMOS tube P1's
G ports, D the and G ports of the first NMOS tube N1, the S ports of the first NMOS tube N1 are simultaneously connected to the bottom of ground wire and capacitance C2
Port, the top port of the capacitance C2 are simultaneously connected to resistance R1 and inV0, the other end of the resistance R1 and the first PMOS tube P1
The connection of D ports, the other end of the inV0 is serially connected with inV1, and the other end of the inV1 is serially connected with RSTB output ports, institute
It states S ports of the inV0 including PMOS tube P0, the PMOS tube P0 and is serially connected with VDD, the G ports of the PMOS tube P0 are simultaneously connected to input
Port, the G ports of the second PMOS tube P1, the G ports of the G ports of NMOS tube N0 and the second NMOS tube N1, the D of the PMOS tube P0
Port and the S ports for being connected to the second PMOS tube P1 and PMOS tube P2, the D ports ground connection of the PMOS tube P2, the 2nd PMOS
The D ports of pipe P1 and the D ports for being connected to the G ports of PMOS tube P2, output port, the G ports of NMOS tube N2 and NMOS tube N0, institute
It states the S ports of NMOS tube N0 and is connected to the D ports of the second NMOS tube N1 and the S ports of NMOS tube N2, the second NMOS tube N1
S ports ground connection, the NMOS tube N2 D ports concatenation VDD.
2. a kind of electrification reset circuit of super low-power consumption highly resistance EFT according to claim 1, it is characterised in that：The electricity
It is ceramic condenser to hold C1 and C2.
3. a kind of electrification reset circuit of super low-power consumption highly resistance EFT according to claim 1, it is characterised in that：The electricity
Resistance R1 is fixed carbon resister.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611004112.XA CN108073259A (en) | 2016-11-15 | 2016-11-15 | A kind of electrification reset circuit of super low-power consumption highly resistance EFT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611004112.XA CN108073259A (en) | 2016-11-15 | 2016-11-15 | A kind of electrification reset circuit of super low-power consumption highly resistance EFT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108073259A true CN108073259A (en) | 2018-05-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611004112.XA Withdrawn CN108073259A (en) | 2016-11-15 | 2016-11-15 | A kind of electrification reset circuit of super low-power consumption highly resistance EFT |
Country Status (1)
| Country | Link |
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| CN (1) | CN108073259A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112187232A (en) * | 2020-09-07 | 2021-01-05 | 上海威固信息技术股份有限公司 | Power-on detection circuit and power-on detection method |
| CN114264869A (en) * | 2021-12-08 | 2022-04-01 | 海速芯(杭州)科技有限公司 | EFT detection device and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010147835A (en) * | 2008-12-19 | 2010-07-01 | Mitsumi Electric Co Ltd | Power-on resetting circuit |
| CN103716023A (en) * | 2013-12-03 | 2014-04-09 | 北京中电华大电子设计有限责任公司 | Power-on reset circuit with ultra-low power consumption |
| CN206209581U (en) * | 2016-11-15 | 2017-05-31 | 无锡中微爱芯电子有限公司 | A kind of electrification reset circuit of super low-power consumption anti-EFT high |
-
2016
- 2016-11-15 CN CN201611004112.XA patent/CN108073259A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010147835A (en) * | 2008-12-19 | 2010-07-01 | Mitsumi Electric Co Ltd | Power-on resetting circuit |
| CN103716023A (en) * | 2013-12-03 | 2014-04-09 | 北京中电华大电子设计有限责任公司 | Power-on reset circuit with ultra-low power consumption |
| CN206209581U (en) * | 2016-11-15 | 2017-05-31 | 无锡中微爱芯电子有限公司 | A kind of electrification reset circuit of super low-power consumption anti-EFT high |
Non-Patent Citations (1)
| Title |
|---|
| 沙占友: "《实用数字化测量技术》", 30 September 1991, 国防工业出版社, pages: 3 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112187232A (en) * | 2020-09-07 | 2021-01-05 | 上海威固信息技术股份有限公司 | Power-on detection circuit and power-on detection method |
| CN112187232B (en) * | 2020-09-07 | 2024-01-26 | 上海威固信息技术股份有限公司 | Power-on detection circuit and power-on detection method |
| CN114264869A (en) * | 2021-12-08 | 2022-04-01 | 海速芯(杭州)科技有限公司 | EFT detection device and method |
| CN114264869B (en) * | 2021-12-08 | 2024-03-22 | 海速芯(杭州)科技有限公司 | EFT detection device and method |
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Application publication date: 20180525 |
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| WW01 | Invention patent application withdrawn after publication |