CN206209581U - A kind of electrification reset circuit of super low-power consumption anti-EFT high - Google Patents

Abstract

The utility model discloses a kind of electrification reset circuit of super low-power consumption anti-EFT high of reset circuit technical field, including electric capacity C1, the top port of the electric capacity C1 is simultaneously connected to the S ports of VDD and the first PMOS P1, the bottom port of the electric capacity C1 is simultaneously connected to the G ports of the first PMOS P1, D the and G ports of the first NMOS tube N1, either power supply fast powering-up still goes up at a slow speed electricity to the circuit, can effectively export reset signal；And the structure is after the completion that resets, in the absence of the DC channel of electric current, so the power consumption of the resetting structure can be preferably minimized；And increased R1 resistance and inv0 are designed to schmitt inverter in the resetting structure, ensure that in the case of supply voltage poor quality, reseting module misoperation is avoided, the eft immunity of reset circuit is improved, the reliability of reset circuit is greatly improved.

Description

A kind of electrification reset circuit of super low-power consumption anti-EFT high

Technical field

The utility model is related to reset circuit technical field, the electrification reset electricity of specially a kind of super low-power consumption anti-EFT high Road.

Background technology

It is well known that power-on reset signal is a vital signal in integrated circuit, the reliability of reset signal It is the basis of guarantee system steady operation, minority electrons equipment, chip etc. are provided by outside special electrification reset chip Reset signal, most of to be built-in electrification reset circuit provide reset signal, with the development of society, portable, wearing class electricity Sub- product extensive use, in order to ensure the stabilization of the electronic product, work long hours, proposes higher to electrification reset circuit Requirement, but in current scheme, such as Fig. 3,4 and 5 propose three kinds of power-on-reset circuit with low power consumption structural representations, Electrification reset structure wherein shown in Fig. 3, after electrification reset is completed, in the absence of DC channel, the power consumption of reset circuit is extremely low, But the structure easily to extremely slow upper electricity failure, causes resetting structure not work；Electrification reset structure shown in Fig. 4, above replies by cable After position completes, there is DC channel, circuit power consumption can be only sustained at relatively low level, and the structure easily to fast powering-up Failure, causes resetting structure not work；Electrification reset structure shown in Fig. 5, combines the advantage of above-mentioned two, but circuit power consumption Still it is unable to reach minimum, and in the case where power quality is bad, is easily interfered, the action for resetting by mistake occurs, i.e., Circuit eft immunity is poor, can have a strong impact on the reliability of electrification reset circuit, therefore, I proposes that a kind of super low-power consumption is high The electrification reset circuit of anti-EFT.

Utility model content

The purpose of this utility model is to provide a kind of electrification reset circuit of super low-power consumption anti-EFT high, above-mentioned to solve The extremely slow upper electricity Problem of Failure and fast powering-up Problem of Failure proposed in background technology, and the eft immunity of circuit are poor, it is impossible to Ensure the steady operation in the case where power quality is bad, and problem of the circuit without ultralow power consumption.

To achieve the above object, the utility model provides following technical scheme：Replied by cable on a kind of super low-power consumption anti-EFT high Position circuit, including electric capacity C1, the top port of the electric capacity C1 is simultaneously connected to the S ports of VDD and the first PMOS P1, the electric capacity The bottom port of C1 is simultaneously connected to the G ports of the first PMOS P1, D the and G ports of the first NMOS tube N1, the first NMOS tube N1 S ports and be connected to the bottom port of ground wire and electric capacity C2, the top port of the electric capacity C2 is simultaneously connected to resistance R1 and inV0, institute The other end for stating resistance R1 is connected with the D ports of the first PMOS P1, and the other end of the inV0 is serially connected with inV1, the inV1 The other end be serially connected with RSTB output ports, the inV0 includes PMOS P0, and the S ports of the PMOS P0 are serially connected with VDD, The G ports of the PMOS P0 are simultaneously connected to input port, the G ports of the second PMOS P1, the G ports and second of NMOS tube N0 The G ports of NMOS tube N1, the D ports of the PMOS P0 are simultaneously connected to the S ports of the second PMOS P1 and PMOS P2, described The D ports ground connection of PMOS P2, the D ports of the second PMOS P1 and be connected to the G ports of PMOS P2, output port, The G ports of NMOS tube N2 and the D ports of NMOS tube N0, the S ports of the NMOS tube N0 are simultaneously connected to the D ports of the second NMOS tube N1 With the S ports of NMOS tube N2, the S ports ground connection of the second NMOS tube N1, the D ports of the NMOS tube N2 concatenate VDD.

Preferably, the electric capacity C1 and C2 is ceramic condenser.

Preferably, the resistance R1 is fixed carbon resister.

Compared with prior art, the beneficial effects of the utility model are：Ceramic condenser is by electric capacity C1 and C2, is had Temperature in use is higher, and specific capacity is big, and moisture resistance is good, and dielectric loss is smaller, and capacitance temperature factor can be in interior selection on a large scale Feature, can improve the stability of circuit, and resistance R1 is fixed carbon resister, the low cost of fixed carbon resister, stable performance, Standard resistance range Wide, temperature coefficient and voltage coefficient are low, and either power supply fast powering-up still goes up at a slow speed electricity to the circuit, can effectively export multiple Position signal；And the structure is after the completion that resets, in the absence of the DC channel of electric current, so the power consumption of the resetting structure can drop To minimum；And increased R1 resistance and inv0 are designed to schmitt inverter in the resetting structure, ensure that in power supply In the case that quality of voltage is bad, it is to avoid reseting module misoperation, the eft immunity of reset circuit is improved, greatly improved The reliability of reset circuit.

Brief description of the drawings

Fig. 1 is the utility model electrification reset basic circuit diagram；

Fig. 2 is the utility model inv0 electrical block diagrams；

Fig. 3 is existing the first electrification reset circuit figure；

Fig. 4 is existing second electrification reset circuit figure；

Fig. 5 is existing the third electrification reset circuit figure.

Specific embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made The every other embodiment for being obtained, belongs to the scope of the utility model protection.

Fig. 1-5 are referred to, the utility model provides a kind of technical scheme：A kind of electrification reset of super low-power consumption anti-EFT high Circuit, including electric capacity C1, the top port of the electric capacity C1 are simultaneously connected to the S ports of VDD and the first PMOS P1, the electric capacity C1 Bottom port and be connected to the G ports of the first PMOS P1, D the and G ports of the first NMOS tube N1, the first NMOS tube N1's S ports are simultaneously connected to the bottom port of ground wire and electric capacity C2, and the top port of the electric capacity C2 is simultaneously connected to resistance R1 and inV0, described The other end of resistance R1 is connected with the D ports of the first PMOS P1, and the other end of the inV0 is serially connected with inV1, the inV1's The other end is serially connected with RSTB output ports, and the inV0 includes PMOS P0, and the S ports of the PMOS P0 are serially connected with VDD, institute State the G ports of PMOS P0 and be connected to input port, the G ports of the second PMOS P1, the G ports of NMOS tube N0 and the 2nd NMOS The G ports of pipe N1, the D ports of the PMOS P0 are simultaneously connected to the S ports of the second PMOS P1 and PMOS P2, the PMOS The D ports ground connection of P2, the D ports of the second PMOS P1 are simultaneously connected to G ports, output port, the NMOS tube N2 of PMOS P2 G ports and NMOS tube N0 D ports, the S ports of the NMOS tube N0 are simultaneously connected to D ports and the NMOS tube of the second NMOS tube N1 The S ports of N2, the S ports ground connection of the second NMOS tube N1, the D ports of the NMOS tube N2 concatenate VDD.

Wherein, the electric capacity C1 and C2 is ceramic condenser, higher with temperature in use, and specific capacity is big, and moisture resistance is good, Dielectric loss is smaller, and capacitance temperature factor can be the characteristics of interior selection on a large scale, and the resistance R1 is fixed carbon resister, fixed carbon resister Low cost, stable performance, Standard resistance range wide, temperature coefficient and voltage coefficient it is low.

Operation principle：NMOS tube N1 connects into diode, in vdd voltage power up, when vdd voltage is less than During the threshold voltage of NMOS tube N1, NMOS tube N1 is closed, and node A is equal to VDD due to the coupling of C1 electric capacity, PMOS P1 is closed, and node B is equal to VSS due to the coupling of C2 electric capacity, is exported by inv0, inv1 and RSTB Low level, chip reset.

When vdd voltage exceedes the threshold voltage value of NMOS tube N1, NMOS tube N1 conductings, the electricity that node A is coupled by C1 Discharged over the ground by NMOS tube N1, when node A voltage is less than the threshold voltage of PMOS P1, PMOS P1 conductings, VDD passes through P1, R1 are charged to C2 electric capacity, and node B voltage is raised, when node B voltage is increased to the upset point of inv0, inv0 upsets, RSTB Output high level, chip reset terminates, and because the resetting structure has RC electric discharges all the way, RC charges all the way, so low level is multiple Position signal can maintain the sufficiently long time, it is ensured that chip stabilization resets.

If power vd D power-up speeds are than very fast, node A is equal to VDD due to the coupling of C1 electric capacity, and node A Electricity can only be discharged by NMOS tube N1, as long as so the size of reasonable design NMOS tube N1, that is, can guarantee that node A is slow Electric discharge, to meet chip reset；Even if node A is discharged into rapidly the threshold value less than PMOS P1, still there is the second level The process that RC charges, node B voltage still can only slowly rise, so the resetting structure can ensure power vd D power-up speeds When fast, can steady operation；NMOS tube N1, can be realized, using raceway groove NMOS tube long to reduce the velocity of discharge of node A.

When supply voltage rises, it is finally reached after stabilization, the voltage of node A, is discharged through NMOS tube N1, eventually stablizes In the near threshold voltage of NMOS tube N1, now states of the PMOS P1 in fully opening, node B, C voltage, charge through RC, Eventually stablize near vdd voltage.And now branch road 1, branch road 2 all pass through in the absence of direct current, the voltage of node B will not also lead Inv0 is caused to occur ganging up electric current, so the resetting structure is after the completion that resets, power consumption is extremely low.

If during supply voltage poor quality, illustrated with occurring a spike for declining on supply voltage, now The voltage of node C can be higher than vdd voltage, and the parasitic PN diodes of PMOS P1 can be in forward conduction state, the voltage of node B Can be discharged by the parasitic PN diode pairs VDD of R1, node C, PMOS P1, due to increased R1 electricity in the reset circuit Resistance, the velocity of discharge of the node B for slowing down after supply voltage recovery, will not cause node B voltage degradation, and triggering is missed Reset, while the Schmidt phase inverter inv0 being followed by of node B, also further increases the Ability of Resisting Disturbance of node B.

While there has been shown and described that embodiment of the present utility model, for the ordinary skill in the art, It is appreciated that these embodiments can be carried out various changes in the case where principle of the present utility model and spirit is not departed from, repaiies Change, replace and modification, scope of the present utility model is defined by the appended claims and the equivalents thereof.

Claims (3)

1. a kind of electrification reset circuit of super low-power consumption anti-EFT high, including electric capacity C1, it is characterised in that：The top of the electric capacity C1 Portion port is simultaneously connected to the S ports of VDD and the first PMOS P1, and the bottom port of the electric capacity C1 is simultaneously connected to the first PMOS P1's G ports, D the and G ports of the first NMOS tube N1, the S ports of the first NMOS tube N1 are simultaneously connected to the bottom of ground wire and electric capacity C2 Port, the top port of the electric capacity C2 is simultaneously connected to resistance R1 and inV0, the other end of the resistance R1 and the first PMOS P1 The connection of D ports, the other end of the inV0 is serially connected with inV1, and the other end of the inV1 is serially connected with RSTB output ports, institute State S ports of the inV0 including PMOS P0, the PMOS P0 and be serially connected with VDD, the G ports of the PMOS P0 are simultaneously connected to input The G ports of port, the G ports of the second PMOS P1, the G ports of NMOS tube N0 and the second NMOS tube N1, the D of the PMOS P0 Port is simultaneously connected to the S ports of the second PMOS P1 and PMOS P2, the D ports ground connection of the PMOS P2, the 2nd PMOS The D ports of pipe P1 and be connected to PMOS P2 G ports, output port, the G ports of NMOS tube N2 and NMOS tube N0 D ports, institute State the S ports of NMOS tube N0 and be connected to the D ports of the second NMOS tube N1 and the S ports of NMOS tube N2, the second NMOS tube N1 S ports ground connection, the NMOS tube N2 D ports concatenation VDD.

2. the electrification reset circuit of a kind of super low-power consumption according to claim 1 anti-EFT high, it is characterised in that：The electricity Hold C1 and C2 and be ceramic condenser.

3. the electrification reset circuit of a kind of super low-power consumption according to claim 1 anti-EFT high, it is characterised in that：The electricity Resistance R1 is fixed carbon resister.