CN113098460A - Ultra-low power consumption reset circuit - Google Patents
Ultra-low power consumption reset circuit Download PDFInfo
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- CN113098460A CN113098460A CN202110223104.9A CN202110223104A CN113098460A CN 113098460 A CN113098460 A CN 113098460A CN 202110223104 A CN202110223104 A CN 202110223104A CN 113098460 A CN113098460 A CN 113098460A
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- pmos
- nmos
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- power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Abstract
The invention relates to an ultra-low power consumption reset circuit, which comprises a micro-current bias circuit, a positive feedback loop, a phase inverter, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube, wherein the micro-current bias circuit is connected with the positive feedback loop; the micro-current bias circuit is used for generating bias voltage; the bias signal output end of the micro-current bias circuit is respectively connected to the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, the source electrodes of the first PMOS tube and the second PMOS tube are connected to a power supply, the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected to the grid electrode of the second PMOS tube, the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube are connected to the signal input end of the phase inverter, and the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded. The ultra-low power consumption reset circuit has the advantages of simple structure, low cost and low static power consumption.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an ultra-low power consumption reset circuit.
Background
In integrated circuits with digital circuits, a reset circuit configuration is basically required, which functions to configure the state of the digital circuit to a desired initial state during power-up, preventing the occurrence of intermediate or indeterminate states.
There are two main types of commonly used reset circuits. The first reset circuit is reset by capacitor charging to generate hysteresis; the second type of reset circuit is in a continuous conducting state and is reset by a bias setting.
First type reset circuit: the structure is simple, but the reset point is not controllable, the capacitor needs a larger area, and the cost is high;
reset circuit of the second kind: due to continuous conduction, large static power consumption exists, and meanwhile, the structure is complex and the cost is high.
Disclosure of Invention
The invention aims to provide an ultra-low power consumption reset circuit which is simple in structure, low in cost and low in static power consumption.
In order to solve the technical problem, the ultra-low power consumption reset circuit comprises a micro-current bias circuit, a phase inverter, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube;
the micro-current bias circuit is used for generating bias voltage, and the generated bias voltage provides bias signals for the first NMOS transistor and the second NMOS transistor;
the bias signal output end of the micro-current bias circuit is respectively connected to the grid electrode of a first PMOS (P-channel metal oxide semiconductor) tube, the grid electrode of a first NMOS (N-channel metal oxide semiconductor) tube and the grid electrode of a second NMOS tube, the source electrodes of the first PMOS tube and the second PMOS tube are connected to a power supply, the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected to the grid electrode of the second PMOS tube, the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube are connected to the signal input end of a phase inverter, and the source electrode of the first NMOS tube and the source electrode of;
preferably, the ultra-low power consumption reset circuit further includes a positive feedback loop, one end of the positive feedback loop is connected to the gate of the second PMOS transistor, and the other end of the positive feedback loop is connected to the drain of the second PMOS transistor.
Preferably, the width-to-length ratio of the first PMOS transistor is an inverse ratio, the on-state current of the first PMOS transistor is greater than the on-state current of the first NMOS transistor, the width-to-length ratio of the second NMOS transistor is greater than the width-to-length ratio of the first NMOS transistor, and the on-state current of the second PMOS transistor is greater than the on-state current of the second NMOS transistor.
Preferably, the trickle bias circuit is formed of a large resistor.
Preferably, the micro-current bias circuit is composed of a plurality of inverse proportion tubes.
The invention has the beneficial effects that:
1. the ultra-low power consumption reset circuit does not need to be provided with a starting circuit and a capacitor, and has simple structure and low cost;
2. in a normal working state (namely after the reset is finished), the micro-current bias circuit, the first NMOS tube and the first PMOS tube are in a working state, and because the current of the ultra-low power consumption reset circuit is only influenced by the micro-current bias circuit, the static working current of the ultra-low power consumption reset circuit can be controlled only by designing the current of the micro-current bias circuit to be very small, so that the static power consumption is low;
3. the reset voltage can be adjusted by adjusting the device size of the first PMOS tube, the bias current of the micro-current bias circuit, the device size of the first NMOS tube and the like;
4. by additionally arranging the positive feedback loop, the grid voltage of the second PMOS pipe P2 can be pulled down at high speed, so that the second PMOS pipe P2 is conducted more quickly and thoroughly, and the reset performance is improved.
Drawings
FIG. 1 is a schematic diagram of a reset circuit of a first type of the prior art;
FIG. 2 is a block diagram of a second type of reset circuit of the prior art;
fig. 3 is a schematic circuit diagram of embodiment 1 of the present invention.
Detailed Description
The present invention is further described below with reference to comparative example 1, comparative example 2, examples and the accompanying drawings.
Comparative example 1:
fig. 1 is a schematic diagram of a first reset circuit in the prior art, which includes a resistor R, a first capacitor C1, a schmitt trigger SMT, and a second inverter INV2, wherein a first end of the resistor R is connected to a power supply, a second end of the resistor R, a first end of the first capacitor C1, and an input end of the schmitt trigger SMT are connected to an intersection a, an output end of the schmitt trigger SMT is connected to an input end of the second inverter INV2, and an output signal is output from an output end of the second inverter INV 2.
The first type of reset circuit has a simple structure, and when the power supply is powered up quickly, the voltage at the junction a rises slowly because the first capacitor C1 needs to be charged at the initial stage, which has a hysteresis effect. The initial output of the Schmitt trigger SMT is high level, at the moment, the output signal is in a reset state, namely the output signal is a reset signal; when the first capacitor C1 is charged to a high level, the voltage at junction a goes high and the output of the schmitt trigger SMT flips to a low level, at which point the reset state is ended.
The first type of reset circuit has the advantages of simple structure and no static power consumption; the disadvantage is that a large-area capacitor is needed, the reset point cannot be set, and if the power supply is slowly electrified, the capacitor has enough time to be fully charged, so that the reset signal cannot be generated possibly.
Comparative example 2:
fig. 2 is a block diagram of a second type of reset circuit in the prior art, which includes a start-up circuit 21, a bias structure 22, a reference voltage module 23, a comparison circuit 24, and a second capacitor C2.
The start-up circuit 21 provides a start-up voltage or current to the biasing structure 22 at the initial power-up, and then turns off; the bias structure 22 provides a bias voltage or current to the reference voltage module 23, and the bias current generated by the bias structure 22 charges the second capacitor C2 with a constant current.
In the initial state, the voltage of the reference voltage module 23 is higher than the voltage of the second capacitor C2, and at this time, the output signal is in the reset state; when the voltage of the second capacitor C2 reaches, approaches, or exceeds the voltage of the reference voltage block 23, the output of the comparator circuit 24 flips, ending the reset state.
The second type of reset circuit has larger static power consumption due to continuous conduction, and has a complex structure and high cost.
Example 1:
as shown in fig. 1, the ultra low power reset circuit of the present invention includes a micro-current bias circuit 1, an inverter INV1, a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2; the micro-current bias circuit 1 is used for generating a bias voltage, and the generated bias voltage provides bias signals for the first NMOS transistor N1 and the second NMOS transistor N2; the bias signal output end of the micro-current bias circuit 1 is respectively connected to the gate of a first PMOS transistor P1, the gate of a first NMOS transistor N1 and the gate of a second NMOS transistor N2, the sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to a power supply, the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 are connected to the gate of the second PMOS transistor P2, the drain of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 are connected to the signal input end of the inverter INV1, and the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are grounded.
Specifically, the ultra-low power consumption reset circuit further includes a positive feedback loop 2, wherein one end of the positive feedback loop 2 is connected to the gate of the second PMOS transistor P2, and the other end is connected to the drain of the second PMOS transistor P2.
Specifically, the width-to-length ratio of the first PMOS transistor P1 is an inverse ratio, the on-state current of the first PMOS transistor P1 is greater than the on-state current of the first NMOS transistor, the width-to-length ratio of the second NMOS transistor N2 is greater than the width-to-length ratio of the first NMOS transistor N1, and the on-state current of the second PMOS transistor P2 is greater than the on-state current of the second NMOS transistor N2.
Specifically, the microcurrent bias circuit 1 is composed of a large resistor.
Specifically, the micro-current bias circuit 1 is composed of a plurality of inverse ratio tubes.
Working principle of example 1: on power up, the trickle bias circuit 1 is started. The first NMOS transistor N1 has a very small on-current, and its gate voltage is slightly lower than the turn-on voltage of a normal NMOS transistor. Since the width-to-length ratio of the first PMOS transistor P1 is inverse (i.e. the channel length is greater than the channel width), the turn-on voltage is large, and the gate has a voltage, therefore, in the initial stage of power-up, its VGS is not sufficient to turn on the first PMOS transistor P1; the grid voltage of the second PMOS tube P2 is pulled to be low level due to the conduction of the first NMOS tube N1, the second PMOS tube P2 is conducted, and the drain electrode of the second PMOS tube P2 outputs high level due to the fact that the conduction current of the second PMOS tube P2 is larger than the conduction current of the second NMOS tube N2; in the conversion process, the positive feedback loop 2 is arranged to accelerate the grid voltage of the second PMOS pipe P2 to be pulled down, so that the second PMOS pipe P2 is conducted more quickly and thoroughly; the reset signal output at this time resets the circuit.
With the rise of the power supply voltage, the gate voltages of the first NMOS transistor N1 and the first PMOS transistor P1 are basically unchanged, the first PMOS transistor P1 gradually enters a conducting state, when the conducting current of the first PMOS transistor P1 is larger than the conducting current of the first NMOS transistor N1, the gate voltage of the second PMOS transistor P2 is gradually pulled high, the second PMOS transistor P2 gradually enters a stopping state, and the output voltage of the drain electrode of the second PMOS transistor P2 is gradually reduced; through the positive feedback loop 2, the grid voltage of the second PMOS pipe P2 is increased in an accelerated manner, the second PMOS pipe P2 is cut off rapidly, and the grid electrode of the second NMOS pipe N2 always has voltage, so that the drain electrodes of the second NMOS pipe N2 and the second PMOS pipe P2 output low level, the output of the inverter INV1 is inverted, and the reset state is ended.
When the power voltage drops, the first PMOS transistor P1 enters the off state first, and the output signal is inverted and enters the reset state.
In a normal working state (namely after the reset is finished), the micro-current bias circuit 1, the first NMOS transistor N1 and the first PMOS transistor P1 are in a working state, and as the current of the ultra-low power consumption reset circuit is only influenced by the micro-current bias circuit 1, the static working current of the ultra-low power consumption reset circuit can be controlled only by designing the current of the micro-current bias circuit 1 to be very small.
The reset voltage can be adjusted by adjusting the device size of the first PMOS transistor P1, the magnitude of the bias current of the micro current bias circuit, the device size of the first NMOS transistor N1, and the like.
In summary, the principle of the present invention is to utilize the turn-on voltage of the MOS transistor, configure parameters such as current and size of the device, and accelerate the speed by positive feedback, thereby performing state switching under different voltage states, and implementing the reset function.
Claims (4)
1. An ultra-low power consumption reset circuit, characterized by: the micro-current bias circuit comprises a micro-current bias circuit (1), an inverter (INV1), a first PMOS (P1), a second PMOS (P2), a first NMOS (N1) and a second NMOS (N2);
the micro-current bias circuit (1) is used for generating a bias voltage, and the generated bias voltage provides bias signals for the first NMOS transistor (N1) and the second NMOS transistor (N2);
the bias signal output end of the micro-current bias circuit (1) is respectively connected to a grid electrode of a first PMOS (P1), a grid electrode of a first NMOS (N1) and a grid electrode of a second NMOS (N2), source electrodes of the first PMOS (P1) and the second PMOS (P2) are connected to a power supply, a drain electrode of the first PMOS (P1) and a drain electrode of the first NMOS (N1) are connected to a grid electrode of the second PMOS (P2), a drain electrode of the second PMOS (P2) and a drain electrode of the second NMOS (N2) are connected to a signal input end of an inverter (INV1), and a source electrode of the first NMOS (N1) and a source electrode of the second NMOS (N2) are grounded.
2. The ultra-low power consumption reset circuit of claim 1, wherein: the transistor also comprises a positive feedback loop (2), wherein one end of the positive feedback loop (2) is connected to the grid electrode of the second PMOS tube (P2), and the other end of the positive feedback loop is connected to the drain electrode of the second PMOS tube (P2).
3. The ultra-low power consumption reset circuit of claim 1, wherein: the width-length ratio of the first PMOS tube (P1) is an inverse ratio, the on-state current of the first PMOS tube (P1) is larger than the on-state current of the first NMOS tube (N1), the width-length ratio of the second NMOS tube (N2) is larger than the width-length ratio of the first NMOS tube (N1), and the on-state current of the second PMOS tube (P2) is larger than the on-state current of the second NMOS tube (N2).
4. An ultra-low power consumption reset circuit according to any one of claims 1 to 3, characterized in that: the micro-current bias circuit (1) is formed by connecting a plurality of inverse ratio tubes in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110223104.9A CN113098460B (en) | 2021-03-01 | 2021-03-01 | Ultra-low power consumption reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110223104.9A CN113098460B (en) | 2021-03-01 | 2021-03-01 | Ultra-low power consumption reset circuit |
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| Publication Number | Publication Date |
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| CN113098460A true CN113098460A (en) | 2021-07-09 |
| CN113098460B CN113098460B (en) | 2022-02-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114785331A (en) * | 2022-04-01 | 2022-07-22 | 无锡力芯微电子股份有限公司 | Adjustable high-precision reset circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187476A (en) * | 2007-01-30 | 2008-08-14 | Toshiba Microelectronics Corp | Power-on reset circuit |
| CN105591637A (en) * | 2015-11-24 | 2016-05-18 | 居水荣 | Automatic reset module in integrated circuit |
| CN206209581U (en) * | 2016-11-15 | 2017-05-31 | 无锡中微爱芯电子有限公司 | A kind of electrification reset circuit of super low-power consumption anti-EFT high |
| CN112290923A (en) * | 2020-10-30 | 2021-01-29 | 广州鸿博微电子技术有限公司 | Low-power-consumption power-on reset circuit and method based on bias circuit |
-
2021
- 2021-03-01 CN CN202110223104.9A patent/CN113098460B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187476A (en) * | 2007-01-30 | 2008-08-14 | Toshiba Microelectronics Corp | Power-on reset circuit |
| CN105591637A (en) * | 2015-11-24 | 2016-05-18 | 居水荣 | Automatic reset module in integrated circuit |
| CN206209581U (en) * | 2016-11-15 | 2017-05-31 | 无锡中微爱芯电子有限公司 | A kind of electrification reset circuit of super low-power consumption anti-EFT high |
| CN112290923A (en) * | 2020-10-30 | 2021-01-29 | 广州鸿博微电子技术有限公司 | Low-power-consumption power-on reset circuit and method based on bias circuit |
Non-Patent Citations (1)
| Title |
|---|
| KUO-HSING CHEN,ET AL: "A fast-lock DLL with power-on reset circuit", 《2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (IEEE CAT. NO.04CH37512)》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114785331A (en) * | 2022-04-01 | 2022-07-22 | 无锡力芯微电子股份有限公司 | Adjustable high-precision reset circuit |
| CN114785331B (en) * | 2022-04-01 | 2023-09-19 | 无锡力芯微电子股份有限公司 | Adjustable high-precision reset circuit |
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| CN113098460B (en) | 2022-02-11 |
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