CN112290923A - Low-power-consumption power-on reset circuit and method based on bias circuit - Google Patents

Low-power-consumption power-on reset circuit and method based on bias circuit Download PDF

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Publication number
CN112290923A
CN112290923A CN202011197700.6A CN202011197700A CN112290923A CN 112290923 A CN112290923 A CN 112290923A CN 202011197700 A CN202011197700 A CN 202011197700A CN 112290923 A CN112290923 A CN 112290923A
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tube
power
nmos tube
circuit
nmos
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CN112290923B (en
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郑轩
宋振宇
黄杨程
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Guangzhou Hongbo Microelectronics Technology Co ltd
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Guangzhou Hongbo Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches

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Abstract

The embodiment of the application discloses a low-power-consumption power-on reset circuit and a method based on a bias circuit; the method comprises the following steps: a low power consumption bias circuit and a power-on reset circuit; the low-power consumption bias circuit is connected with the power-on reset circuit; the low-power consumption bias circuit comprises a first bias current output end, a second bias current output end and a high-potential output end; the power-on reset circuit includes: a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, a seventh NMOS tube, a Schmidt trigger and a rising edge delayer; the whole circuit structure of this application embodiment is simple, the component is few, the electric current branch road is few, the component in the electric current of every branch road can be very low and go up the electricity front circuit is out of work, thereby reduce the circuit consumption, reduce the consumption of battery, use third NMOS pipe and fourth PMOS pipe and the multiplexing low-power consumption biasing circuit of preceding stage to replace the resistance that uses usually for the low-power consumption and reach tens of megabits big resistance, the area of reduction chip that can show, save the cost of chip greatly.

Description

Low-power-consumption power-on reset circuit and method based on bias circuit
Technical Field
The embodiment of the application relates to the technical field of reset circuits, in particular to a low-power-consumption power-on reset circuit and method based on a bias circuit.
Background
The MCU, i.e., a micro control unit, also called a single-chip microcomputer or a single-chip microcomputer, properly reduces the frequency and specification of the cpu, and integrates peripheral interfaces such as a memory, a counter, a USB, a UART, a PLC, a DMA, a GPIO, etc., a detection circuit such as an analog-to-digital converter, a comparator, an operational amplifier, etc., and even an LCD driving circuit on a single chip to form a chip-level computer, which is controlled in different combinations for different applications.
In recent years, with the great development of the internet of things and artificial intelligence, the difference between consumer electronics and computers is smaller and smaller, and the functional requirements of consumer electronics are higher and the design is more and more complex. Therefore, many consumer electronics products use the MCU as the core of their product control. As handheld devices become more and more mainstream of consumer electronics, the requirement of low power consumption and low cost of the MCU also becomes a mainstream trend of the current development. For example, in the application of the MCU to the bluetooth device, the MCU is generally required to wake up every several hundred milliseconds to perform data processing, so that the MCU is mostly in a sleep mode, i.e., a low power consumption mode, and thus the MCU is required to have low power consumption enough to meet the requirement of long-time battery operation when sleeping. When the MCU does not need to work, the MCU enters a stop mode, the power consumption of the MCU which is also needed is as low as possible, the energy of the battery is not consumed as far as possible when the MCU does not work, and the service life of the battery is prolonged.
The power-on reset circuit is a circuit which must exist in the MCU, and has the function of providing an initial state for the MCU mode selection circuit after power-on, so that the MCU works in a default normal mode, and the MCU cannot normally start and work due to the fact that the MCU mistakenly enters a low power consumption mode or a stop mode during starting. When the power supply of the MCU is too low, the power-on reset circuit needs to reset all circuits of the MCU, so that the situation that the MCU executes instructions incorrectly or reads and writes a memory incorrectly to cause unacceptable errors of a program under the condition that the power supply voltage of the MCU is too low is avoided. The existing MCU power-on reset circuit is a normally open circuit, and the power consumption and the cost in the circuit are high.
Disclosure of Invention
The embodiment of the application provides a low-power-consumption power-on reset circuit and a method based on a bias circuit, and aims to solve the problems that in the prior art, a power-on reset circuit of an MCU is a normally open circuit, and power consumption and cost in the circuit are high.
In a first aspect, an embodiment of the present application provides a bias circuit-based low-power-consumption power-on reset circuit, including: a low power consumption bias circuit and a power-on reset circuit; the low-power consumption bias circuit comprises a first bias current output end, a second bias current output end and a high-potential output end; the power-on reset circuit includes: the device comprises a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, a seventh NMOS tube, a Schmidt trigger and a rising edge delayer.
The source electrode of the third PMOS tube is connected with a power supply end, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube; the source electrode of the fourth PMOS tube is connected with a power supply end, the grid electrode of the fourth PMOS tube is connected with the first bias current output end, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and the input end of the Schmitt trigger; the source electrode of the third NMOS tube is connected with a grounding end, and the grid electrode of the third NMOS tube is connected with the second bias current output end; the source electrode of the fourth NMOS tube is connected with a grounding end; the gate of the seventh NMOS transistor is connected to the high-potential output terminal, the source is connected to the ground terminal, the drain is connected to the output terminal of the schmitt trigger and the input terminal of the rising edge delayer, and the output terminal of the rising edge delayer outputs a delay signal.
Further, the low power consumption bias circuit comprises a starting circuit and a bias current generating circuit; the starting circuit is connected with the bias current generating circuit;
the start-up circuit includes: a sixth PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a first capacitor; the source electrode of the sixth PMOS tube is connected with a power supply end and the first end of the first capacitor, the grid electrode of the sixth PMOS tube is connected with a grounding end, and the drain electrode of the sixth PMOS tube is connected with the second end of the first capacitor, the drain electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the bias current generating circuit, and the source electrode of the fifth NMOS tube is connected with a grounding end; and the drain electrode of the sixth NMOS tube is connected with the low-power consumption bias current to generate current, and the source electrode of the sixth NMOS tube is connected with a grounding end.
Further, the bias current generating circuit includes: the NMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first resistor;
the source electrode of the first PMOS tube is connected with a power supply end, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the first bias current output end and the drain electrode of the sixth MOS tube, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the source electrode of the second PMOS tube is connected with a power supply end, the grid electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the first NMOS tube is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the second NMOS tube, the second bias current output end and the grid electrode of the fifth NMOS tube; and the source electrode of the second NMOS tube is connected with a ground terminal through the first resistor.
Further, the power-on reset circuit further comprises a second capacitor and a fifth resistor; the first end of the fifth resistor is connected with the grid electrode of the third PMOS tube, the second end of the fifth resistor is connected with the grid electrode of the fourth NMOS tube and the first end of the second capacitor, and the second end of the second capacitor is connected with the grounding end.
Furthermore, the transistor also comprises a fifth PMOS tube; the bias current generating circuit further comprises a third bias current output terminal; the source electrode of the fifth PMOS tube is connected with a power supply end, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube is connected with a third bias current output end, and the third bias current output end is connected with the grid electrode of the first PMOS tube.
In a second aspect, an embodiment of the present application provides a low power consumption power-on reset method based on a bias circuit, where the method includes:
when the power supply terminal is powered on slowly, Vdd<VGSMN1+minVDSMP1When the low-power consumption bias circuit does not work, no current is generated, the third NMOS tube, the fourth NMOS tube and the fourth PMOS tube are in a cut-off state, and the second node is in a high-resistance state; resetting the output signal in an indeterminate state;
when Vdd is VGSMN1+minVDSMP1When the bias current of the low-power consumption bias circuit is input into the third NMOS tube and the fourth PMOS tube, V1 is Vdd-VGSMP3＝minVDSMP1<VTHMN4The fourth NMOS transistor is cut off, the fourth PMOS transistor pulls up V2 to Vdd, V2 is reversed by the Schmitt trigger,the reset output signal is 0;
when Vdd is VGSMP3+VTHMN4When V1 is Vdd-VGSMP3＝VTHMN4The fourth NMOS transistor is turned on and pulls down V2 to 0, after V2 is reversed by the schmitt trigger, the reset output signal generates a rising edge reset signal from 0 to 1 after td time delay, and the reset state is finished, so that the MCU starts to operate normally.
When the power supply terminal is powered on rapidly, Vdd>VGSMP3+VTHMN4During the starting period of the low-power consumption bias circuit, the fourth NMOS tube is conducted to pull-down V2, and the fourth PMOS tube is conducted to pull-up V2, so that the second node is in an indeterminate state; receiving the high potential of the low-power-consumption biasing circuit through the grid electrode of the seventh NMOS tube, and reducing the level of the output end of the Schmitt trigger to enable the output of the reset signal to be 0;
after the low-power-consumption circuit is started, the potential of the low-power-consumption bias circuit received by the grid electrode of the seventh NMOS tube is 0, the seventh NMOS tube is cut off, the Schmitt trigger outputs a normal signal, after the reset output signal is delayed for td time, a rising edge reset signal from 0 to 1 is generated, and the reset state is finished, so that the MCU starts to work normally;
wherein Vdd is the voltage of the power supply terminal; VGSMN1The grid source voltage of the first NMOS tube; minVDSMP1The minimum drain-source voltage of the first PMOS tube; VTHMN4The threshold voltage of the fourth NMOS transistor; VGSMP3The grid source voltage of the third NMOS tube; v1 is the voltage of a first node, and the first node is the connection point of the grid of the fourth NMOS tube and the grid of the third PMOS tube; and V2 is the voltage of a second node, and the second node is the connection point of the drain electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the output end of the Schmitt trigger.
Further, the low-power bias circuit does not work and does not generate current; the third NMOS transistor, the fourth NMOS transistor and the fourth PMOS transistor are in a cut-off state, and the cut-off state comprises the following steps:
the low-power consumption bias circuit does not work, and no bias current is generated; the third NMOS tube and the fourth PMOS tube are in a cut-off state; the grid voltage of the third PMOS tube is equal to V1, and the grid voltage of the third PMOS tube rises with the voltage of the power supply end but is smaller than the voltage of the power supply end and smaller than the threshold voltage of the fourth NMOS tube, so that the fourth NMOS tube is in a cut-off state.
Further, the bias current is input to the third NMOS transistor and the fourth PMOS transistor, where V1 is Vdd-VGSMP3＝minVDSMP1<VTHMN4The method comprises the following steps:
the low-power-consumption current reference circuit starts to work and generates bias current on the first NMOS tube and the second NMOS tube, and the bias current flows into the third NMOS tube and the fourth PMOS tube to generate initial voltage for the power-on reset circuit; the current of the third NMOS transistor flows into the drain of the third PMOS transistor, so that the gate voltage of the third PMOS transistor, i.e., V1, becomes Vdd-VGSMP3＝minVDSMP1<VTHMN4。
Further, the receiving of the high potential of the low power consumption bias circuit through the gate of the seventh NMOS transistor reduces the level of the output terminal of the schmitt trigger, including:
the power supply end is quickly electrified, the resistance of the sixth PMOS tube is high, the pull-up current is small, the third node is coupled to a high potential by the first capacitor, the grid electrode of a seventh NMOS tube connected with the third node is the high potential, and the fourth NMOS tube strongly pulls down the level of the output end of the Schmitt trigger;
and V3 is the drain voltage of a third node, and the third node is the connection point of the drain of the sixth PMOS tube, the drain of the fifth NMOS tube and the gate of the sixth NMOS tube.
Further, the receiving of the potential of the low power consumption bias circuit through the gate of the seventh NMOS transistor is 0, the seventh NMOS transistor is turned off, and the schmitt trigger outputs a normal signal, which includes:
after the low-power-consumption bias circuit is started, the sixth NMOS tube pulls down the grid voltages of the first PMOS tube and the second PMOS tube until current is generated, the grids of the first NMOS tube, the second NMOS tube and the fifth NMOS tube are changed to be high, the fifth NMOS tube pulls down V3 to 0, the grid potential of a seventh NMOS tube connected with the third node is 0, the seventh NMOS tube is cut off and stops the level of the output end of the strong pull-down Schmitt trigger, and the Schmitt trigger outputs a normal signal.
According to the embodiment of the application, the power-on reset circuit with a simple structure is arranged, and before power-on, an MOS (metal oxide semiconductor) tube in the circuit is cut off, so that power is not consumed; through the inflow of bias current in the power-on process, the third PMOS tube, the fourth PMOS tube and the third NMOS tube are conducted, and a reset signal is output to be 0 through the Schmidt trigger; the power-on voltage is increased, the fourth NMOS tube is conducted, and the output of a delay reset signal from 0 to 1 is realized through the pull-up edge delayer, so that the MCU works normally; meanwhile, when the voltage of the input end of the Schmitt trigger is in an unsteady state, the level of the output end of the Schmitt trigger is pulled down through a seventh NMOS tube, so that the output reset signal is 0, and when the voltage of the input end of the Schmitt trigger is stable, the output of a delay reset signal from 0 to 1 is realized, so that the MCU normally works; the whole circuit is simple in structure, low in power consumption, low in battery consumption and low in cost.
Drawings
Fig. 1 is a schematic structural diagram of a low-power-consumption power-on reset circuit based on a bias circuit according to an embodiment of the present disclosure;
FIG. 2 is a timing diagram of a power-on reset circuit when the power supply terminal is powered on slowly;
fig. 3 is a timing diagram of the power-on reset circuit when the power source terminal is quickly powered on.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, specific embodiments of the present application will be described in detail with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some but not all of the relevant portions of the present application are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
According to the low-power-consumption power-on reset circuit based on the bias circuit, the power-on reset circuit with a simple structure is arranged, and before power is on, an MOS (metal oxide semiconductor) tube in the circuit is cut off, so that power is not consumed; through the inflow of bias current in the power-on process, the third PMOS tube, the fourth PMOS tube and the third NMOS tube are conducted, and a reset signal is output to be 0 through the Schmidt trigger; the power-on voltage is increased, the fourth NMOS tube is conducted, and the output of a delay reset signal from 0 to 1 is realized through the pull-up edge delayer, so that the MCU works normally; meanwhile, when the voltage of the input end of the Schmitt trigger is in an unsteady state, the level of the output end of the Schmitt trigger is pulled down through a seventh NMOS tube, so that the output reset signal is 0, and when the voltage of the input end of the Schmitt trigger is stable, the output of a delay reset signal from 0 to 1 is realized, so that the MCU normally works; the whole circuit is simple in structure, few in elements and few in current branches, the current of each branch can be very low, and the elements in the circuit do not work before power on, so that the power consumption of the circuit is reduced, the consumption of a battery is reduced, a third NMOS (N-channel metal oxide semiconductor) tube, a fourth PMOS (P-channel metal oxide semiconductor) tube and a low-power-consumption bias circuit multiplexed by a preceding stage are used for replacing a large resistor with the resistance value of tens of megabytes, which is usually used for low power consumption, the area of a chip can be remarkably reduced, and the cost of the. The existing MCU power-on reset circuit is a normally open circuit, so that the power consumption of the circuit is high; meanwhile, when the MCU enters the stop mode, the circuit still has high power consumption, which needs to consume the energy of the battery, and affects the service time of the battery. Therefore, the low-power-consumption power-on reset circuit based on the bias circuit is provided, so that the power consumption of the whole power-on reset circuit is reduced, the consumption of a battery is reduced, and the cost is saved.
Fig. 1 is a schematic structural diagram of a low-power-consumption power-on reset circuit based on a bias circuit according to an embodiment of the present disclosure. Referring to fig. 1, the circuit specifically includes: a low power bias circuit based power-on-reset circuit 300; the low power consumption bias circuit comprises a starting circuit 100 and a bias current generating circuit 200; the start-up circuit 100 is connected to the bias current generating circuit 200.
The power-on reset circuit includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a seventh NMOS transistor MN7, a schmitt trigger 310, and a rising edge delay 320.
The start-up circuit 100 includes: a sixth PMOS transistor MP6, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first capacitor C1, and a high-voltage output terminal.
The bias current generating circuit 200 includes: the transistor comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, a first bias current output end and a second bias current output end.
The source electrode of the third PMOS transistor MP3 is connected to a power source terminal, the gate electrode of the third PMOS transistor MP3 is connected to the gate electrode of the fourth NMOS transistor MN4, and the drain electrode of the third PMOS transistor MP3 is connected to the drain electrode of the third NMOS transistor MN 4; the source electrode of the fourth PMOS tube MP4 is connected with a power supply end, the grid electrode of the fourth PMOS tube MP4 is connected with the first bias current output end, and the drain electrode of the fourth PMOS tube MP4 is connected with the drain electrode of the fourth NMOS tube MN4 and the input end of the Schmitt trigger 310; the source electrode of the third NMOS transistor MN3 is connected with the ground terminal, and the grid electrode of the third NMOS transistor MN3 is connected with the second bias current output end; the source electrode of the fourth NMOS transistor MN4 is connected with the ground terminal; the gate of the seventh NMOS transistor MN7 is connected to the high-voltage output terminal, the source is connected to the ground, the drain is connected to the output terminal of the schmitt trigger 310 and the input terminal of the rising edge delay 320, and the output terminal por _ in of the rising edge delay 320 outputs the delay signal.
A source electrode of the sixth PMOS transistor MP6 is connected to a power supply terminal and a first end of the first capacitor C1, a gate electrode is connected to a ground terminal, and a drain electrode is connected to a second end of the first capacitor C1, a drain electrode of the fifth NMOS transistor MN5, and a gate electrode of the sixth NMOS transistor MN 6; the grid electrode of the fifth NMOS transistor MN5 is connected with the bias current generating circuit 200, and the source electrode is connected with the grounding end; the drain electrode of the sixth NMOS transistor MN6 is connected with the low-power consumption bias current generating circuit, and the source electrode is connected with the grounding end.
The source electrode of the first PMOS tube MP1 is connected with a power supply end, the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the second PMOS tube MP2, the first bias current output end and the drain electrode of the sixth MOS tube, and the drain electrode of the first NMOS tube MN1 is connected with the drain electrode of the first NMOS tube; the source electrode of the second PMOS tube MP2 is connected with a power supply end, the grid electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube MN2, and the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube MN 2; the drain electrode of the first NMOS transistor MN1 is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the second NMOS transistor MN2, the second bias current output end and the grid electrode of the fifth NMOS transistor MN 5; the source of the second NMOS transistor MN2 is connected to ground through a first resistor R1.
In this embodiment, the start-up circuit 100 is obtained by connecting the sixth PMOS transistor MP6, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6 and the first capacitor C1. When the power supply terminal voltage is electrified at a low speed, the sixth PMOS transistor MP6 is a high-resistance PMOS transistor resistor, the potential of the third node is pulled high by the sixth PMOS transistor MP6, at this time, the sixth NMOS transistor MN6 pulls down the gate potentials of the first PMOS transistor MP1 and the second PMOS transistor MP2 until current is generated, the I _ MN1 and the I _ MN2 are separated from a 0 state, the potentials of the gates of the first NMOS transistor MN1, the second NMOS transistor MN2 and the fifth NMOS transistor MN5 are raised, the potential of the fifth NMOS transistor MN5 pulls down the third node to 0, the sixth NMOS transistor MN6 is cut off, and the starting process is ended. In addition, when the power supply end voltage is quickly electrified, the potential of the third node is coupled to a high potential through the first capacitor C1, at this time, the sixth NMOS tube MN6 pulls down the gates of the first PMOS tube MP1 and the second PMOS tube MP2 until current is generated, the I _ MN1 and the I _ MN2 are separated from a 0 state, the gates of the first NMOS tube MN1, the second NMOS tube MN2 and the fifth NMOS tube MN5 are heightened, the potential of the fifth NMOS tube MN5 pulls down the third node of the node is 0, the sixth NMOS tube MN6 is cut off, and the starting process is ended.
In this embodiment, the bias current generating circuit 200 is obtained by connecting the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, the second NMOS transistor MN2 and the first resistor R1, wherein the ratio of the channel width-length ratio of the first PMOS transistor MP1 to the channel width-length ratio of the second PMOS transistor MP2 is set to 1:1 (W/L)MP1＝(W/L)MP2，It is understood that the current of the first PMOS transistor MP1 is equal to the current of the second PMOS transistor MP2, i.e., I _ MP1 is equal to I _ MP2, and the current of the first NMOS transistor MN1 is equal to the current of the second NMOS transistor MN2, i.e., I _ MN1 is equal to I _ MN 2. Because the grid electrode of the first NMOS tube MN1 is connected with the grid electrode of the second NMOS tube MN2, the grid electrode voltage of the first NMOS tube MN1 is equal to the grid electrode voltage of the second NMOS tube MN2, namely VGMN1＝VGMN2It is understood that VGSMN1＝VGSMN2+ I × R1. Is provided with the firstThe ratio of the channel width length ratio of the NMOS tube MN1 to the channel width length ratio of the NMOS tube MN2 is 1: M (W/L)MN1＝(W/L)MN2(ii) a/M; it can be understood that the general formula (W/L)MN1＝(W/L)MN2VGS known by the term of/MMN1>VGSMN2The result is I _ MN1 ═ I _ MN2 ═ I (VGS)MN1-VGSMN2)/R1。
In this embodiment, the power-on reset circuit is obtained by connecting the third PMOS transistor MP3, the fourth PMOS transistor MP4, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the seventh NMOS transistor MN7, the schmitt trigger 310 and the rising edge delay 320. The gate voltage VG of the third NMOS transistor MN3MN3＝Vdd-VGSMP3The voltage of the first node is connected to the gate voltage of the third PMOS transistor MP3, and V1 is VGMN3. Specifically, when the voltage of the first node is lower than the threshold voltage VTH of the fourth NMOS transistor MN4MN4Is Vdd<VGSMP3+VTHMN4When the second NMOS transistor MN4 is turned off, since the fourth PMOS transistor MP4 is connected to the second PMOS transistor MP2 through the second bias current output terminal, that is, the current of the fourth PMOS transistor MP4 is equal to the current of the second PMOS transistor MP2, the voltage of the second node is pulled high by the fourth PMOS transistor MP4, and is inverted through the schmitt trigger 310 to output a reset signal of 0. Specifically, when the voltage of the first node is greater than the threshold voltage VTH of the fourth NMOS transistor MN4MN4When is, i.e. Vdd>VGSMP3+VTHMN4When the fourth NMOS transistor MN4 is turned on, the potential of the second node is pulled low, and a rising edge reset signal of 0 to 1 is output after the inversion of the schmitt trigger 310 and the delay of the rising edge delay 320.
It will be appreciated that the schmitt trigger 310 functions to filter out glitch voltages at the first node.
It is understood that the seventh NMOS transistor MN7 is a strong pull-down transistor, and is used to force the output of the schmitt trigger 310 to be pulled low when the third node is coupled to a high voltage by the first capacitor C1 during fast power-up, thereby providing an initial value of 0 for the output reset signal.
It will be appreciated that the role of the rising edge delay 320 is when Vdd>VGSMP3+VTHMN4The time-of-flight deems that the power-on reset circuit can releaseThe MCU can start working by putting a reset signal. By delaying the rising edge delay 320 by time td, the power-on reset circuit provides a low level reset signal of time td before the MCU operates normally.
Specifically, the power-on reset circuit further includes a second capacitor C2 and a fifth resistor R5; a first end of the fifth resistor R5 is connected to a gate of the third PMOS transistor MP3, a second end of the fifth resistor R5 is connected to the gate of the fourth NMOS transistor MN4 and the first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to a ground terminal. The low-pass filter formed by the fifth resistor R5 and the second capacitor C2 is used for filtering high-frequency glitches on the gate of the third PMOS transistor MP3 and preventing the fourth NMOS transistor MN4 from pulling down the potential of the first node by mistake.
Specifically, the transistor further comprises a fifth PMOS transistor MP 5; the bias current generating circuit 200 further comprises a third bias current output terminal; the source electrode of the fifth PMOS transistor MP5 is connected to a power supply terminal, the gate electrode is connected to the gate electrode of the first PMOS transistor MP1, the drain electrode is connected to a third bias current output terminal, and the third bias current output terminal is connected to the gate electrode of the first PMOS transistor MP 1. The fifth PMOS transistor MP5 is arranged, the gate current of the first PMOS transistor MP1 is input to the fifth PMOS transistor MP5 through the third Bias current output terminal, and the drain of the fifth MOS transistor is connected to other circuits, and the pre-storage port Bias _ out provides Bias current for other circuits.
In the embodiment, a starting circuit 100, a bias current generating circuit 200 and a power-on reset circuit are arranged, in the power-on process, the bias current generating circuit 200 is started through the starting circuit 100, current is generated through a low-power-consumption bias circuit and the bias current is output to the power-on reset circuit, the power-on reset circuit generates a delay reset signal from 0 to 1 according to the bias circuit and power voltage, the reset starting of the MCU is realized, and the MCU normally works; the whole circuit adopts fewer circuit elements, so that the power consumption is reduced; and before power-on, the MOS tubes of the low-power-consumption bias circuit and the power-on reset circuit do not generate current, so that the power consumption is reduced. In the stop mode and the low power consumption mode, the reset circuit consumes little quiescent current due to few elements and few current branches, so that the power-on reset function is ensured, the power consumption is reduced, the consumption of a battery is reduced, and the cost is reduced.
On the basis of the foregoing embodiments, an embodiment of the present application further provides a bias circuit based low-power-consumption power-on reset method, where the bias circuit based low-power-consumption power-on reset method provided in this embodiment includes:
referring to FIG. 2, when the MCU is started and the power source terminal is powered on slowly, Vdd<VGSMN1+minVDSMP1When the low-power consumption bias circuit does not work, no current is generated, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 are in a cut-off state, and the second node is in a high-resistance state; resetting the output signal in an indeterminate state;
when Vdd is VGSMN1+minVDSMP1When the bias current of the low power consumption bias circuit is input into the third NMOS transistor MN3 and the fourth PMOS transistor MP4, V1 is Vdd-VGSMP3＝minVDSMP1<VTHMN4The current I _ MN3 of the third NMOS transistor MN3 is generated, the fourth NMOS transistor MN4 is turned off, the fourth PMOS transistor MP4 pulls up V2 to Vdd, and the V2 is inverted by the schmitt trigger 310, and the reset output signal is 0;
when Vdd is VGSMP3+VTHMN4When V1 is Vdd-VGSMP3＝VTHMN4The fourth NMOS transistor MN4 is turned on and pulls down V2 to 0, V2 is reversed by the schmitt trigger 310, and the reset output signal generates a rising edge reset signal of 0 to 1 after a delay td, so as to end the reset state, and the MCU starts to operate normally.
It can be understood that, referring to fig. 2, in the MCU start-up operation, when the power supply terminal is powered on slowly, the voltage Vdd of the power supply terminal is a straight line rising at a uniform speed, the current of the third NMOS transistor MN3 is 0, the voltage of the first node por _ Vdd is pulled up by the gate of the third PMOS transistor MP3 but is still lower than the turn-on voltage VTH of the NMOS transistor MN4MN4The second node por _ pre is in a high-impedance state, and the output reset signal por _ in is in an unstable state; when Vdd is VGSMN1+minVDSMP1Meanwhile, the current of the third NMOS transistor MN3 rises from 0 to I _ MN3, the voltage of the first node is reduced in a short moment and then rises at a constant speed along with the rise of the voltage of the power supply terminal, and the voltage of the second node passes through the fourth PMOS transistor MP4, pulling high, outputting a high level 1, and outputting a reset signal of 0 after Schmidt inversion; when Vdd is VGSMP3+VTHMN4Meanwhile, the fourth NMOS transistor MN4 is turned on, the voltage of the second node is pulled down, the voltage of the second node is lowered to 0, a low level is output, and a reset signal from 0 to 1 is output after passing through the schmitt reverse and rising edge delay 320 for a delay time td.
Referring to FIG. 3, when the power source is powered up rapidly, Vdd>VGSMP3+VTHMN4During the startup of the low power consumption bias circuit, the fourth NMOS transistor MN4 turns on the pull-down V2, and the fourth PMOS transistor MP4 turns on the pull-up V2, so that V2 is in an unstable state; receiving the high potential of the low power consumption bias circuit through the gate of the seventh NMOS transistor MN7, and pulling down the level of the output terminal of the schmitt trigger 310 to make the reset signal output to be 0;
after the low-power-consumption circuit is started, the potential of the low-power-consumption bias circuit received by the grid electrode of the seventh NMOS tube MN7 is 0, the seventh NMOS tube MN7 is cut off, the Schmitt trigger 310 outputs a normal signal, the reset output signal generates a rising edge reset signal from 0 to 1 after the delay td time, and the reset state is finished, so that the MCU starts to work normally;
it is understood that, referring to fig. 3, in the MCU start-up operation, when the power source terminal is rapidly powered on, the voltage of the voltage terminal rapidly rises from 0 to Vdd, the current of the third NMOS transistor MN3 rises from 0 to I _ MN3, and the voltage of the first node por _ Vdd rises from 0 to VTHMN4The second node por _ pre is in an indeterminate state, the third node bias _ okb is at a high potential, the gate of the seventh NMOS transistor MN7 is at a high potential, the seventh MOS transistor asserts the output signal of the schmitt trigger 310, and the output reset signal por _ out is 0; after the third node potential drops to 0, the schmitt trigger 310 outputs a normal signal, and outputs a reset signal from 0 to 1 after being delayed for a time td by the rising edge delay 320.
Wherein Vdd is the voltage of the power supply terminal; VGSMN1Is the gate-source voltage of the first NMOS transistor MN 1; minVDSMP1The minimum drain-source voltage of the first PMOS transistor MP 1; VTHMN4Is the threshold voltage of the fourth NMOS transistor MN 4; VGSMP3The gate-source voltage of the third NMOS transistor MN 3; v1 is the voltage of the first node, which is the fourth NThe connection point of the gate of the MOS transistor MN4 and the gate of the third PMOS transistor MP 3; v2 is the voltage of the second node, which is the connection point of the drain of the fourth PMOS transistor MP4, the drain of the fourth NMOS transistor MN4 and the output terminal of the schmitt trigger 310.
On the basis of the above embodiment, the low-power-consumption power-on reset method based on the bias circuit may be further embodied as: the low-power consumption bias circuit does not work and does not generate current; the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fourth PMOS transistor MP4 are in a cut-off state, and include: the low-power consumption bias circuit does not work, and no bias current is generated; the third NMOS transistor MN3 and the fourth PMOS transistor MP4 are in a cut-off state; the gate voltage of the third PMOS transistor MP3 is equal to V1, and the gate voltage of the third PMOS transistor MP3 rises with the voltage of the power supply terminal but is less than the voltage of the power supply terminal and less than the threshold voltage of the fourth NMOS transistor MN4, so that the fourth NMOS transistor MN4 is in an off state.
On the basis of the above embodiment, the low-power-consumption power-on reset method based on the bias circuit may be further embodied as: the bias current is input to the third NMOS transistor MN3 and the fourth PMOS transistor MP4, where V1 is Vdd-VGSMP3＝minVDSMP1<VTHMN4The method comprises the following steps: the low-power consumption current reference circuit starts to work and generates bias current in a first NMOS transistor MN1 and a second NMOS transistor MN2, and the bias current flows into a third NMOS transistor MN3 and a fourth PMOS transistor MP4 to generate initial voltage for the power-on reset circuit; the current of the third NMOS transistor MN3 flows into the drain of the third PMOS transistor MP3, so that the gate voltage V1 of the third PMOS transistor MP3 is Vdd-VGSMP3＝minVDSMP1<VTHMN4。
On the basis of the above embodiment, the low-power-consumption power-on reset method based on the bias circuit may be further embodied as: the receiving of the high potential of the low power consumption bias circuit through the gate of the seventh NMOS transistor MN7 pulls down the level at the output of the schmitt trigger 310 includes: the power supply end is quickly powered on, the resistance of the sixth PMOS tube MP6 is high, the pull-up current is small, the third node is coupled to a high potential by the first capacitor C1, the grid electrode of the seventh NMOS tube MN7 connected with the third node is the high potential, and the fourth NMOS tube MN4 strongly pulls down the level of the output end of the Schmitt trigger 310;
the voltage V3 is the drain voltage of the third node, and the third node is the connection point of the drain of the sixth PMOS transistor MP6, the drain of the fifth NMOS transistor MN5, and the gate of the sixth NMOS transistor MN 6.
On the basis of the above embodiment, the low-power-consumption power-on reset method based on the bias circuit may be further embodied as: the receiving of the potential of the low power consumption bias circuit through the gate of the seventh NMOS transistor MN7 is 0, the seventh NMOS transistor MN7 is turned off, and the schmitt trigger 310 outputs a normal signal, which includes: after the low power consumption bias circuit is started, the sixth NMOS transistor MN6 pulls down the gate voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 until current is generated, the gates of the first NMOS transistor MN1, the second NMOS transistor MN2 and the fifth NMOS transistor MN5 are changed to be high, the fifth NMOS transistor MN5 pulls down V3 to 0, the gate potential of the seventh NMOS transistor MN7 connected with the third node is 0, the seventh NMOS transistor MN7 is cut off and stops the level of the output end of the strong pull-down Schmitt trigger 310, and the Schmitt trigger 310 outputs a normal signal.
In this embodiment, simulation software may be used to implement the test of the low power consumption power-on reset method based on the bias circuit in this embodiment: setting the quick power-on time of a power supply end to be 1us, setting the voltage of the power supply end to be 2V, 3.3V and 3.6V respectively, and setting the temperature to be-40 degrees, 25 degrees and 125 degrees respectively for simulation, wherein simulation results show that a low-level reset signal of more than 3us is generated under different temperature and quick power-on conditions, the quiescent current is less than 1uA, and the requirement of low power consumption is met; setting the slow power-on time of a power supply end to be 10ms, setting the voltage of the power supply end to be 2V, 3.3V and 3.6V respectively, and setting the temperature to be-40 ℃, 25 ℃ and 125 ℃ respectively for simulation, wherein simulation results show that a low-level reset signal of more than 3us is generated under different temperature and fast power-on conditions, the quiescent current is less than 1uA, and the requirement of low power consumption is met;
by arranging the power-on reset circuit with a simple structure, before power-on, an MOS (metal oxide semiconductor) tube in the circuit is cut off, so that power is not consumed; starting the MCU, electrifying, enabling a bias current to flow in the electrifying process, electrifying the power-on reset circuit, enabling the MOS tube to be conducted, and generating a reset signal to enable the MCU to normally work; the whole circuit is simple in structure, few in elements and few in current branches, the current of each branch can be very low, and the elements in the circuit do not work before power on, so that the power consumption of the circuit is reduced, the consumption of a battery is reduced, a third NMOS (N-channel metal oxide semiconductor) tube, a fourth PMOS (P-channel metal oxide semiconductor) tube and a low-power-consumption bias circuit multiplexed by a preceding stage are used for replacing a large resistor with the resistance value of tens of megabytes, which is usually used for low power consumption, the area of a chip can be remarkably reduced, and the cost of the.
The foregoing is considered as illustrative of the preferred embodiments of the invention and the technical principles employed. The present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the claims.

Claims (10)

1. A low-power-consumption power-on reset circuit based on a bias circuit is characterized by comprising: a low power consumption bias circuit and a power-on reset circuit;
the low-power consumption bias circuit comprises a first bias current output end, a second bias current output end and a high-potential output end;
the power-on reset circuit includes: a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, a seventh NMOS tube, a Schmidt trigger and a rising edge delayer;
the source electrode of the third PMOS tube is connected with a power supply end, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube; the source electrode of the fourth PMOS tube is connected with a power supply end, the grid electrode of the fourth PMOS tube is connected with the first bias current output end, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and the input end of the Schmitt trigger; the source electrode of the third NMOS tube is connected with a grounding end, and the grid electrode of the third NMOS tube is connected with the second bias current output end; the source electrode of the fourth NMOS tube is connected with a grounding end; the gate of the seventh NMOS transistor is connected to the high-potential output terminal, the source is connected to the ground terminal, the drain is connected to the output terminal of the schmitt trigger and the input terminal of the rising edge delayer, and the output terminal of the rising edge delayer outputs a delay signal.
2. The bias circuit based low power consumption power-on reset circuit according to claim 1, wherein the low power consumption bias circuit comprises a start-up circuit and a bias current generating circuit; the starting circuit is connected with the bias current generating circuit;
the start-up circuit includes: a sixth PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a first capacitor; the source electrode of the sixth PMOS tube is connected with a power supply end and the first end of the first capacitor, the grid electrode of the sixth PMOS tube is connected with a grounding end, and the drain electrode of the sixth PMOS tube is connected with the second end of the first capacitor, the drain electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the bias current generating circuit, and the source electrode of the fifth NMOS tube is connected with a grounding end; and the drain electrode of the sixth NMOS tube is connected with the low-power consumption bias current to generate current, and the source electrode of the sixth NMOS tube is connected with a grounding end.
3. The bias circuit based low power consumption power-on reset circuit according to claim 2, wherein the bias current generating circuit comprises: the NMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first resistor;
the source electrode of the first PMOS tube is connected with a power supply end, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the first bias current output end and the drain electrode of the sixth MOS tube, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the source electrode of the second PMOS tube is connected with a power supply end, the grid electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the first NMOS tube is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the second NMOS tube, the second bias current output end and the grid electrode of the fifth NMOS tube; and the source electrode of the second NMOS tube is connected with a ground terminal through the first resistor.
4. The bias circuit based low power consumption power-on reset circuit according to claim 1, further comprising a second capacitor and a fifth resistor; the first end of the fifth resistor is connected with the grid electrode of the third PMOS tube, the second end of the fifth resistor is connected with the grid electrode of the fourth NMOS tube and the first end of the second capacitor, and the second end of the second capacitor is connected with the grounding end.
5. The bias circuit based low power consumption power-on reset circuit as claimed in claim 3, further comprising a fifth PMOS transistor; the bias current generating circuit further comprises a third bias current output terminal; the source electrode of the fifth PMOS tube is connected with a power supply end, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube is connected with a third bias current output end, and the third bias current output end is connected with the grid electrode of the first PMOS tube.
6. A low power consumption power-on reset method based on a bias circuit, the low power consumption power-on reset circuit based on the bias circuit of any one of claims 1 to 5, characterized in that the method comprises the following steps:
when the power supply terminal is powered on slowly, Vdd<VGSMN1+minVDSMP1When the low-power consumption bias circuit does not work, no current is generated, the third NMOS tube, the fourth NMOS tube and the fourth PMOS tube are in a cut-off state, and the second node is in a high-resistance state; resetting the output signal in an indeterminate state;
when Vdd is VGSMN1+minVDSMP1When the bias current of the low-power consumption bias circuit is input into the third NMOS tube and the fourth PMOS tube, V1 is Vdd-VGSMP3＝minVDSMP1<VTHMN4When the fourth NMOS transistor is cut off, the fourth PMOS transistor pulls up V2 to Vdd, and after V2 is reversed through a Schmidt trigger, the reset output signal is 0;
when Vdd is VGSMP3+VTHMN4When V1 is Vdd-VGSMP3＝VTHMN4The fourth NMOS tube is conducted and pulled down to be V2 to 0, after the V2 is reversed through a Schmitt trigger, a reset output signal generates a rising edge reset signal from 0 to 1 after the reset output signal passes through the delay td time, and the reset state is finished, so that the MCU starts to work normally;
when the power supply terminal is powered on rapidly, Vdd>VGSMP3+VTHMN4During the starting period of the low-power consumption bias circuit, the fourth NMOS tube is conducted to pull-down V2, and the fourth PMOS tube is conducted to pull-up V2, so that V2 is in an unsteady state; receiving the high potential of the low-power-consumption biasing circuit through the grid electrode of the seventh NMOS tube, and reducing the level of the output end of the Schmitt trigger to enable the output of the reset signal to be 0;
after the low-power-consumption circuit is started, the potential of the low-power-consumption bias circuit received by the grid electrode of the seventh NMOS tube is 0, the seventh NMOS tube is cut off, the Schmitt trigger outputs a normal signal, after the reset output signal is delayed for td time, a rising edge reset signal from 0 to 1 is generated, and the reset state is finished, so that the MCU starts to work normally;
wherein Vdd is the voltage of the power supply terminal; VGSMN1The grid source voltage of the first NMOS tube; minVDSMP1The minimum drain-source voltage of the first PMOS tube; VTHMN4The threshold voltage of the fourth NMOS transistor; VGSMP3The grid source voltage of the third NMOS tube; v1 is the voltage of a first node, and the first node is the connection point of the grid of the fourth NMOS tube and the grid of the third PMOS tube; and V2 is the voltage of a second node, and the second node is the connection point of the drain electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the output end of the Schmitt trigger.
7. The bias circuit based low power consumption power-on reset method according to claim 6, wherein the low power consumption bias circuit does not work and generates no current; the third NMOS transistor, the fourth NMOS transistor and the fourth PMOS transistor are in a cut-off state, and the cut-off state comprises the following steps:
the low-power consumption bias circuit does not work, and no bias current is generated; the third NMOS tube and the fourth PMOS tube are in a cut-off state; the grid voltage of the third PMOS tube is equal to V1, and the grid voltage of the third PMOS tube rises with the voltage of the power supply end but is smaller than the voltage of the power supply end and smaller than the threshold voltage of the fourth NMOS tube, so that the fourth NMOS tube is in a cut-off state.
8. The bias circuit based on claim 6 for low power consumptionThe electric reset method is characterized in that the bias current is input into a third NMOS tube and a fourth PMOS tube, and V1 is equal to Vdd-VGSMP3＝minVDSMP1<VTHMN4The method comprises the following steps:
the low-power-consumption current reference circuit starts to work and generates bias current on the first NMOS tube and the second NMOS tube, and the bias current flows into the third NMOS tube and the fourth PMOS tube to generate initial voltage for the power-on reset circuit; the current of the third NMOS transistor flows into the drain of the third PMOS transistor, so that the gate voltage of the third PMOS transistor, i.e., V1, becomes Vdd-VGSMP3＝minVDSMP1<VTHMN4。
9. The bias circuit-based low-power-consumption power-on reset method according to claim 6, wherein the step of receiving the high potential of the low-power-consumption bias circuit through the gate of the seventh NMOS transistor and pulling down the level of the output terminal of the schmitt trigger comprises the steps of:
the power supply end is quickly electrified, the resistance of the sixth PMOS tube is high, the pull-up current is small, the third node is coupled to a high potential by the first capacitor, the grid electrode of a seventh NMOS tube connected with the third node is the high potential, and the fourth NMOS tube strongly pulls down the level of the output end of the Schmitt trigger;
and V3 is the drain voltage of a third node, and the third node is the connection point of the drain of the sixth PMOS tube, the drain of the fifth NMOS tube and the gate of the sixth NMOS tube.
10. The bias circuit-based low-power-consumption power-on reset method according to claim 9, wherein the receiving of the potential of the low-power-consumption bias circuit through the gate of the seventh NMOS transistor is 0, the seventh NMOS transistor is turned off, and the schmitt trigger outputs a normal signal, comprising:
after the low-power-consumption bias circuit is started, the sixth NMOS tube pulls down the grid voltages of the first PMOS tube and the second PMOS tube until current is generated, the grids of the first NMOS tube, the second NMOS tube and the fifth NMOS tube are changed to be high, the fifth NMOS tube pulls down V3 to 0, the grid potential of a seventh NMOS tube connected with the third node is 0, the seventh NMOS tube is cut off and stops the level of the output end of the strong pull-down Schmitt trigger, and the Schmitt trigger outputs a normal signal.
CN202011197700.6A 2020-10-30 2020-10-30 Low-power-consumption power-on reset circuit and method based on bias circuit Active CN112290923B (en)

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