CN213185874U - Soft start circuit, soft start low dropout regulator - Google Patents
Soft start circuit, soft start low dropout regulator Download PDFInfo
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- CN213185874U CN213185874U CN202021996580.1U CN202021996580U CN213185874U CN 213185874 U CN213185874 U CN 213185874U CN 202021996580 U CN202021996580 U CN 202021996580U CN 213185874 U CN213185874 U CN 213185874U
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Abstract
The application provides a soft start circuit and soft start low dropout regulator, wherein the soft start circuit includes: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a resistive device, a third NMOS tube, a second PMOS tube, a third PMOS tube and a capacitive device. The drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube; the drain electrode of the second NMOS tube is connected with the resistive device, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the second PMOS tube is connected with the grid electrode of the second PMOS tube; the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube, and the grid electrode of the third NMOS tube is connected with the resistive device; the capacitive device is connected in parallel to two ends of the drain electrode and the source electrode of the third NMOS tube; the grid electrode of the third PMOS tube is connected with the grid electrode of the second PMOS tube. Compared with the conventional method, the circuit has lower power consumption and smaller area, and is suitable for high-voltage input under the low-voltage device process.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a soft start circuit and a soft start low dropout regulator.
Background
In the field of power supply design and application, a soft start circuit is an important method and a necessary means for solving the problems of overshoot and current surge generated in the output of a power supply in the power-on stage. With the development of semiconductor process technology, the size of devices is continuously reduced, and the corresponding adaptive working voltage of the devices is also lower and lower, so that in circuit design, some original circuit architectures in high-voltage application are not applicable any more when implemented under the low-voltage device process.
Fig. 1 shows a typical soft start circuit implemented by a conventional device of voltage adaptation type. The circuit is generally composed of a comparator Comp, a control switch S0, a control switch S1, a constant current path, and a capacitive device Cs. In the initial stage of power-up, the control switch S1 is turned on, Vsoft is connected to the inverting terminal of the error amplifier EA, and Vsoft is obtained by charging the capacitive device Cs from the constant current path, and at this time, Vsoft rises slowly from 0. In the whole process, the output voltage of an LDO (low dropout regulator) is guided to be gradually increased through a negative feedback loop until the Vsoft voltage is larger than the vcom voltage, the control switch S1 is turned off, the control switch S0 is turned on, and the soft start is completed, so that the phenomenon that the output of the LDO is overshot or surged due to the fact that a power tube PM is completely opened in the initial power-on stage of the LDO is avoided.
The conventional implementation mode is complex in circuit, power consumption and area increase are needed for using the comparator, meanwhile, the withstand voltage of the used device needs to be adapted to the power supply voltage, and under the low-voltage device process, the Vsoft voltage finally reaches the power supply voltage, so that the input ends of the error amplifier and the comparator which are implemented by adopting the low-voltage device have the risk of overvoltage, and therefore the circuit architecture cannot be applied.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a soft start circuit, and its circuit structure is more simple high-efficient than conventional method, and the consumption is lower, and the area is littleer to be applicable to the high-voltage input under the low pressure device technology, the suitability is wider.
The application provides a soft start circuit, which is applied to a low dropout linear regulator; the soft start circuit includes: the source electrode of the first PMOS tube is used for being connected with a power supply, and the grid electrode of the first PMOS tube is used for being connected with the low dropout linear regulator; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is grounded; the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube; the first end of the resistive device is used for being connected with a power supply; the drain electrode of the second NMOS tube is connected with the second end of the resistive device, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded; the source electrode of the second PMOS tube is used for being connected with a power supply, and the drain electrode of the second PMOS tube is connected with the grid electrode of the second PMOS tube; a drain electrode of the third NMOS tube is connected with a drain electrode of the second PMOS tube, a gate electrode of the third NMOS tube is connected with the second end of the resistive device, and a source electrode of the third NMOS tube is grounded;
the capacitive device is connected in parallel to two ends of the drain electrode and the source electrode of the third NMOS tube;
and the source electrode of the third PMOS tube is used for being connected with a power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is used for being connected with the low dropout linear regulator.
In an embodiment, in an initial power-up stage, a gate voltage of the second NMOS transistor is a low voltage, and the second NMOS transistor is in an off state.
In an embodiment, when the second NMOS transistor is in an off state, the gate voltage of the third NMOS transistor is a high voltage, and the third NMOS transistor is turned on.
In an embodiment, when the third NMOS transistor is turned on, the second PMOS transistor is turned on, and a gate voltage of the second PMOS transistor is lower than a power supply voltage.
In an embodiment, the turn-on threshold voltage of the third PMOS transistor is lower than the turn-on threshold voltage of the third PMOS transistor; and when the second PMOS tube is conducted, the third PMOS tube is conducted slightly.
In an embodiment, after the current of the first PMOS transistor increases, the second NMOS transistor is turned on.
In an embodiment, when the second NMOS transistor is turned on, the third NMOS transistor is turned off, and the capacitive device is charged.
In an embodiment, after the capacitive device is charged, the gate voltage of the third PMOS transistor rises, and the third PMOS transistor is turned off.
The application also provides a soft start low dropout regulator, the soft start low dropout regulator includes:
the soft start circuit provided by the embodiment of the application;
a low dropout linear regulator comprising: the error amplifier, a fourth PMOS tube, a first resistor, a second resistor and a first capacitor; the source electrode of the fourth PMOS tube is used for being connected with a power supply, the grid electrode of the fourth PMOS tube is connected with the output end of the error amplifier, the drain electrode of the fourth PMOS tube is connected with the first end of the first resistor, the first end of the second resistor is connected with the first end of the first resistor, the second end of the second resistor is grounded, the second end of the first resistor is connected with the non-inverting input end of the error amplifier, the inverting input end of the error amplifier is used for being connected with a reference source, the first end of the first capacitor is connected with the first end of the first resistor, and the second end of the first capacitor is connected with the second end of the second resistor;
the drain electrode of a third PMOS tube of the soft start circuit is connected with the grid electrode of the fourth PMOS tube, and the grid electrode of a first PMOS tube of the soft start circuit is connected with the grid electrode of the fourth PMOS tube.
In an embodiment, in an initial power-up stage, the third PMOS transistor is turned on slightly, and the gate voltage of the fourth PMOS transistor is pulled up.
According to the soft start circuit provided by the embodiment of the application, the circuit structure is adopted, so that a soft start mode of the circuit is realized, and compared with a conventional method, the circuit structure is simpler and more efficient, the power consumption is lower, and the area is smaller. In addition, the soft start circuit is also suitable for high-voltage input under the low-voltage device process, and has wider applicability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described below.
FIG. 1 is a circuit schematic of a soft start circuit for a typical high voltage device implementation;
fig. 2 is a circuit diagram of a soft-start low dropout linear regulator according to an embodiment of the present application.
Description of the main element symbols: 210-a soft start circuit; 211-first PMOS transistor; 212-first NMOS transistor; 213-second NMOS tube; 214-a resistive device; 215-third NMOS transistor; 216-second PMOS tube; 217-third PMOS tube; 218-a capacitive device; 220-low dropout linear regulator; 221-an error amplifier; 222-a fourth PMOS tube; 223-a first resistance; 224-a second resistance; 225-first capacitance.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Fig. 2 is a circuit diagram of a soft-start low dropout linear regulator according to an embodiment of the present application. As shown in fig. 2, the circuit includes: a soft start circuit 210 and a low dropout linear regulator 220.
The soft start circuit 210 includes: a first PMOS transistor 211, a first NMOS transistor 212, a second NMOS transistor 213, a resistive device 214, a third NMOS transistor 215, a second PMOS transistor 216, a third PMOS transistor 217, and a capacitive device 218.
The source of the first PMOS transistor 211 is used for connecting a power supply; the drain of the first NMOS tube 212 is connected to the drain of the first PMOS tube 211, the source of the first NMOS tube 212 is grounded, and the drain of the first NMOS tube 212 is connected to the gate thereof; a first terminal of the resistive device 214 is for connection to a power supply; the drain of the second NMOS tube 213 is connected to the second end of the resistive device 214, the gate of the second NMOS tube 213 is connected to the gate of the first NMOS tube 212, and the source of the second NMOS tube 213 is grounded; the source of the second PMOS transistor 216 is used for connecting a power supply, and the drain of the second PMOS transistor 216 is connected to the gate of the second PMOS transistor 216; the drain of the third NMOS transistor 215 is connected to the drain of the second PMOS transistor 216, the gate of the third NMOS transistor 215 is connected to the second end of the resistive device 214, and the source of the third NMOS transistor 215 is grounded; the capacitive device 218 is connected in parallel to the drain and source terminals of the third NMOS transistor 215; the source of the third PMOS transistor 217 is used for connecting a power supply, and the gate of the third PMOS transistor 217 is connected to the gate of the second PMOS transistor 216.
In one embodiment, the resistive device 214 may be a resistor, a bias circuit, or a MOS transistor. The capacitive device 218 may be a capacitor or a MOS transistor.
The low dropout linear regulator 220 includes: the error amplifier 221, the fourth PMOS transistor 222, the first resistor 223, the second resistor 224, and the first capacitor 225.
The source of the fourth PMOS transistor 222 is used for connecting a power supply, the gate of the fourth PMOS transistor 222 is connected to the output terminal of the error amplifier 221, the drain of the fourth PMOS transistor 222 is connected to the first terminal of the first resistor 223, the first terminal of the second resistor 224 is connected to the first terminal of the first resistor 223, the second terminal of the second resistor 224 is grounded, the second terminal of the first resistor 223 is connected to the non-inverting input terminal of the error amplifier 221, the inverting input terminal of the error amplifier 221 is used for connecting a reference source, the first terminal of the first capacitor 225 is connected to the first terminal of the first resistor 223, and the second terminal of the first capacitor 225 is connected to the second terminal of the second resistor 224. The low dropout regulator 220 stabilizes the output voltage by applying a reference voltage to the inverting input terminal of the error amplifier 221 and applying a feedback voltage to the non-inverting input terminal of the error amplifier 221, and controlling the voltage drop of the fourth PMOS transistor 222 after the difference between the two is amplified by the error amplifier 221.
In addition, the third PMOS transistor 217 of the soft start circuit 210 is connected to the gate of the fourth PMOS transistor 222. The first PMOS transistor 211 in the soft start circuit 210 is connected to the gate of the fourth PMOS transistor 222.
When the power supply is in the initial stage of power-on, the branch of the first PMOS transistor 211 and the first NMOS transistor 212 has no current, and the voltage of the node VBN is 0, which makes the second NMOS transistor 213 in an off state. At this time, the gate (node VNS) of the third NMOS transistor 215 is connected to the power supply through the resistive device 214, and the voltage of the node VNS is high, so that the third NMOS transistor 215 is turned on. Since the gate and the drain of the second PMOS transistor 216 are shorted, and have the forward conduction characteristic of a diode, when the third NMOS transistor 215 is turned on, the second PMOS transistor 216 is also turned on, and the gate voltage and the drain voltage Vsoft of the second PMOS transistor 216 are lower than the power voltage. The conduction voltage threshold of the third PMOS transistor 217 is lower than that of the second PMOS transistor 216, so that when the second PMOS transistor 216 is turned on, the third PMOS transistor 217 is turned on slightly. The micro-conduction means that the third PMOS transistor 217 is not fully turned on, but is not fully turned off, i.e. a small amount of current flows through the third PMOS transistor 217. At this time, the drain voltage of the third PMOS transistor 217 is lower than the power voltage. The third PMOS transistor 217 pulls up the gate of the fourth PMOS transistor 222 weakly, i.e., pulls up the gate voltage of the fourth PMOS transistor 222, thereby avoiding overshoot of the output voltage and current surge caused by complete conduction of the fourth PMOS transistor 222 in the power-up stage.
Thereafter, the output current of the fourth PMOS transistor 222 increases due to the negative feedback effect of the low dropout linear regulator 220, and the current of the first PMOS transistor 211 also increases due to the connection between the gate of the first PMOS transistor 211 and the gate of the fourth PMOS transistor 222. At this time, the first NMOS transistor 212 is turned on, and the voltage of the node VBN is increased, so that the second NMOS transistor 213 is turned on. The voltage at the node VNS is 0, turning off the second NMOS transistor 213. At this time, the branch of the second PMOS transistor 216 charges the capacitive device 218, so that the Vsoft voltage is increased, the third PMOS transistor 217 is turned off, and the soft start is ended.
The soft-start circuit provided in the above embodiment of the present application implements a soft-start method of the low dropout regulator 220 by using the circuit structure described in the above embodiment and shown in fig. 2, and the circuit structure is simpler and more efficient, has lower power consumption, and has a smaller area than a conventional method. In addition, the soft start circuit 210 is also suitable for high-voltage input under a low-voltage device process, and has wider applicability.
Claims (4)
1. The soft start circuit is characterized in that the soft start circuit is applied to a soft start low dropout linear regulator; the soft start circuit includes:
the source electrode of the first PMOS tube is used for being connected with a power supply, and the grid electrode of the first PMOS tube is used for being connected with the low dropout linear regulator;
the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the first NMOS tube is grounded; the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube;
the first end of the resistive device is used for being connected with a power supply;
the drain electrode of the second NMOS tube is connected with the second end of the resistive device, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded;
the source electrode of the second PMOS tube is used for being connected with a power supply, and the drain electrode of the second PMOS tube is connected with the grid electrode of the second PMOS tube;
a drain electrode of the third NMOS tube is connected with a drain electrode of the second PMOS tube, a gate electrode of the third NMOS tube is connected with the second end of the resistive device, and a source electrode of the third NMOS tube is grounded;
the capacitive device is connected in parallel to two ends of the drain electrode and the source electrode of the third NMOS tube;
and the source electrode of the third PMOS tube is used for being connected with a power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is used for being connected with the low dropout linear regulator.
2. The soft-start circuit of claim 1, wherein the resistive device comprises: a resistor, a bias circuit or a MOS tube.
3. The soft-start circuit of claim 1, wherein the capacitive device comprises: a capacitor or a MOS tube.
4. A soft-start low dropout regulator, comprising:
a soft start circuit of any one of claims 1-3;
a low dropout linear regulator comprising: the error amplifier, a fourth PMOS tube, a first resistor, a second resistor and a first capacitor; the source electrode of the fourth PMOS tube is used for being connected with a power supply, the grid electrode of the fourth PMOS tube is connected with the output end of the error amplifier, the drain electrode of the fourth PMOS tube is connected with the first end of the first resistor, the first end of the second resistor is connected with the first end of the first resistor, the second end of the second resistor is grounded, the second end of the first resistor is connected with the non-inverting input end of the error amplifier, the inverting input end of the error amplifier is used for being connected with a reference source, the first end of the first capacitor is connected with the first end of the first resistor, and the second end of the first capacitor is connected with the second end of the second resistor;
the drain electrode of a third PMOS tube of the soft start circuit is connected with the grid electrode of the fourth PMOS tube, and the grid electrode of a first PMOS tube of the soft start circuit is connected with the grid electrode of the fourth PMOS tube.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021996580.1U CN213185874U (en) | 2020-09-11 | 2020-09-11 | Soft start circuit, soft start low dropout regulator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021996580.1U CN213185874U (en) | 2020-09-11 | 2020-09-11 | Soft start circuit, soft start low dropout regulator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113568466A (en) * | 2021-09-26 | 2021-10-29 | 芯灵通(天津)科技有限公司 | High-voltage-resistant low dropout regulator (LDO) and power-on circuit thereof |
| CN115202424A (en) * | 2022-09-15 | 2022-10-18 | 宁波奥拉半导体股份有限公司 | Low dropout regulator and electronic device |
| CN116430938A (en) * | 2023-06-12 | 2023-07-14 | 上海海栎创科技股份有限公司 | Soft start control module, system and method |
-
2020
- 2020-09-11 CN CN202021996580.1U patent/CN213185874U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113568466A (en) * | 2021-09-26 | 2021-10-29 | 芯灵通(天津)科技有限公司 | High-voltage-resistant low dropout regulator (LDO) and power-on circuit thereof |
| CN115202424A (en) * | 2022-09-15 | 2022-10-18 | 宁波奥拉半导体股份有限公司 | Low dropout regulator and electronic device |
| CN115202424B (en) * | 2022-09-15 | 2022-11-22 | 宁波奥拉半导体股份有限公司 | Low dropout regulator and electronic device |
| CN116430938A (en) * | 2023-06-12 | 2023-07-14 | 上海海栎创科技股份有限公司 | Soft start control module, system and method |
| CN116430938B (en) * | 2023-06-12 | 2023-09-12 | 上海海栎创科技股份有限公司 | Soft start control module, system and method |
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