CN203027363U - Starting-up reset circuit and television - Google Patents
Starting-up reset circuit and television Download PDFInfo
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- CN203027363U CN203027363U CN 201320006744 CN201320006744U CN203027363U CN 203027363 U CN203027363 U CN 203027363U CN 201320006744 CN201320006744 CN 201320006744 CN 201320006744 U CN201320006744 U CN 201320006744U CN 203027363 U CN203027363 U CN 203027363U
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- reset circuit
- electric capacity
- master chip
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Abstract
The utility model is suitable for the field of electronics, and provides a starting-up reset circuit and a television. The starting-up reset circuit comprises a main chip, a memory chip, a control circuit connected with a first output end of the main chip, a delay circuit connected with a second output end of the main chip, and a switching circuit, wherein an input end of the switching circuit is connected with an output end of the delay circuit; an output end of the switching circuit is connected with a second input end of the control circuit; and an output end of the control circuit is connected with a power supply end of the memory chip. According to the starting-up reset circuit, the main chip controls the change of output levels of two I/O (Input/Output) ports internally provided with pull-up resistors, so that the memory chip is restarted after power failure before the main chip is reset, the problem of communication abnormity between the main chip and the memory chip is solved, and the normal starting of a system is ensured.
Description
Technical field
The utility model belongs to electronic applications, relates in particular to a kind of start reset circuit and television set.
Background technology
Development along with science and technology, it is intelligent that TV moves towards comprehensively, intelligent TV set all can be used storage chip (generally having the functions such as enhancement region, anti-deletion, anti-copy, hidden area) at present, the working power of system is directly taken from its power supply, in the process of television set normal boot-strap or standby start, storage chip all may occur can not normal communication with master chip situation, cause system to start, this can cause great injury to the stability of product and consumer's experience property, therefore prior art needs to improve.
The utility model content
The purpose of this utility model is to provide a kind of start reset circuit, is intended to solve the problem that existing television system is opened rear master chip and storage chip communication abnormality.In order to solve the problems of the technologies described above, the utility model adopts following scheme to be achieved:
A kind of start reset circuit, comprise master chip, storage chip, described start reset circuit also comprises the control circuit that is connected with the first output of described master chip, the delay circuit that is connected with the second output of described master chip, and the switching circuit that input is connected with described delay circuit output, output is connected with the second input of described control circuit, the output of described control circuit is connected with the feeder ear of described storage chip.
Further, the first output of described master chip and the second output are the I/O mouth that described master chip inside has pull-up resistor.
Further, described delay circuit comprises the first resistance and the first electric capacity; One end of wherein said the first resistance is connected with the second output of described master chip, the other end is connected with the first end of described the first electric capacity, the second end ground connection of described the first electric capacity.
Further, described switching circuit comprises the second resistance and triode; Wherein the first end of the second resistance is connected with the first end of described the first electric capacity, the second end is connected with the base stage of described triode, and the grounded emitter of described triode, collector electrode are the output of described switching circuit.
Further, described control circuit comprises metal-oxide-semiconductor, the 3rd resistance, the 4th resistance, the 5th resistance, the second electric capacity, the 3rd electric capacity and system works power supply; Wherein the first end of the 3rd resistance is connected with the first output of described master chip, the second end is connected with the grid of described metal-oxide-semiconductor by described the 5th resistance, and the second end of described the 3rd resistance also is connected with the first end of described the 4th resistance, the collector electrode of described triode respectively; Described system works power supply is connected with the first end of described the second electric capacity, the second end of the 4th resistance and the source electrode of metal-oxide-semiconductor respectively, the second end ground connection of described the second electric capacity, and the drain electrode of described metal-oxide-semiconductor is the output of described control circuit; The first end of described the 3rd electric capacity is connected with the drain electrode of described metal-oxide-semiconductor, the second end ground connection.
Further, described triode is NPN type triode.
Further, described metal-oxide-semiconductor is the P channel MOS tube.
Another purpose of the present utility model also provides the television set with above-mentioned start reset circuit.
The start reset circuit that the utility model adopts, control by adopting master chip the variation that its inside has two I/O mouth output levels of pull-up resistor, make master chip guarantee that storage chip completed power-down rebooting before resetting completing, solve the communication abnormality problem between master chip and storage chip, thereby the system that guaranteed starts normally; This start reset circuit reliability is high, simple in structure, cost is extremely low, has larger using value and market prospects.
Description of drawings
Fig. 1 is the theory diagram of the start reset circuit that provides of the utility model embodiment;
Fig. 2 is the start reset circuit figure that the utility model embodiment provides;
Fig. 3 is each key node voltage oscillogram of start reset circuit that the utility model embodiment provides.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
Fig. 1 shows the theory diagram of the start reset circuit that the utility model embodiment provides, and details are as follows:
This reset circuit of starting shooting, comprise master chip 10, storage chip 30, described start reset circuit also comprises the control circuit that is connected with the first output of described master chip, the delay circuit that is connected with the second output of described master chip, and the switching circuit 23 that input is connected with the output of described delay circuit 22, output is connected with the second input of described control circuit 21, the output of described control circuit 23 is connected with the feeder ear of described storage chip 30.
Fig. 2 shows the start reset circuit figure that the utility model embodiment provides, and details are as follows:
As shown in Figure 2, in the utility model embodiment, the first output GPIO1 of described master chip 10 and the second output GPIO2 are the I/O mouth that described master chip 10 inside have pull-up resistor, when normal operation, and the first output GPIO1 and the second equal output low level of output GPIO2; When powering on communication abnormality, the first output GPIO1 and the second output GPIO2 all export high level.
In the utility model embodiment, described system works power supply V
INBe the 3.3V power supply that system's normal operation provides, described start reset circuit operation principle is as follows:
When system powers on normal operation, described system works power supply V
INBe high level, the first output GPIO1 and the second output GPIO2 of described master chip 10 are low level, triode Q1 cut-off; Due to the resistance of described the 4th resistance R 4 resistance much larger than the 3rd resistance R 3, after the 4th resistance R 4 and the 3rd resistance R 3 dividing potential drops, the source electrode of metal-oxide-semiconductor Q2 and the potential difference of grid enough make its conducting, the output of described control circuit 23 is exported high level, for storage chip 30 provides operating voltage.
Fig. 3 shows each key node voltage oscillogram of start reset circuit that the utility model embodiment provides, when system powers on when communication abnormality occurring, the first output GPIO1 and the second output GPIO2 of described master chip 10 are high level, existence due to delay circuit 21, VCC2 charges by 1 pair of the first capacitor C 1 of the first resistance R, so the base voltage of triode Q1 can not rise to the required voltage of its conducting at once, but a time-delay T1 is arranged; Wherein said time-delay T1 can realize by the parameter of regulating the first resistance R 1 and the first capacitor C 1.
In time period T1, described triode Q1 cut-off, and the first output GPIO1 of described master chip 10 remains high level simultaneously, and the source electrode of metal-oxide-semiconductor Q2 and grid do not have potential difference, not conducting of described metal-oxide-semiconductor Q2 this moment, and the power supply of storage chip 30 disconnects; Along with the carrying out to the first capacitor C 1 charging, the base voltage of described triode Q1 constantly raises, after elapsed time T1, base voltage is greater than conducting voltage, triode Q1 conducting, the grid voltage of metal-oxide-semiconductor Q2 is dragged down, thereby the source electrode of metal-oxide-semiconductor Q2 and grid have just had potential difference, metal-oxide-semiconductor Q2 conducting this moment, the output output high level of described control circuit 23, storage chip 30 restores electricity, and completes to reset.
As shown in Figure 3, then after elapsed time T2, master chip 10 is completed and is resetted and control the first output GPIO1, the second output GPIO2 output low level, due to the second output GPIO2 output low level, and described triode Q1 cut-off; The first output GPIO1 is also low level simultaneously, system works power supply V
INDividing potential drop through the 4th resistance R 4 and the 3rd resistance R 3, there are potential difference in source electrode and the grid of metal-oxide-semiconductor Q2, and metal-oxide-semiconductor Q2 will keep conducting state always, thereby have guaranteed that also storage chip 30 power supplies are normal, thereby guarantee normal communication between master chip 10 and storage chip 30, system's normal operation.
The start reset circuit that the utility model adopts, control by adopting master chip the variation that its inside has two I/O mouth output levels of pull-up resistor, make master chip guarantee that storage chip completed power-down rebooting before resetting completing, solve the communication abnormality problem between master chip and storage chip, thereby the system that guaranteed starts normally; This start reset circuit reliability is high, simple in structure, cost is extremely low, has larger using value and market prospects.
The above is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (8)
- One kind the start reset circuit, comprise master chip, storage chip, it is characterized in that, described start reset circuit also comprises the control circuit that is connected with the first output of described master chip, the delay circuit that is connected with the second output of described master chip, and the switching circuit that input is connected with described delay circuit output, output is connected with the second input of described control circuit, the output of described control circuit is connected with the feeder ear of described storage chip.
- 2. start reset circuit according to claim 1, is characterized in that, the first output of described master chip and the second output are the I/O mouth that described master chip inside has pull-up resistor.
- 3. start reset circuit according to claim 1, is characterized in that, described delay circuit comprises the first resistance and the first electric capacity; One end of wherein said the first resistance is connected with the second output of described master chip, the other end is connected with the first end of described the first electric capacity, the second end ground connection of described the first electric capacity.
- 4. start reset circuit according to claim 1, is characterized in that, described switching circuit comprises the second resistance and triode; Wherein the first end of the second resistance is connected with the first end of described the first electric capacity, the second end is connected with the base stage of described triode, and the grounded emitter of described triode, collector electrode are the output of described switching circuit.
- 5. start reset circuit according to claim 1, is characterized in that, described control circuit comprises metal-oxide-semiconductor, the 3rd resistance, the 4th resistance, the 5th resistance, the second electric capacity, the 3rd electric capacity and system works power supply; Wherein the first end of the 3rd resistance is connected with the first output of described master chip, the second end is connected with the grid of described metal-oxide-semiconductor by described the 5th resistance, and the second end of described the 3rd resistance also is connected with the first end of described the 4th resistance, the collector electrode of described triode respectively; Described system works power supply is connected with the first end of described the second electric capacity, the second end of the 4th resistance and the source electrode of metal-oxide-semiconductor respectively, the second end ground connection of described the second electric capacity, and the drain electrode of described metal-oxide-semiconductor is the output of described control circuit; The first end of described the 3rd electric capacity is connected with the drain electrode of described metal-oxide-semiconductor, the second end ground connection.
- 6. start reset circuit according to claim 4, is characterized in that, described triode is NPN type triode.
- 7. start reset circuit according to claim 5, is characterized in that, described metal-oxide-semiconductor is the P channel MOS tube.
- 8. a television set, is characterized in that, described television set comprises the described start reset circuit of any one in claim 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320006744 CN203027363U (en) | 2013-01-07 | 2013-01-07 | Starting-up reset circuit and television |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320006744 CN203027363U (en) | 2013-01-07 | 2013-01-07 | Starting-up reset circuit and television |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203027363U true CN203027363U (en) | 2013-06-26 |
Family
ID=48651304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320006744 Expired - Lifetime CN203027363U (en) | 2013-01-07 | 2013-01-07 | Starting-up reset circuit and television |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203027363U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103686358A (en) * | 2013-11-14 | 2014-03-26 | 乐视致新电子科技（天津）有限公司 | MCU reset control device, television system and method |
| CN110366040A (en) * | 2019-07-26 | 2019-10-22 | Tcl王牌电器(惠州)有限公司 | TV factory reset method, apparatus, computer readable storage medium and system |
-
2013
- 2013-01-07 CN CN 201320006744 patent/CN203027363U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103686358A (en) * | 2013-11-14 | 2014-03-26 | 乐视致新电子科技（天津）有限公司 | MCU reset control device, television system and method |
| CN110366040A (en) * | 2019-07-26 | 2019-10-22 | Tcl王牌电器(惠州)有限公司 | TV factory reset method, apparatus, computer readable storage medium and system |
| CN110366040B (en) * | 2019-07-26 | 2023-01-20 | Tcl王牌电器(惠州)有限公司 | Television delivery resetting method and device, computer readable storage medium and system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130626 |
|
| CX01 | Expiry of patent term |