CN209946887U

CN209946887U - Special IO level switching circuit of programmer and PCB

Info

Publication number: CN209946887U
Application number: CN201920617323.3U
Authority: CN
Inventors: 王葆春
Original assignee: Individual
Current assignee: Individual
Priority date: 2019-04-30
Filing date: 2019-04-30
Publication date: 2020-01-14
Anticipated expiration: 2029-04-30

Abstract

The utility model discloses a special IO level shift circuit of programmer, including FPGA chip and ZIF connector, there are a plurality of IO pins in the FPGA chip, and is a plurality of the IO pin all through level shift circuit with the pin one-to-one of ZIF connector is connected. The utility model discloses a PCB circuit board for level conversion circuit provides the wiring for the components and parts among the level conversion circuit, the PCB board front side is equipped with the FPGA chip and places district and ZIF connector locking seat, the FPGA chip is placed the district and is placed the FPGA chip, be provided with the ZIF connector on the tight locking seat of ZIF connector, ZIF connector pin interval is 2.54 mm. The utility model discloses effectively optimized circuit structure and PCB plate structure, reduced the intensive degree of PCB board positive surface element device for PCB face area is littleer, and wiring distance is shorter, does benefit to the stability of signal, reduces the loss.

Description

Special IO level switching circuit of programmer and PCB

Technical Field

The utility model relates to a level shift circuit and PCB circuit board specifically are and are used for a special IO level shift circuit of programmer and PCB board.

Background

When the universal programmer burns various ICs, the VCC voltage needs to be from 1.2V to 6.5V power supply voltage, and the VPP voltage needs to be from 5V to the highest programming power supply voltage of 25V according to different IC chips. For any I/O pin of the general-purpose programmer connected to the locking seat of the programmer, the high voltage of up to 25V can be borne, and high-speed communication is required at the same time, generally, the pin is a general-purpose programmer with full drive and has 48 to 144 paths of identical I/O drive circuits, and whether the design of the I/O drive circuits reasonably and greatly determines the cost and the performance of the programmer.

Similarly, because the size of the chip locking seat is large, the wiring is dense, each pin needs to be provided with VPP, VCC, GND and I/O signals, the unreasonable connection can greatly increase the wiring length of a signal line on a PCB circuit board, the high-speed communication is greatly influenced, the reasonable optimized circuit structure reduces the area of components, the area of the PCB is reduced on the premise of ensuring the stability of the circuit, the lower cost is realized, and the lower power consumption is the key for the success of electronic products.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a special IO level shift circuit of programmer and PCB board to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

a special IO level conversion circuit for a programmer comprises an FPGA chip and a ZIF connector, wherein the FPGA chip is provided with a plurality of I/O pins, the I/O pins are connected with pins of the ZIF connector in a one-to-one correspondence mode through level conversion circuits, the level conversion circuit comprises a diode D1, a resistor R1, a MOSFET tube Q1, a triode Q10, a triode Q11, a triode Q12 and a diode D10, one end of the resistor R1 is connected with the corresponding I/O pins of the FPGA chip, the other end of the resistor is connected with the anode of the diode D1, the anode of the diode is connected with the source of the MOSFET tube Q1, the drain of the MOSFET tube Q1 is connected with the collector of the triode Q10, the collector of the triode Q10 is connected with the cathode of the diode D10, the cathode of the diode D10 is respectively connected with the collector of the triode Q12 and the corresponding pins of the ZIF connector, the anode of the diode D10 is connected to the collector of the transistor Q11.

Preferably, the cathode of the diode D1 is connected with 3.3V, the base of the triode Q10 is connected with VPP1, the emitter is connected with VPP, the base of the triode Q11 is connected with VCC1, the emitter is connected with VCC, and the base of the triode Q12 is connected with GND1, and the emitter is connected with GND.

Preferably, VPP1, VCC1, and GND1 are control signal terminals, VPP and VCC are voltage power terminals, and GND is a ground terminal.

Preferably, the gates of the MOSFET transistors Q1 of the multiple level shift circuits are connected to the voltage of 5V through an RC filter circuit, the RC filter circuit includes a resistor Rg and a capacitor Cg connected in series, the series connection point of the resistor Rg is connected to the gate of the MOSFET transistor Q1, the resistor Rg is connected to the voltage of 5V, and the capacitor Cg is grounded.

Preferably, the MOSFET Q1 is an N-type MOSFET.

Preferably, the MOSFET Q1 is an SOT323 packaged device, the diode D1 is a common cathode diode BAT54CW, the diode is also an SOT323 package, and the resistor R1 is a 0603 package resistor.

A PCB circuit board for foretell level shift circuit provides the wiring for the components and parts among the level shift circuit, PCB circuit board openly is equipped with the FPGA chip and places district and ZIF connector locking seat, the FPGA chip is placed the district and is placed the FPGA chip, be provided with the ZIF connector on the ZIF connector locking seat, ZIF connector pin interval is 2.54 mm.

Preferably, the width of each of the MOSFET tube Q1 and the diode D1 is 2mm, and the MOSFET tube Q1 and the diode D1 are respectively arranged in the gap between the corresponding pins of the ZIF connector.

Preferably, a triode Q10, triodes Q11 and D10 and a triode Q12 are respectively arranged on different surfaces of the PCB, and the triode Q10, the triodes Q11 and D10 and the triode Q12 are all connected through corresponding pins of a ZIF connector.

Compared with the prior art, the beneficial effects of the utility model are that:

1. the utility model discloses a structure is simple relatively, can realize on the PCB circuit board the shortest distance wiring, very big reduction PCB board area, effective reduce cost, the consumption is also lower simultaneously, and IO drive itself is close 0 consumption, and is energy-conserving stable again.

2. The utility model discloses a have the MOSFET pipe, the junction electric capacity of MOSFET pipe is the biggest only 15PF, compares in general analog switch and has higher performance, makes simultaneously the utility model discloses IO drive stability further strengthens, and actual FPGA chip IO stabilizes operating frequency and reaches more than 50 MHZ.

3. The utility model discloses effectively optimized circuit structure and PCB plate structure, can effectively reduce the intensive degree that the positive components and parts of PCB circuit board were placed, and make the components and parts of placing on the PCB circuit board realize the optimal connection, dwindle the PCB board area greatly, the wiring distance is shorter, more does benefit to the stability of signal, reduces the loss.

Drawings

FIG. 1 is a schematic diagram of the multi-path I/O driving connection of the present invention;

FIG. 2 is a schematic circuit diagram of the present invention;

fig. 3 is a schematic diagram of the front side of the PCB of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-2, an IO level shift circuit dedicated for a programmer is shown, which includes an FPGA chip and a ZIF connector, where the FPGA chip has a plurality of I/O pins, the I/O pins are all connected to pins of the ZIF connector in a one-to-one correspondence manner through level shift circuits, the level shift circuit includes a diode D1, a resistor R1, a MOSFET Q1, a transistor Q10, a transistor Q11, a transistor Q12, and a diode D2, one end of the resistor R1 is connected to the corresponding I/O pin of the FPGA chip, the other end of the resistor R1 is connected to an anode of the diode D1, an anode of the diode is connected to a source of the MOSFET Q1, a drain of the MOSFET Q1 is connected to a collector of the transistor Q10, a collector of the transistor Q10 is connected to a cathode of the diode D10, and a cathode of the diode D10 is connected to a collector of the transistor Q12 and a corresponding pin of the ZIF connector, the anode of the diode D10 is connected to the collector of the transistor Q11. The negative electrode of the diode D1 is connected with 3.3V voltage, the negative electrode of the diode D1 is connected with 3.3V voltage, the base of the triode Q10 is connected with VPP1, the emitter is connected with VPP, the base of the triode Q11 is connected with VCC1, the emitter is connected with VCC, the base of the triode Q12 is connected with GND1, the emitter is connected with GND, the VPP1, VCC1 and GND1 are all control signal ends, VPP1, VCC1 and GND1 ports (the first path of level conversion circuit is VPP1, VCC1 and GND1, all 1+ N in the level conversion circuit below the first path of level conversion circuit, and each VPP1+ N, VCC1+ N, GND1+ N is independently connected with one I/O port of a control chip (singlechip) and is connected to the control chip, generally the I/O port of the singlechip, and the VPP1, VCC1 and GND1 of the multi-path level conversion circuit are respectively and are independently connected with corresponding I/O ports of the corresponding single, each I/O port of the single chip microcomputer independently controls the on-off of the corresponding VPP1 or VCC1 or GND1, the VPP and the VCC are voltage power supply ends, the GND is a grounding end, the VPPs in the multi-path level conversion circuits are all connected to a total power supply circuit, and the VCC in the multi-path level conversion circuits is additionally connected to a total power supply circuit.

Multichannel level shift circuit's MOSFET pipe Q1's grid passes through RC filter circuit and 5V voltage connection jointly, RC filter circuit includes series connection's resistance Rg and electric capacity Cg, the concatenation point of resistance Rg with MOSFET pipe Q1's grid is connected, resistance Rg and 5V voltage connection, electric capacity Cg ground connection, MOSFET pipe Q1 is N type MOSFET pipe, MOSFET pipe Q1 chooses SOT323 encapsulation device for use, diode D1 chooses common cathode diode BAT54CW for use, and the diode chooses SOT323 encapsulation equally, and has two diodes in the encapsulation that diode D1 used, and diode D1's encapsulation can provide diode D1 for two flat-level electricity converting unit, effectively improves the space of PCB circuit board, resistance R1 chooses 0603 encapsulation resistance for use.

The specific working principle of the multi-path I/O level conversion circuit is as follows:

the level conversion circuit only uses one N-type MOSFET 2SK3018 (devices of the same type can be used) driven by a low-voltage grid electrode, according to a 2SK3018 data manual, when the grid electrode voltage is only 2.5V, the grid electrode can be completely started, a large number of practical tests are carried out, the grid electrode voltage reaches 1.5V, the grid electrode voltage can be started, the maximum current Ids is only limited to about 5ma at the moment, and when the grid electrode voltage is lower than 1.3V, the grid electrode voltage is completely closed, so that the grid electrode voltage is fixed to about 5.0V, the characteristics of the starting voltage of the MOSFET are fully utilized, and unidirectional level conversion is realized. When VCC or VPP voltage of a pin of a ZIF connector is larger than 4.0V (when I/O of the FPGA chip is in an input state), no matter what the voltage of the pin of the ZIF connector is, the gate voltage Vgs is 5.0V-3.7V 1.3V, the MOSFET tube Q1 is completely closed, so that the voltage of the source electrode can never be higher than 3.7V, and the maximum allowable voltage of the I/O port of the FPGA chip can be 4.0V generally, thereby well protecting the FPGA chip.

Under normal conditions, D1/R1 is not effective, the value range of R1 can be between 0-33 ohms, the voltage of a source electrode is not larger than 3.7V, so that the power loss is 0, R1 and D1 can be eliminated theoretically, and the main function of the protection circuit is to prevent the FPGA chip from being protected under the condition that the MOSFET Q1 breaks down and is damaged.

When the voltage of VCC is 4.0-6.5V, the I/O output voltage of the target chip (the target chip refers to a programmed chip) is 3.5V to 6.0V, and the output port of the target chip is not overloaded at this time. The grids of the MOSFET tubes in the multi-path plane switching circuit unit are connected together in sequence and are connected with a 5V power supply through an RC filter circuit, and pins of the ZIF connector are connected with I/O pins of an FPGA chip one by one through multi-path level switching circuits respectively, so that the wiring difficulty is greatly reduced, the voltage of the MOSFET tubes can be effectively stabilized,

refer to the PCB board that is used for level shift circuit that 3 is shown, provide the wiring for the components and parts among the level shift circuit, PCB circuit board openly is equipped with the FPGA chip and places district and ZIF connector locking seat, the FPGA chip is placed the district and is placed the FPGA chip, be provided with the ZIF connector on the ZIF connector locking seat, ZIF connector pin interval is 2.54 mm.

MOSFET pipe Q1 and diode D1 width are 2mm, because MOSFET pipe Q1 and diode D1's width is less than the interval of ZIF connector pin, consequently MOSFET pipe Q1 and diode D1 set up can be nearer from the ZIF connector pin in the position of PCB board, can set up even in the interval gap of ZIF connector pin, great reduction the area that MOSFET pipe Q1 and diode D1 occupy, triode Q10, triode Q11 and D10, triode Q12 have been placed respectively to the different faces of PCB board, triode Q10, triode Q11 and D10, triode Q12 all correspond the pin with the ZIF connector and are connected, realize the connection of shortest distance, indirect realization VCC, VPP, GND are connected with ZIF connector shortest distance, reduce the loss.

The utility model discloses with triode Q10, triode Q11 and D10, triode Q12 sets up in the different faces of PCB board, can effectively reduce the intensive degree that the positive surface element device of PCB board was placed, make PCB face area littleer, the wiring distance is shorter, be favorable to the stability of signal, reduce the loss, through the wiring that adopts this level conversion circuit in the PCB circuit board, realize the shortest connection between each components and parts, very big reduction loss (the length of wiring is very big to circuit performance influence in high frequency circuit) promotes circuit performance.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The utility model provides a special IO level translation circuit of programmer, includes FPGA chip and ZIF connector, its characterized in that: the FPGA chip is provided with a plurality of I/O pins which are all correspondingly connected with the pins of the ZIF connector through level conversion circuits, the level conversion circuit comprises a diode D1, a resistor R1, a MOSFET tube Q1, a transistor Q10, a transistor Q11, a transistor Q12 and a diode D2, one end of the resistor R1 is connected with an I/O pin corresponding to the FPGA chip, the other end of the resistor is connected with the anode of the diode D1, the anode of the diode is connected with the source electrode of the MOSFET Q1, the drain electrode of the MOSFET Q1 is connected with the collector electrode of the triode Q10, the collecting electrode of triode Q10 with diode D10's negative pole is connected, diode D10's negative pole respectively with triode Q12's collecting electrode and the corresponding pin of ZIF connector are connected, diode D10's positive pole with triode Q11 collecting electrode is connected.

2. The IO level shift circuit of claim 1, wherein: the negative electrode of the diode D1 in the level conversion circuit is connected with 3.3V voltage, the base of the triode Q10 is connected with VPP1, the emitter is connected with VPP, the base of the triode Q11 is connected with VCC1, the emitter is connected with VCC, the base of the triode Q12 is connected with GND1, and the emitter is connected with GND.

3. The IO level shift circuit of claim 2, wherein: VPP1, VCC1, GND1 are control signal terminals, VPP, VCC are voltage power supply terminals, and GND is a ground terminal.

4. The IO level shift circuit for a programmer of claim 3, wherein: the grid of multichannel level shifter circuit's MOSFET pipe Q1 passes through RC filter circuit and 5V voltage connection jointly, RC filter circuit includes series connection's resistance Rg and electric capacity Cg, the concatenation point of resistance Rg with the grid of MOSFET pipe Q1 is connected, resistance Rg and 5V voltage connection, electric capacity Cg ground connection.

5. The IO level conversion circuit dedicated to a programmer of claim 4, wherein: the MOSFET Q1 is an N-type MOSFET.

6. The IO level shift circuit of claim 1, wherein: the MOSFET Q1 is an SOT323 packaged device, the diode D1 is a common cathode diode BAT54CW, the diode is also packaged by SOT323, and the resistor R1 is a 0603 packaged resistor.

7. A PCB board for use in claims 1-6, wherein: provide the wiring for the components and parts among the level shift circuit, PCB circuit board openly is equipped with the FPGA chip and places district and ZIF connector locking seat, the FPGA chip is placed the district and is placed the FPGA chip, be provided with the ZIF connector on the ZIF connector locking seat, ZIF connector pin interval is 2.54 mm.

8. The PCB board of claim 7, wherein: the width of the MOSFET Q1 and the width of the diode D1 are both 2mm, and the MOSFET Q1 and the diode D1 are respectively arranged in a gap between corresponding pins of the ZIF connector.

9. The PCB board of claim 8, wherein: triode Q10, triode Q11 and D10, triode Q12 have been placed respectively to the different faces of PCB board, triode Q10, triode Q11 and D10, triode Q12 all correspond the pin connection with the ZIF connector and directly link to each other.