CN111367841B - High-speed programmer - Google Patents
High-speed programmer Download PDFInfo
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- CN111367841B CN111367841B CN202010232837.4A CN202010232837A CN111367841B CN 111367841 B CN111367841 B CN 111367841B CN 202010232837 A CN202010232837 A CN 202010232837A CN 111367841 B CN111367841 B CN 111367841B
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- circuit board
- digital signal
- signal circuit
- isp
- speed
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The invention discloses a high-speed programmer, which comprises a digital signal circuit board, a DC-DC conversion and VDD/VPP power driving circuit board, wherein the digital signal circuit board is connected with the DC-DC conversion and VDD/VPP power driving circuit board below through a bottom pin header and a bus header connector, an FPGA chip is connected with a locking seat/switching seat through an ISP/switching seat IO digital signal wire, the FPGA chip is connected with an ISP and an expansion interface through an ISP and an expansion IO digital signal wire, and a GND power driving circuit is further arranged at the bottom layer of the digital signal circuit board.
Description
Technical Field
The invention relates to the technical field of programmers, in particular to a high-speed programmer.
Background
The industry generally proceeds as shown in fig. 3 and 4: the following drawbacks exist:
1. the digital signal circuit board is arranged below, the power driving circuit board is connected with the locking seat/switching seat by the pin row female connector in the middle, and the locking seat/switching seat IO digital signals between the FPGA chip and the chip to be programmed are transmitted by the pin row female connector in a crossing way, so that the PCB wiring is long, the impedance is high, the signal frequency is limited, and the product speed cannot reach a higher level; moreover, the pin header female connector is easy to loosen and has overlarge contact resistance, so that high-speed signals are attenuated and unstable, and the reliability of products is affected;
2. the multi-group DC-DC conversion circuit is used for generating multi-path voltages such as VDD/VPP/VCCIO and the like, and is put together with the digital signal circuit board, so that the aim of facilitating centralized control and dynamic adjustment of output voltage is initially achieved, but the multi-group DC-DC conversion circuit can bring non-negligible transmission line interference and radio frequency interference, is too close to an FPGA chip, can bring subtle interference problems, has relatively large influence on high-speed signal integrity, and is challenged in product stability;
3. the power driving circuit board comprises three groups of VDD/VPP/GND, a plurality of triodes are used for providing VDD/VPP power supply and GND loops for chips to be programmed, as shown in FIG. 3, the reference ground of signals of the FPGA chips is arranged on a digital signal circuit board at the lower side, the reference ground of the chips to be programmed on the locking seat/the adapter seat is arranged on the power driving circuit board at the upper side, the two groups of reference grounds are connected through pin row female connectors, the connectors are provided with contact resistors, overlong PCB wires have larger impedance, and dynamic currents driven by the VDD/VPP/GND power are needed, so that the variable voltage difference between the two groups of reference grounds can be caused, the high-speed signal transmission is influenced, the stability of products is poor, and the programming speed is not improved;
4. the locking seat/adapter seat is usually provided with 48 pins at most, the number of IO and power driving pins of the programmer is usually between 48 and 144, and the number exceeds the number of 48 pins, the industry commonly adopts a Dupont wire to be connected with a multi-pin chip on the locking seat/adapter seat through a side ISP and an expansion interface, the signal speed of the connection mode is limited, the operation process is complex, and the user experience is poor;
5. as can be seen from fig. 4, because of the problem of circuit board layout, ISP and expansion IO digital signals must traverse the entire circuit board to the other side, and the high-speed transmission of signals is affected by the excessively long routing, resulting in limited ISP and expansion interface speeds.
Disclosure of Invention
The present invention is directed to a high-speed programmer to solve the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the utility model provides a high-speed programmer, includes digital signal circuit board, DC-DC conversion and VDD/VPP power drive circuit board, the DC-DC conversion and the VDD/VPP power drive circuit board of digital signal circuit board below through bottom row's needle and row female connector connection, be equipped with FPGA chip, locking seat/adapter and ISP and expansion interface on the digital signal circuit board, the FPGA chip passes through locking seat/adapter IO digital signal line connection locking seat/adapter, the FPGA chip passes through ISP and expansion IO digital signal line connection ISP and expansion interface, the bottom of digital signal circuit board still is equipped with GND power drive circuit.
As a further aspect of the invention: and the digital signal circuit board is provided with a USB interface.
As a further aspect of the invention: the DC-DC conversion and VDD/VPP power driving circuit board is provided with a plurality of DC-DC conversion circuits.
As a further aspect of the invention: and the digital signal circuit board is provided with an FPGA chip.
As a further aspect of the invention: the digital signal circuit board is provided with a locking seat/adapter seat.
As a further aspect of the invention: and the digital signal circuit board is provided with an ISP and an expansion interface.
As a further aspect of the invention: the ISP and the expansion interface are positioned on the front surface of the digital signal circuit board.
As a further aspect of the invention: the bottom layer pin header is arranged below the locking seat/adapter seat and on the other side of the circuit board.
As a further aspect of the invention: the digital signal circuit board is above and the DC-DC conversion and VDD/VPP power drive circuit board is below.
Compared with the prior art, the invention has the beneficial effects that:
1. the DC-DC conversion and VDD/VPP power driving circuit is arranged below, and the locking seat/switching seat and the digital signal circuit board are arranged above, so that the locking seat/switching seat IO digital signals between the FPGA and the chip to be programmed are directly connected on the same circuit board at the nearest distance, the adverse effects on the locking seat/switching seat IO digital signals caused by pin header connectors and overlong PCB wiring are thoroughly eliminated, and the high-speed signals are more stable and the product speed is faster;
2. the multi-group DC-DC conversion circuit is used for generating multi-path voltages such as VDD/VPP/VCCIO, and the multi-path voltages are placed on the VDD/VPP power driving circuit board and shielded and filtered, and far away from an MCU/FPGA chip on the digital signal circuit board, the DC-DC interference problem can be effectively solved, the integrity of high-speed signals is ensured, and the stability of products is improved;
3. the GND power driving circuit is placed at the bottom layer of the digital signal circuit board, so that the reference ground of an FPGA signal and the reference ground of a chip to be programmed are ensured to be connected nearby on the same circuit board, the dynamic current of the pin header connector, the overlong PCB wiring and the VDD/VPP/GND power driving circuit is stopped, the adverse effect on the two reference grounds is avoided, the stability of high-speed digital signals is improved, and the product speed is improved;
4. the ISP and the expansion interface are placed on the front surface, the chip beyond 48 feet is arranged, the pin arrangement of the chip adapter is directly inserted into the locking seat
The adapter is arranged on the same surface and ISP and expansion interfaces at different positions, does not need to be connected with a DuPont line, and has the advantages of simpler operation and better user experience;
5. ISP and expansion interface are placed on the front surface, ISP and expansion IO digital signals are also connected to FPGA nearby, and the shorter connecting line can improve the transmission speed and stability of signals and the product speed.
In a word, the invention adopts a relatively shorter and impedance-matched PCB connecting line, a minimum connector and an optimized structural scheme, ensures the integrity of high-speed signals, is far away from DC-DC interference, and performs shielding and filtering, thereby achieving higher speed and stable operation, and being more convenient for users to use.
Drawings
Fig. 1 is a side view of the present invention.
Fig. 2 is a top view of a digital signal circuit board of the present invention.
Fig. 3 is a side view of the prior art.
Fig. 4 is a top view of a prior art digital signal circuit board.
In the figure: the power supply comprises a 1-USB interface, a 2-FPGA chip, a 3-locking seat/adapter seat, a 4-ISP and expansion interface, a 5-locking seat/adapter seat IO digital signal line, a 6-ISP and expansion IO digital signal line, a 7-GND power driving circuit, an 8-bottom pin header, a 9-digital signal circuit board, a 10-bus connector and a 11-DC-DC conversion and VDD/VPP power driving circuit board.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Please refer to fig. 1-2:
example 1: in the embodiment of the invention, the high-speed programmer comprises a digital signal circuit board 9 and a DC-DC conversion and VDD/VPP power driving circuit board 11, wherein the digital signal circuit board 9 is connected with the DC-DC conversion and VDD/VPP power driving circuit board 11 through a bottom pin header 8 and a bus header connector 10, an FPGA chip 2 is connected with a locking seat/switching seat 3 through a locking seat/switching seat IO digital signal wire 5, the FPGA chip 2 is connected with an ISP and expansion interface 4 through an ISP and expansion IO digital signal wire 6, and the bottom layer of the digital signal circuit board 9 is also provided with a GND power driving circuit 7. The digital signal circuit board 9 is provided with a USB interface 1. The DC-DC conversion and VDD/VPP power driving circuit board 11 is provided with a plurality of DC-DC conversion circuits. The digital signal circuit board 9 is provided with an FPGA chip 2. The digital signal circuit board 9 is provided with a locking seat/adapter seat 3. The digital signal circuit board 9 is provided with an ISP and expansion interface 4. The bottom layer pin header 8 is arranged below the locking seat/adapter seat 3 and on the other side of the circuit board.
Example 2: on the basis of embodiment 1, as shown in fig. 2, an ISP and an expansion interface are placed on the front surface, the ISP and the expansion IO digital signals are also connected to the FPGA nearby, the shorter connection line can improve the transmission speed and stability of the signals, and improve the product speed, and meanwhile, the expansion interface is placed on the front surface, so that the use of the multi-pin adapter is also facilitated;
it will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (9)
1. The utility model provides a high-speed programmer, including digital signal circuit board (9), DC-DC conversion and VDD/VPP power drive circuit board (11), a serial communication port, DC-DC conversion and VDD/VPP power drive circuit board (11) of digital signal circuit board (9) below through bottom row needle (8) and row female connector (10) connection, be equipped with FPGA chip (2) on digital signal circuit board (9), locking seat/switching seat (3) and ISP and expansion interface (4), locking seat/switching seat (3) are connected through locking seat/switching seat IO digital signal line (5) in FPGA chip (2), ISP and expansion interface (4) are connected through ISP and expansion IO digital signal line (6) in FPGA chip (2), the bottom of digital signal circuit board (9) still is equipped with GND power drive circuit (7).
2. A high-speed programmer according to claim 1, characterized in that the digital signal circuit board (9) is provided with a USB interface (1).
3. A high-speed programmer according to claim 1, characterized in that the DC-DC conversion and VDD/VPP power drive circuit board (11) is provided with a plurality of DC-DC conversion circuits.
4. A high-speed programmer according to claim 1, characterized in that the digital signal circuit board (9) is provided with an FPGA chip (2).
5. A high-speed programmer according to claim 1, characterized in that the digital signal circuit board (9) is provided with locking/adapter seats (3).
6. A high-speed programmer according to claim 4, characterized in that the digital signal circuit board (9) is provided with an ISP and expansion interface (4).
7. A high-speed programmer according to claim 6, characterized in that the ISP and expansion interface (4) is located on the front side of the digital signal circuit board (9).
8. A high-speed programmer according to claim 5, characterized in that the bottom row of pins (8) is mounted under the locking/adapter (3) on the other side of the circuit board.
9. A high-speed programmer according to claim 1, characterized in that the digital signal circuit board (9) is above and the DC-DC conversion and VDD/VPP power drive circuit board (11) is below.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010232837.4A CN111367841B (en) | 2020-03-28 | 2020-03-28 | High-speed programmer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010232837.4A CN111367841B (en) | 2020-03-28 | 2020-03-28 | High-speed programmer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111367841A CN111367841A (en) | 2020-07-03 |
| CN111367841B true CN111367841B (en) | 2023-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010232837.4A Active CN111367841B (en) | 2020-03-28 | 2020-03-28 | High-speed programmer |
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| Country | Link |
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| CN (1) | CN111367841B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203732702U (en) * | 2014-02-28 | 2014-07-23 | 湖南电气职业技术学院 | DSP and FPGA based variable frequency power supply electrical parameter measuring system |
| CN106681213A (en) * | 2017-01-04 | 2017-05-17 | 北京润科通用技术有限公司 | Automatic code generating loading platform system |
| CN106774030A (en) * | 2017-03-08 | 2017-05-31 | 北京航空航天大学 | A kind of general purpose controller of the power electronic system based on DSP+FPGA |
| CN207925808U (en) * | 2018-03-23 | 2018-09-28 | 深圳市新蕾电子有限公司 | The device of switching high speed signal between the circuit board of different function |
| CN110113864A (en) * | 2019-05-11 | 2019-08-09 | 武汉精立电子技术有限公司 | A kind of PCB pin layout method and structure of module board, module board |
| CN209946887U (en) * | 2019-04-30 | 2020-01-14 | 王葆春 | Special IO level switching circuit of programmer and PCB |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200739335A (en) * | 2006-04-07 | 2007-10-16 | Sunplus Technology Co Ltd | Circuit emulation system having function of burning record |
-
2020
- 2020-03-28 CN CN202010232837.4A patent/CN111367841B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203732702U (en) * | 2014-02-28 | 2014-07-23 | 湖南电气职业技术学院 | DSP and FPGA based variable frequency power supply electrical parameter measuring system |
| CN106681213A (en) * | 2017-01-04 | 2017-05-17 | 北京润科通用技术有限公司 | Automatic code generating loading platform system |
| CN106774030A (en) * | 2017-03-08 | 2017-05-31 | 北京航空航天大学 | A kind of general purpose controller of the power electronic system based on DSP+FPGA |
| CN207925808U (en) * | 2018-03-23 | 2018-09-28 | 深圳市新蕾电子有限公司 | The device of switching high speed signal between the circuit board of different function |
| CN209946887U (en) * | 2019-04-30 | 2020-01-14 | 王葆春 | Special IO level switching circuit of programmer and PCB |
| CN110113864A (en) * | 2019-05-11 | 2019-08-09 | 武汉精立电子技术有限公司 | A kind of PCB pin layout method and structure of module board, module board |
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| Publication number | Publication date |
|---|---|
| CN111367841A (en) | 2020-07-03 |
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