CN111211772A

CN111211772A - Circuit with high-speed IO (input/output) and high-voltage circuit of programmer coexisting

Info

Publication number: CN111211772A
Application number: CN202010197382.7A
Authority: CN
Inventors: 季春
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-03-19
Filing date: 2020-03-19
Publication date: 2020-05-29

Abstract

The invention discloses a circuit with a programmer high-speed IO coexisting with a high-voltage circuit, which comprises an FPGA chip U1A, an MOS tube M1, a resistor RS1, a triode QC1, a triode QP1 and a triode QN1, wherein an IO power supply pin of the FPGA chip U1A is connected with a program-controlled variable voltage VCCIO, a general port IO1 of the FPGA chip U1A is connected with a resistor RS1, the other end of the resistor RS1 is connected with a source electrode of the MOS tube M1, a gate electrode of the MOS tube M1 is connected with a program-controlled variable voltage VG, and a drain electrode of the MOS tube M1 is connected with a locking seat ZIF1 and a VDD/VPP/GND driving circuit. By using the circuit structure of the invention, the IO clock speed of the universal programmer product can reach 60MHz, which is far more than similar products of other companies. And because VPP high pressure can not add on FPGA IO, so complete machine power consumption also greatly reduced, calorific capacity reduces, directly uses USB can provide complete machine operating current, and the like product all needs extra power adapter at present.

Description

Circuit with high-speed IO (input/output) and high-voltage circuit of programmer coexisting

Technical Field

The invention relates to the technical field of programmers, in particular to a circuit with a high-speed IO (input/output) and a high-voltage circuit coexisting in a programmer.

Background

Currently, an IO driving structure of a full-drive general programmer of other companies is shown in fig. 1 (an actual product has 48 to 144 identical IO driving circuits), ZIF1 is a programmer lock socket interface and is connected to pins of a target chip, and the pins may function as general IO, chip power supply VDD, chip programming high-voltage VPP or power supply GND, so that the circuit shown in fig. 1 needs to be configured to perform different functions. The circuit structure has a bottleneck that the IO speed is not high during programming, and particularly, the read-write speed of a data bus of weak pull-up bidirectional IO built in a target chip, such as a NAND flash memory, is difficult to exceed 1 MB/S. In addition, the VPP circuit consumes a very large amount of power, and RS1 requires a large-power resistor, resulting in a large amount of heat generation.

The specific reasons are as follows: the CE poles of the three triodes QC1/QP1/QN1 have junction capacitors, the triodes of different models have the capacitance of several pF to tens of pF, and the junction capacitors and RS1 form an RC integrating circuit, so that the waveform of a high-speed IO signal is seriously distorted, and the improvement of the reading and writing speed of a programmer is limited.

If the speed bottleneck needs to be solved, only two ways are provided, namely, the PN junction capacitance of the triode is reduced, and the triode with smaller PN junction capacitance is difficult to be manufactured due to the limitation of a semiconductor process.

Secondly, the resistance of the RS1 is reduced, but in the circuit, the RS1 is used as a current-limiting resistor of the VPP voltage to protect the FPGA IO from being burned out, assuming that VPP is 21.5V, VCCIO is 3.3V, and QP1 is turned on, at this time, the voltage drop across the RS1 is 21.5-3.3-0.7-17.5V, and the power consumption of the RS1 is U2/R is 0.93W, which is quite large. If RS1 is reduced to 100 ohms, the power consumption of RS1 reaches 3.06W, obviously far exceeds the maximum power of a common chip resistor, the power consumption of the whole machine is very large, and therefore, in order to improve the speed, the contradiction between VPP power supply, RS1 resistor and triode junction capacitor must be solved.

Disclosure of Invention

The present invention is directed to a circuit with a high-speed IO compatible with a high-voltage circuit of a programmer, so as to solve the problems mentioned in the background art.

In order to achieve the purpose, the invention provides the following technical scheme:

a circuit with high-speed IO and high-voltage circuits of a programmer, which comprises an FPGA chip U1A, an MOS tube M1, a resistor RS1, a triode QC1, a triode QP1 and a triode QN1, the input/output (IO) power supply pin of the FPGA chip U1A is connected with a program-controlled variable voltage VCCIO, the general port IO1 of the FPGA chip U1A is connected with a resistor RS1, the other end of the resistor RS1 is connected with the source electrode of an MOS tube M1, the gate electrode of the MOS tube M1 is connected with a program-controlled variable voltage VG, the drain electrode of the MOS tube M1 is connected with the cathode of a diode DC1, a locking seat ZIF1, the collector electrode of a triode QP1 and the collector electrode of a triode QN1, the anode of the diode DC1 is connected with the collector electrode of a triode QC1, the base electrode of the triode QC1 is connected with a VDD driving chip, the emitter electrode of the triode QC1 is connected with a power supply VDD, the emitter electrode of the triode QP1 is connected with the power supply VPP, the base electrode of the.

As a further scheme of the invention: the voltage range of the program-controlled variable voltage VCCIO is DC 1.2-3.6V.

As a further scheme of the invention: the voltage range of the power supply VDD is DC 1.2-6.5V.

As a further scheme of the invention: the voltage range of the power supply VPP is typically DC 6-25V.

As a further scheme of the invention: the program-controlled variable voltage VG is controlled by an MCU or FPGA program.

As a further scheme of the invention: the MOS tube M1 is one of 2N7002, 2SK1658, 2SK3018 and 2SK 3019.

As a further scheme of the invention: the transistor QC1 and the transistor QP1 are PNP transistors, and the transistor QN1 is an NPN transistor.

Compared with the prior art, the invention has the beneficial effects that: by using the circuit structure of the invention, the IO clock speed of the universal programmer product can reach 60MHz, which is far more than similar products of other companies. And because VPP high pressure can not add on FPGA IO, so complete machine power consumption also greatly reduced, calorific capacity reduces, directly uses USB can provide complete machine operating current, and the like product all needs extra power adapter at present.

Drawings

Fig. 1 is a circuit diagram of the prior art.

Fig. 2 is a circuit diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, embodiment 1: in the embodiment of the invention, a circuit with a programmer high-speed IO and a high-voltage circuit coexisting comprises an FPGA chip U1A, an MOS tube M1, a resistor RS1, a triode QC1, a triode QP1 and a triode QN1, the input/output (IO) power supply pin of the FPGA chip U1A is connected with a program-controlled variable voltage VCCIO, the general port IO1 of the FPGA chip U1A is connected with a resistor RS1, the other end of the resistor RS1 is connected with the source electrode of an MOS tube M1, the gate electrode of the MOS tube M1 is connected with a program-controlled variable voltage VG, the drain electrode of the MOS tube M1 is connected with the cathode of a diode DC1, a locking seat ZIF1, the collector electrode of a triode QP1 and the collector electrode of a triode QN1, the anode of the diode DC1 is connected with the collector electrode of a triode QC1, the base electrode of the triode QC1 is connected with a VDD driving chip, the emitter electrode of the triode QC1 is connected with a power supply VDD, the emitter electrode of the triode QP1 is connected with the power supply VPP, the base electrode of the. The design aims at solving the contradiction between high speed and VPP high voltage, an automatic switch circuit consisting of N-channel MOS tubes is used, the voltage range of VCCIO in the figure is DC 1.2-3.6V, the voltage range of VDD is usually DC 1.2-6.5V, the voltage range of VPP is usually DC6-25V, the three are all determined by the parameters of a chip to be programmed on a locking seat, VG is program-controlled variable voltage and is controlled by an MCU or FPGA program and adjustable in a certain range, and the on and off of an MOS tube M1 can be accurately controlled under different VCCIO voltages. The calculation formula is VG ═ VCCIO + Vf (Desd1) + Vgsth (M1), where Vf (Desd1) is the forward voltage drop of IO esd protection diode Desd1 inside FPGA, usually between 0.5V and 0.7V, and Vgsth (M1) is the turn-on voltage of MOS transistor M1, usually between 1.5V and 2.5V.

It is assumed that Vf (Desd1) is 0.7V, Vgsth (M1) is 2V, VDD and IO voltages of the chip to be burned are 3.3V, VPP is 12V, VCCIO is adjusted by the MCU program to be 3.3V, and VG is 3.3+0.7+2 is 6V.

Because of the chip pin to be burned corresponding to ZIF1, there may be 4 cases: VDD/VPP/GND or signal IO, therefore we analyze in 4 cases:

1. when the chip pin corresponding to the position of the locking seat ZIF1 is supplied with power by VDD, the FPGA IO corresponding to the point A is internally set to be a push-pull output high level, and the voltage of the point A is approximately equal to 3.3V at the moment. Then a VDD driving 1 signal is controlled by the MCU to be pulled down, the VDD voltage is 3.3V and is added to ZIF1, at the moment, the D pole of M1 is 3.3V, the G pole is 6V, the S pole voltage is approximately equal to 3.3V, the voltage of the D pole is the same as that of the S pole, M1 is in a turn-off state, and the VDD power supply cannot be loaded to FPGA IO;

2. when the chip pins corresponding to the positions of the locking seats ZIF1 supply power for the VPP, the interior of the FPGA IO corresponding to the point A is set to be in a suspension state. At the moment, a signal of 'VPP drive 1' is controlled to be pulled down by an MCU (microprogrammed control Unit), then VPP high voltage 12V is added to ZIF1, at the moment, the D pole of M1 is 12V, the G pole is 6V, the voltage of a point A is clamped at VCCIO + Vf (Desd1), namely 4V, the voltage of an S pole is slightly higher than 4V, at the moment, M1 is in a linear state close to turn-off, so that a small current of several milliamperes can pass through an MOS (metal oxide semiconductor) transistor M1, under the condition that parameters of VG, VCCIO and an MOS transistor M1 are determined, the current depends on the resistance of RS1, and the resistance of RS1 is adjusted in a design stage to ensure that the actual power consumption of the MOS transistor M1 and;

3. when the chip pin corresponding to the position of the locking seat ZIF1 is GND, the FPGA IO corresponding to the point A is internally set to be a push-pull output low level, and the voltage of the point A is approximately equal to 0V at the moment. Then a 'GND drive 1' signal is controlled by the MCU to be pulled up, the ZIF1 is pulled down by the QN1 to be grounded, at the moment, the D pole of M1 is close to 0V, the G pole is 6V, the S pole voltage is approximately equal to 0V, the voltage of the D pole is the same as that of the S pole, at the moment, the M1 is in a turn-off state, and the normal work of a GND circuit is not influenced;

4. when a chip pin signal IO corresponding to the position of the locking seat ZIF1 is provided, the interior of the FPGA IO corresponding to the point A is set to be input, output or tri-state according to needs, and no matter in which state, the voltage of the point A is between 0 and 3.3V, the voltage of the G is always 6V, the GS voltage difference is between 2.7 and 6V and is greater than the opening voltage Vgsth (M1) of M1 (here, 2V), so that the M1 is always in a conducting state, the DS pole is equivalent to a lead, a bidirectional signal can be passed, at the moment, only a small resistor RS1 is provided between the FPGA IO and the chip on the ZIF1 locking seat (according to product needs, the value of the resistor can be properly adjusted between 10 ohms and 100 ohms, namely, the balance between the IO speed and RS1/M1 current and power consumption can be ensured), the waveform distortion is very small, and the read.

If the IO voltage of the chip is other values, for example, 1.8V, we only need to program VCCIO to 1.8V, and VG is 1.8+0.7+2 is 4.5V to normally drive and read/write the chip. In order to achieve the best effect, an FPGA product with the highest IO input voltage resistance of 5V is selected, under different VCCIO conditions, the voltage applied to the FPGA IO is always clamped in a safe value range, and the analysis method under different VDD/VPP/VCCIO/VG voltages is the same except that the voltage values are different, and the description is not repeated here.

By using the circuit structure, the IO clock speed of the universal programmer product can reach 60MHz, which is far higher than similar products of other companies. And because VPP high pressure can not add on FPGA IO, so complete machine power consumption also greatly reduced, calorific capacity reduces, directly uses USB can provide complete machine operating current, and the like product all needs extra power adapter at present.

Example 2: on the basis of the embodiment 1, the M1 uses an N-channel MOS transistor as a switch, and has various models, for example, many similar models such as 2N7002, 2SK1658, 2SK3018, 2SK3019 and the like can be used, and the VG parameter is adjusted; VG is program-controlled variable voltage, is controlled by MCU or FPGA program, is coordinated with VCCIO to adjust within a certain range, and can accurately control the on and off of MOS pipe M1 under different VCCIO voltages.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A circuit with high-speed IO and high-voltage circuits of a programmer, which comprises an FPGA chip U1A, an MOS tube M1, a resistor RS1, a triode QC1, a triode QP1 and a triode QN1, the FPGA-based driving circuit is characterized in that an IO power supply pin of the FPGA chip U1A is connected with a program-controlled variable voltage VCCIO, a general port IO1 of the FPGA chip U1A is connected with a resistor RS1, the other end of the resistor RS1 is connected with a source electrode of an MOS tube M1, a gate electrode of the MOS tube M1 is connected with a program-controlled variable voltage VG, a drain electrode of the MOS tube M1 is connected with a cathode of a diode DC1, a locking seat ZIF1, a collector electrode of a triode QP1 and a collector electrode of a triode QN1, an anode of the diode DC1 is connected with a collector electrode of a triode QC1, a base electrode of the triode 1 is connected with a VDD driving chip, an emitter electrode of the triode QC1 is connected with a power supply VDD, an emitter electrode of the triode QP1 is connected with a power supply VPP, a base electrode of the QP.

2. The circuit of claim 1, wherein the programmable variable voltage VCCIO is in a voltage range of DC 1.2-3.6V.

3. The circuit of claim 1, wherein the voltage range of the power supply VDD is DC 1.2-6.5V.

4. The circuit of claim 1, wherein the power supply VPP voltage is generally in the range of DC 6-25V.

5. The circuit of claim 1, wherein the programmable variable voltage VG is programmed by an MCU or an FPGA.

6. The circuit of claim 4, wherein the MOS transistor M1 is one of 2N7002, 2SK1658, 2SK3018 and 2SK 3019.

7. The circuit of claim 4, wherein the transistor QC1 and the transistor QP1 are PNP transistors and the transistor QN1 is NPN transistor.