CN214480548U

CN214480548U - High-voltage driving circuit

Info

Publication number: CN214480548U
Application number: CN202120243156.8U
Authority: CN
Inventors: 张胜; 谭在超; 丁国华; 罗寅
Original assignee: Suzhou Covette Semiconductor Co ltd
Current assignee: Suzhou Covette Semiconductor Co ltd
Priority date: 2021-01-28
Filing date: 2021-01-28
Publication date: 2021-10-22
Anticipated expiration: 2031-01-28

Abstract

The utility model discloses a high voltage drive circuit, circuit include power offset module and drive circuit module, the circuit has improved drive voltage's power input voltage by a wide margin, and the magnitude of voltage can be as high with the high-pressure MOS tube source leakage breakdown voltage in the circuit, and the grid source drive voltage of high-pressure MOS pipe is 5V, guarantees to work in order to guarantee the defeated tub of safe and reliable ground of drive. Meanwhile, a dead time control circuit consisting of a high-voltage PMOS tube P3, a high-voltage NMOS tube N4, a resistor R5, a high-voltage NMOS tube N3, a high-voltage PMOS tube P4 and a resistor R4 is additionally arranged in the power generation circuit, so that the high-voltage PMOS tube P2 and the high-voltage NMOS tube N2 can be ensured not to be conducted simultaneously, and the safety of an output MOS tube is protected.

Description

High-voltage driving circuit

Technical Field

The utility model relates to an analog integrated circuit design field, concretely relates to high voltage drive circuit.

Background

In the design process of analog integrated circuit, we often use a driving circuit. The structure of a conventional driving circuit is shown in fig. 1, in which P0 is a PMOS transistor, N0 is an NMOS transistor, and P0 and N0 are driving output tubes of the driving circuit; inv1 and inv2 are inverters for driving the PMOS transistor P0 and the NMOS transistor N0, respectively; the devices in the circuit all operate between ground and the supply VDD. The circuit of this structure has two disadvantages: 1. the gate-source voltage swings of the output tubes P0 and N0 are ground and power VDD, so the power voltage VDD cannot be higher than the gate-source breakdown voltage, and the application range of the power voltage is limited. 2. The output tubes P0 and N0 are on simultaneously, so that a large current flows from the power supply to the ground through P0 and N0, and the output tubes P0 and N0 are damaged.

SUMMERY OF THE UTILITY MODEL

Based on the above mentioned problems, the present invention discloses a high voltage driving circuit, which improves the application range of the power voltage, increases the dead time control circuit, prevents the output tube from conducting at the same time, the circuit includes a power Bias module (Bias) and a driving circuit module (Driver), the power Bias module includes a high voltage PMOS transistor P1, a high voltage NMOS transistor N1, a regulator D1, a regulator D2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a resistor R1 is connected in series with a regulator D1, a source of an NMOS transistor N1 is connected with a capacitor C1 to form VREG, a gate of the NMOS transistor N1 is connected with a junction of the resistor R1 and the regulator D1, the resistor D2 is connected in series with the resistor R2, a source of the high voltage PMOS transistor P1 is connected with the capacitor C2 to form a VHS, a gate of the high voltage transistor P5 is connected with a resistor R5857324R 2, the driving circuit module comprises a high-voltage NMOS transistor N2, a high-voltage PMOS transistor P2, an inverter X2, a NOR gate X2, a NAND gate X2, a resistor R2 and a resistor R2, wherein the input end of the inverter X2 is connected with an input signal of the driving circuit, the output end of the inverter X2 is connected with the gate of the high-voltage NMOS transistor N2 and the second input end of the NAND gate X2, the drain of the high-voltage PMOS transistor N2 is connected with the drain of the high-voltage PMOS transistor P2, the source of the high-voltage PMOS transistor P2 is connected with one end of the resistor R2 and the input end of the inverter X2, the other end of the resistor R2 is connected with a power supply VDD, the output end of the NOR gate X2 of the inverter X2, and the first input end of the inverter X2 is connected with the output end of the NOR gate X2. The input end of an inverter X1 is connected with the source of a high-voltage PMOS tube P4 and one end of a resistor R4, the other end of the resistor R4 is connected with a power supply VDD, the output end of a NOR gate X7 is connected with the input end of an inverter X3, the output end of an inverter X3 is sequentially connected with the gates of a high-voltage PMOS tube P2 and a high-voltage PMOS tube P3, the sources of a high-voltage PMOS tube P2 and a high-voltage PMOS tube P3 are connected with the power supply VDD, the drain of a high-voltage PMOS tube P3 is connected with the drain of a high-voltage NMOS tube N4, the source of a high-voltage NMOS tube N4 is connected with one end of a resistor R5 and the input end of an inverter X5, the other end of the resistor R5 is grounded, the output end of the inverter X5 is connected with a first input end of a NAND gate X5, the output end of the NAND gate X5 is connected with the input end of the inverter X5, the output end of the inverter X5 is sequentially connected with the drains of a high-voltage NMOS tube N5 and the drain of the high-voltage NMOS tube N5 are respectively connected with the drain of the NMOS tube P5. The drain electrode of the high-voltage NMOS tube N2 is connected with the drain electrode of the high-voltage PMOS tube P2 and the output end of the high-voltage drive circuit.

As an improvement of the present invention, the high voltage NMOS transistor N2 and the high voltage PMOS transistor P2 are power driven output tubes.

As an improvement of the present invention, the inverter X1, the inverter X2, the inverter X3, and the nor gate X7 operate in a voltage domain between VDD and VHS.

As an improvement of the present invention, the inverter X4, the inverter X5, the inverter X6, and the nand gate X8 operate in the voltage domain between VREG and ground.

As an improvement of the utility model, the signal high level is the VDD voltage, and the signal low level is the VHS voltage, and the relative voltage difference of VDD voltage and VHS voltage is 5V.

As an improvement of the utility model, the signal high level is the VREG voltage, and the signal low level is ground, and the voltage difference of VREG voltage and ground is 5V.

As an improvement of the utility model, the threshold value of opening of high pressure PMOS pipe P1 and high pressure NMOS pipe N1 all is 1.5V, and stabilivolt D1 and stabilivolt D2's steady voltage value is 6.5V.

The utility model has the advantages that: the utility model discloses a circuit has improved drive voltage's power input voltage by a wide margin, and the magnitude of voltage can be as high with the high-pressure MOS pipe source leakage breakdown voltage in the circuit, and the grid source drive voltage of high-pressure MOS pipe is 5V, guarantees to work in order to guarantee the defeated tub safe and reliable ground of drive. Meanwhile, a dead time control circuit consisting of a high-voltage PMOS tube P3, a high-voltage NMOS tube N4, a resistor R5, a high-voltage NMOS tube N3, a high-voltage PMOS tube P4 and a resistor R4 is additionally arranged in the power generation circuit, so that the high-voltage PMOS tube P2 and the high-voltage NMOS tube N2 can be ensured not to be conducted simultaneously, and the safety of an output MOS tube is protected.

Drawings

Fig. 1 is a schematic diagram of a driving circuit in the prior art.

Fig. 2 is a schematic diagram of a driving circuit structure according to the present invention.

Fig. 3 is a waveform diagram illustrating the operation of each node in the driving circuit when the input signal changes from low level to high level.

Fig. 4 is a waveform diagram illustrating the operation of each node in the driving circuit when the input signal changes from high level to low level.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings and embodiments, which are to be understood as illustrative only and not limiting the scope of the invention.

Example (b): according to the figure 2, the circuit comprises a power supply bias module and a driving circuit module, wherein the power supply bias module comprises a high-voltage PMOS tube P1, a high-voltage NMOS tube N1, a voltage regulator tube D1, a resistor R1, a capacitor C1 and a capacitor C1, the resistor R1 is connected with the voltage regulator tube D1 in series, the source electrode of the NMOS tube N1 is connected with the capacitor C1 to form VREG, the grid electrode of the NMOS tube N1 is connected with the connection position of the resistor R1 and the voltage regulator tube D1, the voltage regulator tube D1 is connected with the resistor R1 in series, the source electrode of the high-voltage PMOS tube P1 is connected with the capacitor C1 to form VHS, the grid electrode of the high-voltage PMOS tube P1 is connected with the connection position of the voltage regulator tube D1 and the resistor R1, the driving circuit module comprises the high-voltage NMOS tube N1, the high-voltage PMOS tube P1, the inverter 1, the high-voltage PMOS tube P1, the inverter 1 and the high-voltage PMOS X1, An inverter X4, an inverter X5, an inverter X6, a nor gate X7, a nand gate X8, a resistor R3, a resistor R4 and a resistor R4, wherein an input terminal of the inverter X4 is connected with an input signal of the driving circuit, an output terminal of the inverter X4 is connected with a gate of a high-voltage NMOS transistor N4 and a second input terminal of the nand gate X4, a drain of the high-voltage NMOS transistor N4 is connected with a drain of the high-voltage PMOS transistor P4, a source of the high-voltage PMOS transistor P4 is connected with one end of the resistor R4 and an input terminal of the inverter X4, the other end of the resistor R4 is connected with a power supply VDD, an output terminal of the inverter X4 is connected with a first input terminal of the nor gate X4, an output terminal of the nor gate X4 is connected with a second input terminal of the nor gate X4, an input terminal of the high-voltage PMOS transistor P4 and one end of the resistor R4, the other end of the resistor R4 is connected with the high-voltage PMOS transistor P4, the high-voltage PMOS tube P2 and the source of the high-voltage PMOS tube P3 are connected with a power supply VDD, the drain of the high-voltage PMOS tube P3 is connected with the drain of a high-voltage NMOS tube N4, the source of the high-voltage NMOS tube N4 is connected with one end of a resistor R5 and the input end of an inverter X5, the other end of the resistor R5 is grounded, the output end of the inverter X5 is connected with the first input end of a NAND gate X8, the output end of the NAND gate X8 is connected with the input end of the inverter X6, the output end of the inverter X6 is sequentially connected with the gates of the high-voltage NMOS tube N2 and the high-voltage NMOS tube N3, the source of the high-voltage NMOS tube N3 and the source of the high-voltage NMOS tube N2 are grounded respectively, the drain of the high-voltage PMOS tube P4 is connected with the drain of the high-voltage NMOS tube N3, the drain of the high-voltage NMOS tube N2 is connected with the drain of the high-voltage PMOS tube P2 and the output end of the high-voltage PMOS tube P2 and the high-voltage PMOS tube P2 are power drive output tube, the VHX 1, the inverter X2, the inverter X3 and the NOR gate circuit VDD working voltage of the VHX 7 are connected between the VHX 3929 and the VHX 46X working region. The high level of the signal is VDD voltage, the low level of the signal is VHS voltage, the relative voltage difference between the VDD voltage and the VHS voltage is 5V, the inverter X4, the inverter X5, the inverter X6 and the nand gate logic circuit X8 work in a voltage domain between VREG and ground, the high level of the signal is VREG voltage, the low level of the signal is ground, the voltage difference between VREG voltage and ground is 5V, the turn-on threshold values of the high-voltage PMOS transistor P1 and the high-voltage NMOS transistor N1 are both 1.5V, the voltage stabilizing values of the voltage regulator tube D1 and the voltage regulator tube D2 are 6.5V, and in the power supply bias module circuit, the voltage value of the node V1 is equal to the voltage stabilizing value of the voltage regulator tube D1, that is: v1 ═ 6.5V;

therefore, the voltage of the reference voltage VREG is: VREG-V1-VGS 1-6.5V-1.5V-5V;

where VGS1 is the gate-source voltage of NMOS transistor N1, which is approximately the turn-on voltage.

The voltage value of the node V2 is equal to the regulated value of the power supply voltage VDD minus the regulated voltage value of the voltage regulator tube D2, that is: V2-VDD-6.5V;

the voltage of reference voltage VHS is therefore: VHS-V2 + VGS 2-VDD-6.5V + 1.5V-VDD-5V;

where VGS2 is the gate-source voltage of PMOS transistor P1, which is approximately its turn-on voltage.

In the driving circuit module, N2, N3, N4 and N5 are high-voltage NMOS tubes, and N2 is used as a power driving output tube; p2, P3, P4 and P5 are high-voltage PMOS tubes, and P2 is used as a power driving output tube; X1-X6 are inverters; x7 is a NOR gate logic circuit, and X8 is a NAND gate logic circuit; R3-R5 are resistors, and IN and OUT are input and output pins of the driving circuit, respectively.

In the circuit, X1-X3 and X7 operate in a voltage range between VDD and VHS, the high level of a signal is VDD voltage, the low level of the signal is VHS voltage, the relative voltage difference is 5V, X4-X6 and X8 operate in a voltage range between VREG and ground, the high level of the signal is VREG voltage, the low level of the signal is ground, and the relative voltage difference is 5V.

The utility model discloses a working principle of circuit as follows:

as shown IN fig. 3, when the input signal IN changes from low level to high level at time t1, the lower input terminal of the nand gate X8 changes to low level, so that X8 outputs a high VREG voltage quickly, the signal level of the Ngate node changes to low level, the output tube N2 is turned off, the NMOS tube N3 is turned off, the voltage of the Ngate _ B node is delayed to output a high VDD voltage at time t2, and the length of the delay time t2 is determined by the resistor R4.

When the input signal IN changes from low level to high level at time t1, the high-voltage NMOS transistor N5 is turned off, the IN _ H node outputs high-level VDD voltage, after the signal Ngate _ B also changes to high-level VDD voltage at time t2, the nor gate X7 outputs high-level VDD voltage, the Pgate node outputs low-level VHS, the high-voltage PMOS transistor P2 is turned on, the output signal OUT changes to high-level VDD voltage, and the time difference between t2 and t1 is the dead time between the turning-off of the high-voltage NMOS transistor N2 and the conduction of the high-voltage PMOS transistor P2, so that the simultaneous conduction of the high-voltage PMOS transistor P2 and the high-voltage NMOS transistor N2 can be prevented.

As shown IN fig. 4, when the input signal IN changes from high level to low level at time t3, the high-voltage NMOS transistor N5 is turned on, the IN _ H node outputs a low-level VHS voltage, the upper input terminal of the nor gate X7 changes to a high-level VDD voltage, so the nor gate logic circuit X7 outputs a low-level VHS voltage quickly, the signal level of the Pgate node changes to a high-level VDD voltage, the high-voltage PMOS transistor P2 is turned off, the high-voltage PMOS transistor P3 is turned off, the Pgate _ B outputs a high-level VREG voltage at time t4 after being delayed, the length of the t4 delay is determined by the resistor R5, the input signal IN changes from high level to low level at time t3, the lower input terminal of the nand gate X8 changes to a high-level VREG voltage, the nand gate X8 outputs a low level after the Pgate _ B signal also changes to a high-level VREG voltage at time t4, the ngte node outputs a high-level VREG voltage, the NMOS transistor N2 is turned on, and the output signal OUT voltage changes to a low level, the time difference between t4 and t3 is the dead time between the turn-off of the high voltage PMOS transistor P2 and the turn-on of the high voltage NMOS transistor N2, which prevents the simultaneous turn-on of the high voltage PMOS transistor P2 and the high voltage NMOS transistor N2.

In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made without departing from the spirit and scope of the present invention.

Claims

1. A high-voltage driving circuit is characterized by comprising a power supply bias module and a driving circuit module, wherein the power supply bias module comprises a high-voltage PMOS (P1) tube, a high-voltage NMOS (N-channel metal oxide semiconductor) tube N1, a voltage stabilizing tube D1, a voltage stabilizing tube D2, a resistor R1, a resistor R2, a capacitor C1 and a capacitor C1, the resistor R1 is connected with the voltage stabilizing tube D1 in series, the source electrode of the NMOS tube N1 is connected with the capacitor C1 to form VREG, the grid electrode of the NMOS tube N1 is connected with the connection part of the resistor R1 and the voltage stabilizing tube D1, the voltage stabilizing tube D1 is connected with the resistor R1 in series, the source electrode of the high-voltage PMOS tube P1 is connected with the capacitor C1 to form VHS, the connection part of the grid electrode of the high-voltage PMOS tube P1 and the voltage stabilizing tube D1 with the resistor R1, the driving circuit module comprises the high-voltage PMOS tube N1, the high-voltage NMOS tube N1, the high-voltage PMOS tube P1, the high-voltage PMOS 72, the high-voltage PMOS-P1, the high-voltage PMOS-P1, the high-voltage PMOS-P1, the high-voltage PMOS-P1, the high-P1 and the high-P1, An inverter X2, an inverter X3, an inverter X4, an inverter X5, an inverter X6, a nor gate X7, a nand gate X8, a resistor R3, a resistor R4 and a resistor R5, wherein an input terminal of the inverter X5 is connected to an input signal of the driving circuit, an output terminal of the inverter X5 is connected to a gate of a high-voltage NMOS transistor N5 and a second input terminal of the nand gate X5, a drain of the high-voltage NMOS transistor N5 is connected to a drain of the high-voltage PMOS transistor P5, a source of the high-voltage PMOS transistor P5 is connected to one terminal of the resistor R5 and an input terminal of the inverter X5, the other terminal of the resistor R5 is connected to a power supply VDD, an output terminal of the inverter X5 is connected to a first input terminal of the nor gate X5, an output terminal of the inverter X5 is connected to one terminal of the resistor R5, and an input terminal of the nor gate X5 is connected to the output terminal of the nor gate X5, the output end of the inverter X3 is sequentially connected with the gates of a high-voltage PMOS tube P2 and a high-voltage PMOS tube P3, the sources of the high-voltage PMOS tube P2 and the high-voltage PMOS tube P3 are connected with a power supply VDD, the drain of the high-voltage PMOS tube P3 is connected with the drain of a high-voltage NMOS tube N4, the source of the high-voltage NMOS tube N4 is connected with one end of a resistor R5 and the input end of an inverter X5, the other end of the resistor R5 is grounded, the output end of the inverter X5 is connected with the first input end of a NAND gate X8, the output end of the NAND gate X8 is connected with the input end of the inverter X6, the output end of the inverter X6 is sequentially connected with the gates of a high-voltage NMOS tube N2 and a high-voltage NMOS tube N3, the source of the high-voltage NMOS tube N3 and the source of the high-voltage NMOS tube N2 are respectively grounded, the drain of the high-voltage PMOS tube P4 is connected with the drain of the high-voltage NMOS tube N3, and the drain of the high-voltage PMOS tube N2 is connected with the drain of the high-voltage PMOS tube P2 and the output end of the high-voltage drive circuit.

2. The high voltage driving circuit as claimed in claim 1, wherein the high voltage NMOS transistor N2 and the high voltage PMOS transistor P2 are power driving output transistors.

3. The high voltage driving circuit as claimed in claim 1, wherein the inverter X1, the inverter X2, the inverter X3 and the nor gate X7 operate in a voltage domain between VDD and VHS.

4. The high voltage driving circuit as claimed in claim 1, wherein the inverter X4, the inverter X5, the inverter X6 and the nand gate X8 operate in a voltage domain between VREG and ground.

5. The high voltage driving circuit as claimed in claim 3, wherein the signal high level is a VDD voltage, the signal low level is a VHS voltage, and a relative voltage difference between the VDD voltage and the VHS voltage is 5V.

6. The high voltage driving circuit as claimed in claim 4, wherein the signal high level is VREG voltage, the signal low level is ground, and the difference between VREG voltage and ground is 5V.

7. The high voltage driving circuit as claimed in claim 1, wherein the turn-on threshold of the high voltage PMOS transistor P1 and the turn-on threshold of the high voltage NMOS transistor N1 are both 1.5V, and the regulated voltage values of the voltage regulator D1 and the voltage regulator D2 are 6.5V.