WO2014007006A1

WO2014007006A1 - Delay circuit and semiconductor apparatus

Info

Publication number: WO2014007006A1
Application number: PCT/JP2013/065120
Authority: WO
Inventors: Junichi Kanno; Kuniaki Arai
Original assignee: Ricoh Company, Ltd.
Priority date: 2012-07-02
Filing date: 2013-05-24
Publication date: 2014-01-09
Also published as: JP2014011733A

Abstract

A delay circuit and a semiconductor apparatus which includes the delay circuit are provided. An output control circuit controls an output signal level from an output terminal to a High level or a Low level or controls the output terminal such that it is brought into a High impedance state. A delay time setting circuit discharges a capacitance in response to a control signal from a logical operation circuit and generates a delay time setting signal based on a voltage across the capacitance. The logical operation circuit controls the output control circuit such that the output terminal is brought into the High impedance state in response to a detection signal and outputs the control signal to the delay time setting circuit, and controls the output control circuit such that a Low level output signal is output in response to the delay time setting signal.

Description

DESCRIPTION

TITLE OF THE INVENTION

DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS

TECHNICAL FIELD

The present invention relates to a delay circuit for a semiconductor apparatus such as a semiconductor apparatus for secondary cell protection and a semiconductor apparatus for voltage detection, etc. , and a semiconductor apparatus which includes the delay circuit .

BACKGROUND ART

A semiconductor apparatus for secondary cell protection that is disclosed in Non-patent documents 1 and 2, for example, detects an abnormal state such as an excess current state, an over-charge state, or an over-discharge state of a secondary cell and outputs a detection signal which indicates detected results when the abnormal state has continued for a predetermined detection delay time. Moreover, a semiconductor apparatus for voltage detection that is disclosed in Non-patent documents 3 and 4 outputs a detection signal which indicates detection results when an input voltage being greater than or equal to a predetermined first threshold voltage is detected for a predetermined detection delay time and the input voltage being less than or equal to a predetermined second threshold voltage which is lower than the first threshold voltage is detected for the above-described predetermined detection delay time. Here, a user may freely set the above-described detection delay time in accordance with a capacitance value of a capacitance which is attached to the semiconductor apparatus.

The respective semiconductor apparatuses disclosed in Non-patent documents 1 to 4 include a terminal for connecting a capacitance for setting a detection delay time. Therefore, there is a problem that a package which has been used may have to be changed to a package with a large number of terminals and a large mounted area when a function of setting the detection delay time using the attached capacitance is added to a semiconductor apparatus which does not have the above-described function. For example, if a 6-terminal semiconductor apparatus uses a 6-terminal package, a necessity arises of changing to a larger sized package as adding the above-described function leads to a 7-terminal semiconductor apparatus. This is not preferable for a semiconductor apparatus to be used in an application in which a reduced component size is called for, such as a portable-type electrical equipment unit .

SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEMS

An object of the present invention is to solve the above-described problems and relates to a delay circuit which makes it possible to add a function of setting a detection delay time with an attached capacitance without increasing the number of terminals; and a semiconductor apparatus which includes the delay circuit.

According to the present invention, a delay circuit is provided which delays an input first detection signal by a predetermined detection delay time and outputs the delayed first detection signal inverted or non-inverted from a first output terminal as a first output signal, wherein

the detection delay time is set based on a first capacitance which is provided outside the delay circuit and which is connected between the first output terminal and a ground terminal; and wherein

the delay circuit generates a delay time setting signal indicating that the detection delay time has elapsed based on a voltage across the first capacitance in response to the first detection signal, and generates the first output signal to output the generated first output signal at generated timing of the delay time setting signal .

According to the delay circuit and the semiconductor apparatus of the present invention, the detection delay time is set based on a first capacitance which is provided outside the delay circuit and which is connected between the first output terminal and a ground terminal; and the delay circuit generates a delay time setting signal indicating that the detection delay time has elapsed based on a voltage across the first capacitance in response to the first detection signal, and generates the first^■ output signal to output the generated first output signal at generated timing of the delay time setting signal, making it possible to add a function of setting a detection delay time with an attached capacitance without increasing the number of terminals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a configuration of a semiconductor apparatus 100 according to a first embodiment of the present invention;

FIG. 2 is a timing chart illustrating an operation of the semiconductor apparatus 100 in FIG. 1;

FIG. 3 is a circuit diagram illustrating a configuration of a semiconductor apparatus 200 according to a second embodiment of the present invention;

FIG. 4A is a timing chart illustrating an operation of the semiconductor apparatus 200 in FIG. 3 when a voltage level of a detection signal Detl changes from a Low level to a High level;

FIG. 4B is a timing chart illustrating an operation of the semiconductor apparatus 200 in FIG. 3 when a voltage level of a detection signal Det2 changes from a Low level to a High level;

/

FIG. 5 is a circuit diagram illustrating a configuration of a semiconductor apparatus 300 according to a third embodiment of the present invention;

FIG. 6 is a timing chart illustrating an operation of the semiconductor apparatus 300 in FIG. 5;

FIG. 7 is a circuit diagram illustrating a configuration of a semiconductor apparatus 400 according to a fourth embodiment of the present invention;

FIG. 8 is a timing chart illustrating an operation of the semiconductor apparatus 400 in FIG. 5;

FIG. 9 is a circuit diagram illustrating a configuration of a semiconductor apparatus 100A according to a fifth embodiment of the present invention;

FIG. 10 is a circuit diagram illustrating a configuration of a delay time setting circuit 210A according to a sixth embodiment of the present invention; FIG. 11 is a block diagram illustrating a configuration of a battery pack which includes a semiconductor apparatus for secondary cell protection 500 according to a seventh embodiment of the present invention; and

FIG. 12 is a block diagram illustrating a configuration of a semiconductor apparatus for voltage detection 600 according to an eighth embodiment of the present invention.

MODE FOR CARRYING OUT THE INVENTION

A description is given below with regard to embodiments of the present invention with reference to the drawings. In the respective embodiments below, the same letter is given for the same elements. Moreover, in the respective circuit and block diagrams in FIGS. 1, 3, 5, 7, and 9 to 12 below, description of circuits which are not related to a delay circuit, a secondary cell protection circuit, a voltage detection circuit, and a semiconductor apparatus is omitted.

First Embodiment

FIG. 1 is a circuit diagram illustrating a configuration of a semiconductor apparatus 100 according to a first embodiment of the present invention, while FIG. 2 is a timing chart illustrating an operation of the semiconductor apparatus 100 in FIG. 1. In FIG. 1, the semiconductor apparatus 100 is, for example, a semiconductor apparatus for secondary cell protection or a semiconductor apparatus for voltage detection and is configured to include a delay circuit 101; a power supply terminal VDD, an output terminal OUT, and a ground terminal VSS. When the semiconductor apparatus 100 is the semiconductor apparatus for secondary cell protection, the semiconductor apparatus is configured to include a current monitoring circuit (not shown) which detects a current flowing in a secondary cell and outputs a High level detection signal Detl to a delay circuit 101 when a current value of a current detected is greater than or egual to a predetermined first threshold value, or less than or equal to a predetermined second threshold value which is lower than the first threshold value. Moreover, when the semiconductor apparatus 100 is the semiconductor apparatus for voltage detection, the semiconductor apparatus is configured to include a voltage detection circuit (not shown) which detects a voltage input and outputs a High level detection signal Det to the delay circuit 101 when a voltage value of the detected voltage is greater than or equal to a predetermined threshold value .

As described below in detail, the delay circuit 101 according to the present embodiment is the delay circuit 101 which delays, by a predetermined detection delay time D, and inverts an input detection signal Det to output, from an output terminal OUT as an output signal, the delayed and inverted detection signal Det, wherein the detection delay time D is set based on a capacitance 1 provided outside the delay circuit 101 and connected between the output terminal OUT and the ground terminal VSS, and wherein the delay circuit 101 generates a delay time setting signal DLY which indicates that the detection delay time D has elapsed based on a voltage across the capacitance 1 in response to the detection signal Det and generates an output signal to output the generated output signal at a generated timing of the delay time setting signal DLY.

Moreover, the delay circuit 101 includes:

(a) an output control circuit 120 which controls an output signal level to a High level or a Low level to output the output signal level from the output terminal OUT or control the output terminal OUT such that it is brought to a High impedance state;

(b) a delay time setting circuit 110 which discharges the capacitance 1 in response to an input control signal CntS and generates the delay time setting signal DLY based on the voltage across the capacitance 1; and (c) a logical operation circuit 130 which controls the output control circuit 120 such that the output terminal OUT is brought to the High impedance state in response to the detection signal Det, outputs a control signal CntS to the delay time setting circuit 110, and controls the output control circuit 120 such that a Low level output signal is output from the output terminal OUT in response to the delay time setting signal DLY.

Furthermore, the delay time setting circuit 110 compares a voltage across the capacitance 1 with a predetermined threshold voltage VI corresponding to the detection delay time D and generates the delay time setting signal DLY when the voltage across the capacitance 1 reached the threshold voltage VI . Furthermore, the delay time setting circuit 110 includes a constant current source 114 which generates a predetermined constant current to discharge the capacitance 1 by the constant current.

In FIG. 1, the delay circuit 101 is configured to include the logical operation circuit 130; the delay time setting circuit 110; and the output control circuit 120. Moreover, the delay time setting circuit 110 is configured to include a reference voltage source 111 which generates a reference voltage having a predetermined reference voltage value Vref; a comparison circuit (comparator) 112; an N-channel type MOS field effect transistor (below called an NMOS transistor) 113; and the constant current source 114 which generates a reference current having a predetermined reference current value Iref. Moreover, the output control circuit 120 is configured to include a P-channel type MOS field effect transistor (below called a PMOS transistor) 121; an NMOS transistor 122; and inverters 123-126. Furthermore, the capacitance 1 of a capacitor which has a capacitance value Cdly is connected to the outside of the semiconductor apparatus 100 between the output terminal OUT and the ground terminal VSS.

Here, as described in detail below, the logical operation circuit 130 generates control signals CntS, CntP, and CntN based- on the delay time ^{^}setting signal DLY from the delay time setting circuit 110 and the input detection signal Det. Moreover, the logical operation circuit 130 outputs the control signal CntS to a gate of the NMOS transistor 113; outputs the control signal CntP to a gate of the PMOS transistor 121 via the inverters 123 and 124; and outputs the control signal CntN to a gate of the NMOS transistor 122 via the inverters 125 and 126.

Furthermore, a non-inverting input terminal of the comparison circuit 112 is connected to the power supply terminal VDD via the reference voltage source 111. On the other hand, an inverting input terminal of the comparison circuit 112 is grounded via the NMOS transistor 113 and the constant current source 114 and connected to the output terminal OUT. Moreover, the NMOS transistor 113 is turned on and off in response to the control signal CntS from the logical operation circuit 130. When a voltage level of an output signal from the output terminal OUT is higher than a threshold voltage VI (see FIG. 2) which is lower than a voltage level of the power supply terminal VDD (also called a power supply voltage) by a reference voltage value Vref, the comparison circuit 112 generates a low-level delay time setting signal DLY to output the generated results to the Logical operation circuit 130. On the other hand, when the voltage level of the output signal from the output terminal OUT is lower than or equal to the threshold voltage VI (see FIG. 2) , it outputs a High level delay time setting signal DLY to output the generated results to the logical operation circuit 130.

Furthermore, the PMOS transistor 121 and the NMOS transistor 122 are serially connected between the power supply terminal VDD and the ground terminal VSS via a connection point which is connected to the output terminal OUT. The control signal CntP from the logical operation circuit 130 is output to a gate of the PMOS transistor via the inverters 123 and 124 which make a driving circuit, while the control signal CntN is output to a gate of the NMOS transistor 122 via the inverters 125 and 126 which make up a driving circuit. Here, the PMOS transistor 121 and the NMOS transistor 122 are turned on and off in a mutually independent manner. Therefore, the output control circuit 120 is a tri-state output circuit. More specifically, in accordance with the control signals CntP and CntN, the output control circuit 120 controls an output signal level from the output terminal OUT to a High level or a Low level, or controls the output terminal OUT such that it is brought into a High impedance state.

An operation of the semiconductor apparatus 100 which is configured as described above is explained with reference to FIG. 2. In timing charts of a voltage level, of the output terminal OU in FIG. 2 and the below-described FIGS. 4A, 4B, 6, and 8, a voltage level of the power supply terminal VDD (a power supply voltage level) is denoted as VDD and a voltage level of the ground terminal VSS is denoted as VSS.

In FIG.2, when a voltage level of the detection signal Det is a Low level, the logical operation circuit 130 generates Low level control signals CntS, CntP, and CntN. In response thereto, the NMOS transistors 113 and 122 are turned off, while the PMOS transistor 121 is turned on. Therefore, the output control circuit 120 outputs an output signal of a High level (the power supply voltage level) via the output terminal OUT. Moreover, the capacitance 1 is connected to the power supply terminal VDD via the output terminal OUT and the PMOS transistor 121 and charged.

At timing Tl, when a voltage level of the detection signal Det is inverted from the Low level to the High level, the logical operation circuit 103, in response thereto, inverts the respective voltage levels of the control signals CntP and CntS from the Low level to the High level. In response thereto, the PMOS transistor 121 is turned off. As a result, the PMOS transistor 121 and the NMOS transistor 122 are both turned off, so that the output terminal OUT is brought into the High impedance state. However, as the capacitance 1 is connected between the output terminal OUT and the ground terminal VSS, the voltage level of the output terminal OUT does not become floating, so that the power supply voltage level is maintained .

On the other hand, at the timing Tl, the NMOS transistor 113 is turned on in response to the High level control signal CntS. Therefore, the constant current source 114 is connected to the output terminal OUT, the capacitance 1 is discharged by the reference current from the constant current source 114, and the voltage across the capacitance 1 (in other words, a voltage level of an output signal from the output terminal OUT) gradually decreases. When the voltage level of the output signal from the output terminal OUT becomes less than or equal to the threshold voltage VI at timing T2, a voltage level of the delay time setting signal DLY from the comparison circuit 112 is inverted from a Low level to a High level . In response thereto, the logical operation circuit 130 inverts a voltage level of the control signal CntN from a Low level to a High level and turns on the NMOS transistor 122 of the output control circuit 120. Therefore, the capacitance 1 is substantially discharged at the timing T2 via the NMOS transistor 122, so that a Low level output signal is output via the output terminal OUT from the output control circuit

120.

Therefore, when the voltage level of the detection signal Det is inverted from the Low level to the High level at the timing Tl, the voltage level of the output signal from the output terminal OUT changes to the Low level at the timing T2, which is after the timing Tl. Now, assuming a time difference between the timing Tl and the timing T2 as a detection delay time D, the detection delay time D Is calculated in accordance with the following Equation (1) :

Cdl Vref

D = (1)

Iref As evident from Equation (1), the capacitance value Cdly of the capacitance 1 connected between the output terminal OUT and the ground terminal VSS may be changed to freely set the detection delay time D. In other words, the present embodiment is arranged to include not only a function of outputting a signal to the output terminal OUT, but also to be able to set the detection delay time D by the attached capacitance 1 connected to the output terminal OUT. Therefore, the present embodiment may add the function of setting the detection delay time D with the attached capacitance 1 without increasing the number of terminals of the semiconductor apparatus.

In the semiconductor apparatus 100, a voltage level of the output terminal OUT which outputs a High level or Low level output signal is guaranteed at a time of outputting a High level output and at a time of outputting a Low level output in the specification. For example, in the specification, it is specified that a minimum value of a voltage level of the output signal at a time of outputting the High level output signal is 0.8 x a voltage level of the power supply terminal VDD and that a maximum value of the voltage level of the output signal at a time of outputting the Low level output signal is 0.5V + a voltage level of the ground terminal VSS. Therefore, in the present embodiment, the reference voltage value Vref is set such that the threshold voltage VI becomes at least a minimum value of a voltage level of the High level output signal.

Moreover, while the delay circuit 101 delays and inverts the input detection signal Det by a predetermined detection delay time D and outputs the delayed and inverted results as an output signal from the output terminal OUT in the present embodiment, the present invention is not limited thereto. The delay circuit 101 may delay, but not invert the input detection signal Det by the predetermined detection delay time D and output the delayed results as the output signal from the output terminal OUT. In this case, in lieu of the delay time setting circuit 110, for example, a delay time setting circuit 210 in FIG. 3 (described in detail in a second embodiment) may be used.

Second embodiment

FIG. 3 is a circuit diagram illustrating a configuration of a semiconductor apparatus 200 according to a second embodiment of the present invention. Moreover, FIG. 4A is a timing chart showing an operation of the semiconductor apparatus 200 in FIG. 3 when the voltage level of a detection signal Detl changes from a Low level to a High level, while FIG. 4B is a timing chart showing an operation of the semiconductor apparatus 200 in FIG. 3 when the voltage level of a detection signal Det2 changes from a Low level to a High level. In FIG. 3, the semiconductor apparatus 200 is, for example, a semiconductor apparatus for secondary cell protection or a semiconductor apparatus for voltage detection and is configured to include a delay circuit 201; a power supply terminal VDD, output terminals OUT1 and OUT2, and a ground terminal VSS.

When the semiconductor apparatus 200 is a semiconductor apparatus for secondary cell protection, the semiconductor apparatus is configured to include a current monitoring circuit (not shown) which detects a current flowing in a secondary cell and outputs a High level detection signal Detl to the delay circuit 201 when a current value of a current detected is greater than or equal to a predetermined first threshold value, or less than or equal to a predetermined second threshold value which is lower than the first threshold value; and a cell voltage monitoring circuit (not shown) which detects a voltage of the secondary cell and outputs a High level detection signal Det2 to the delay circuit 201 when a voltage value of a voltage detected is greater than or equal to a predetermined third threshold value, or less than or equal to a predetermined fourth threshold value which is lower than the third threshold value. Moreover, when the semiconductor apparatus 200 is a semiconductor apparatus for voltage detection, the semiconductor apparatus is configured to include a voltage detecting circuit (not shown) which detects an input voltage and outputs a High level detection signal Detl to the delay circuit 201 when a voltage value of a voltage detected is greater than or equal to a predetermined first threshold value and outputs a High level detection signal Det2 to the delay circuit 201 when the voltage detected is less than or equal to a predetermined second threshold value which is lower than the first threshold value.

As described in detail below, the delay circuit 201 according to the present embodiment includes:

(a) an output control circuit 120 which controls a first output signal, level from an output terminal OUT1 to a predetermined High level or a Low level to output an output signal from the output terminal OUT1 or control the output terminal OUT1 such that it is brought into a High impedance state;

(b) a delay time setting circuit 210 which discharges a capacitance 1 in response to an input control signal CntS and generates a delay time setting signal DLY based on a voltage across the capacitance 1; and

(c) a logical operation circuit 240 which controls the output control circuit 120 such that the output terminal OUTl is brought into the High impedance state in response to the detection signal Detl, outputs the control signal CntS to the delay time setting circuit 210, and controls the output control circuit 120 such that a High level first output signal is output from the output terminal OUTl in response to the delay time setting signal DLY.

Moreover, the delay circuit 201 further includes an output control circuit 230 which controls a second output signal level to a Low level or High level to output the controlled results from an output terminal OUT2; and the logical operation circuit 240 responds to the input detection signal Det2 to control the output control circuit 120 so as to bring the output terminal OUTl into the High impedance state, and to control the output control circuit 230 to output the control signal CntS to the delay time setting circuit 210 , and respond to the delay time setting signal DLY so as to change the second output signal level from the Low level to the High level.

In FIG. 3, the delay circuit 201 is configured to include the logical operation circuit 240; the delay time setting circuit 210; and the output control circuits 120 and 230. Moreover, the delay time setting circuit 210 is configured to include a reference voltage source 111; a comparison circuit 112; a PMOS transistor 212; and a constant current source 114. Moreover, the output control circuit 120 is configured in the same manner as the output control circuit 120 in FIG. 1. In the present embodiment, a connection point between the NMOS transistor 122 and the PMOS transistor 122 of the output control circuit 120 is connected to the output terminal OUT1. In addition, the output control circuit 230 is configured to include a PMOS transistor 231; an NMOS transistor 232; and inverters 233 and 234.

Here, as described in detail below, the logical operation circuit 240 generates control signals CntS, CntP, CntN, and Cnt2 based on the delay time setting signal DLY from the delay time setting circuit 210 and the input detection signals Detl and Det2. Then, the control signal CntS is output to a gate of the PMOS transistor 212, the control signal CntP is output to a gate of the PMOS transistor 121 via inverters 123 and 124, the control signal CntN is output to a gate of the NMOS transistor 122 via the inverters 125 and 126, and the control signal Cnt2 is output to each gate of the NMOS transistor 232 and the PMOS transistor 231 via inverters 233 and 234.

Moreover, an inverting input terminal of the comparison circuit 112 is grounded via the reference voltage source 111. On the other hand, a non-inverting input terminal of the comparison circuit 112 is connected to the power supply terminal VDD via the PMOS transistor 212 and the constant current source 114 and connected to the output terminal OUTl. Moreover, the PMOS transistor 212 is turned on and off in response to the control signal CntS from the logical operation circuit 240. The comparison circuit 112 generates a Low level delay time setting signal DLY when a voltage level of an output terminal OUTl is lower than a threshold voltage V2 (see FIGS. 4A and 4B) which is higher than a ground potential by a reference voltage value Vref, while it generates a High level delay time setting signal DLY when a voltage level of the output terminal OUTl is at least a threshold voltage V2.

Moreover, the PMOS transistor 231 and the NMOS transistor 232 are serially connected between the power supply terminal VDD and the ground terminal VSS via a connection point which is connected to the output terminal OUT2. Here, a control signal Cnt2 from the logical operation circuit 240 is output to each gate of the NMOS transistor 232 and the PMOS transistor 231 via the inverters 233 and 234 which make up a driving circuit. The output control circuit 230 is a bi-state output circuit. More specifically, in accordance with the control signal Cnt2, the output control circuit 230 outputs a High level or low level output signal from the output terminal OUT2.

An operation of the semiconductor apparatus 200 which is configured as described above is explained with reference to FIGS. 4A and 4B.

In FIGS. 4A and 4B, when each voltage level of the detection signals Detl and Det2 is a Low level, the logical operation circuit 240 generates a Low level control signal CntS and High level control signals CntP, CntN, and Cnt2. In response thereto, the NMOS transistors 122 and 232 are turned on, while the PMOS transistors 121 and 231 are turned off. Moreover, the PMOS transistor 212 is turned off. Therefore, the output control circuit 120 outputs a Low level output signal from the output terminal OUTl. Moreover, the output control circuit 230 outputs a Low level output signal from the output terminal OUT2.

Next, a voltage level of the detection signal Detl is inverted from a Low level to a High level at timing Tl. in FIG. 4A, or a voltage level of the detection signal Det2 is inverted from a Low level to a High level at the timing Tl in FIG. 4B. In response thereto, the logical operation' circuit 240 inverts a voltage level of the control signal CntS from a Low level to a High level and inverts a voltage level of the control signal CntN from a High level to a Low level. In response thereto, the NMOS transistor 122 is turned off. As a result, both the PMOS transistor 121 and the NMOS transistor 122 are brought into a turned off state, and the output terminal OUTl is brought into a High impedance state. However, as the capacitance 1 is connected between the output terminal OUT1 and the ground terminal VSS, the voltage level of the output terminal OUT does not become floating, so that a ground potential, which is a Low level, is maintained.

On the other hand, at the timing Tl, the PMOS transistor 212 is turned on in response to the High level control signal CntS. Therefore, the constant current source 114 is connected to the output terminal OUT1, the capacitance 1 is charged by the reference current from the constant current source 114, and a voltage across the capacitance 1 (in other words, a voltage level of the output terminal OUT1) gradually rises. Then, when the voltage level of the output terminal OUT1 becomes greater than or equal to the threshold voltage V2 at the timing T2, a voltage level of the delay time setting signal DLY from the comparison circuit 112 is inverted from a Low level to a High level.

When the logical operation circuit 230 detects that a voltage level of the delay time setting signal DLY has inverted from a Low level to a High level, the control signals CntP, CntN, and Cnt2 for controlling the output control circuits 120 and 230 are generated in response to each voltage level of the detection signals Detl and Det2 at the time of detection.

More specifically, as shown in FIG. 4A, when a voltage level of the detection signal Detl at the timing T2 is at a High level (or, in other words, when a voltage level of the detection signal Detl is inverted from a Low level to a High level at the timing Tl) , the logical operation inverts a voltage level of the control signal CntP from a High level to a Low level and the PMOS transistor 121 of the output control circuit 120 is turned on. Therefore, the capacitance 1 is substantially charged at the timing T2 via the PMOS transistor 121 and a High level output signal is output via the output terminal OUTl from the output control circuit 120.

Moreover, as shown in FIG. 4B, when a voltage level of the detection signal Det2 at the timing T2 is at a High level (or, in other words, when a voltage level of the detection signal Det2 is inverted from a Low level to a High level at a timing Tl) , the logical operation circuit 230 inverts a voltage level of the control signal CntN from a Low level to a High level and inverts a voltage level of the control signal Cnt2 from a High level to a Low level . When a voltage level of the control signal CntN becomes a High level, the NMOS transistor 122 of the output control circuit 120 is turned on, the capacitance 1 is substantially discharged at the timing T2 via the NMOS transistor 121, and the output control circuit 120 outputs a Low level output signal from the output terminal OUTl. Moreover, when the voltage level of the control signal Cnt2 becomes a Low level, the output control circuit 230 outputs a High level output signal from the output terminal OUT2.

Therefore, when a voltage level of the detection signal Detl is inverted from a Low level to a High level at the timing Tl (FIG. 4A) , a voltage level of an output signal from the output terminal OUT1 changes to the High level at the timing T2, which is after the timing Tl. Moreover, when a voltage level of the detection signal Det2 is inverted from a Low level to a High level at the timing Tl (FIG. 4B) , a voltage level of the output terminal OUT2 changes to the High level at the timing T2, which is after the timing Tl. Now, assuming a time difference between the timing Tl and the timing T2 of a detection delay time D, the detection delay time D is calculated in accordance with Equation (1) as in the first embodiment.

Therefore, the capacitance value Cdly of the capacitance 1 connected between the output terminal OUT1 and the ground terminal VSS may be changed to freely set the detection delay time D. In other words, the present embodiment is arranged to include not only a function of outputting a signal to the output terminal OUT1, but also a function of allowing to set the detection delay time D by the attached capacitance 1 connected to the output terminal OUT. Therefore, the present embodiment may add a function of setting, in the semiconductor apparatus, the detection delay time D with the attached capacitance 1 without increasing the number of terminals of the semiconductor apparatus .

While a common detection delay time D is set for the detection signals Detl and Det2 in the present embodiment, the present invention is not limited thereto. In accordance with which of the detection signals Detl and Det2 for which a voltage level has been inverted at the timing Tl in FIGS. 4A and 4B, at least one of the reference voltage value Vref and the reference current value Iref may be changed to set a different detection delay time for the detection signals Detl and Det2.

Moreover, in the present embodiment, the output control circuit 120, the delay time setting circuit 210, and the capacitance 1 are connected to the output terminal OUT1 to provide the output terminal OUT1 with not only a function of outputting a signal, but also a function of allowing to set the detection delay time D of the detection signals Detl and Det2 with an attached capacitance 1 which is connected to the output terminal 0UT1. However, the present invention is not limited thereto, so that the output terminal 0UT2 may also be connected to an output control circuit which is similar to the output control circuit 120, a delay time setting circuit which is similar to the delay time setting circuit 210, and a capacitance 1 to set a detection delay time of the detection signal Det2 independent of a detection delay time D of the detection signal Detl.

Furthermore, in the semiconductor apparatus

200, each voltage level of the output terminals OUTl and OUT2 which output a High level or a Low level output signal is guaranteed at a time of outputting a High level output and at a time of outputting a Low level output in the specification. For example, in the specification, it is specified that a minimum value of a voltage level of the output signal at a time of outputting a High level output signal is 0.8 x a voltage level of the power supply terminal VDD and that a maximum value of a voltage level of the output signal at a time of outputting a Low level output signal is 0.5V + a voltage level of the ground terminal VSS. Therefore, in the present embodiment, ^■ the reference voltage value Vref is set such that the threshold voltage V2 becomes less than or egual to a maximum value of a voltage level of the Low level output signal.

Third embodiment

FIG. 5 is a circuit diagram illustrating a configuration of a semiconductor apparatus 300 according to a third embodiment of the present invention, while FIG. 6 is a timing chart illustrating an operation of the semiconductor apparatus 300 in FIG. 5. Compared to the semiconductor apparatus 100 according to the first embodiment, the semiconductor apparatus 300 according to the present embodiment differs in having a delay circuit 301 in lieu of the delay circuit 101. Below, only differences from the first embodiment will be described.

In FIG. 5, the delay circuit 301 is configured to include a logical operation circuit 330; a delay time setting circuit 310; and an output control circuit 120. Here, the output control circuit 120 in FIG. 5 is similarly configured to the output control circuit 120 in FIG, 1, so that explanations will be omitted.

As described in detail below, the delay time setting circuit 310 includes:

(a) an oscillating circuit 301 which generates a clock CLK which has a predetermined period Tc which is set by the capacitance 1 in response to the control signal CntS; and (b) a counter circuit 360 which counts a clock CLK and which generates a delay time setting signal DLY when a count number of the clock CLK reached the predetermined number of threshold times Count which corresponds to the detection delay time D.

The delay time setting circuit 310 is configured to include an oscillating circuit 350 and a counter circuit 360. Moreover, the oscillating circuit 350 is configured to include a constant current source 351 which generates a reference current having a predetermined reference current value It; a PMOS transistor 352; a NMOS transistor 353; a reference voltage source 354 which generates a reference voltage having a predetermined reference voltage value Vt; a comparison circuit 355; a NAND gate 356; an OR gate 357; and a NOT gate 358. Furthermore, the counter circuit 360 is configured to include T flip flops 361-364 and an AND gate 365.

In the oscillating circuit 350, the constant current source 351 is connected to the voltage supply terminal VDD. Moreover, the PMOS transistor 352 and the NMOS transistor 353 are serially connected between the constant current source 351 and the ground terminal VSS via a connection point which is connected to the output terminal OUT. The control signal CntS from the logical operation circuit 330 is output to a first input terminal of the NAND gate 356 and an output signal from the OR gate 357 is output to a second input terminal of the NAND gate 356. Then, an output signal from the NAND gate 356 is output to each gate of the PMOS transistor 352 and the NMOS transistor 353. Moreover, a non-inverting input terminal of the comparison circuit 355 is connected to the output terminal OUT, while the inverting input terminal is connected to the ground terminal VSS via the reference voltage source 354. The comparison circuit 355 generates a Low level clock 355 when a voltage level of the output terminal OUT is lower than a threshold voltage V3 (see FIG. 6) which is higher than a ground potential by a reference voltage value Vt, while it generates a High level output signal when a voltage level of the output terminal OUT is greater than or equal to the threshold voltage V3. An output signal from the comparison circuit 355 is output to the first input terminal of the OR gate 357 via the NOT gate 358 as a clock CLK and also output to the T flip flop of the counter circuit 360.

Moreover, in the counter circuit 360, the T flip flops 361-364 are mutually connected in a serial manner. Output signals from the T flip flops 362 and 364 are output to the AND gate 365 and an output signal from the AND gate 365 is output to the second input terminal of the OR gate 357 and the logical operation circuit 330 as a delay time setting signal DLY.

The counter circuit 360 counts the clock CLK from the oscillating circuit 350 and inverts a voltage level of the delay time setting signal DLY from a Low level to a High level when the number of counts of the clock CLY reached the predetermined times of thresholds Count . While the counter circuit 360 includes four of the T flip flops 361 to 364 in FIG. 5, it is not limited thereto in the present invention, so that an arbitrary number of serially connected T flip flops may be included.

An operation of the semiconductor apparatus 300 which is configured as described above is explained with reference to FIG. 6. In FIG. 6, when a voltage level of the detection signal Det is a Low level, the logical operation circuit 330 generates a Low level control signal CntS, and High level control signals CntP and CntN. In response thereto, the NMOS transistor 122 is turned on, while the PMOS transistor 121 is turned off. Therefore, the output control circuit 120 outputs a Low level output signal from the output terminal OUT. Moreover, a voltage level of an output terminal OUT is a Low level, so that a voltage level of the clock CLK is brought to a Low level.

Next, at a timing Tl in FIG. 6, when a voltage level of the detection signal Detl is inverted from a Low level to a High level, in response thereto, the logical operation circuit 330 inverts a voltage level of the control signal CntS from a Low level to a High level and inverts a voltage level of the control signal CntN from a High level to a Low level. In response thereto, the NMOS transistor 122 is turned off. As a result, the PMOS transistor 121 and the NMOS transistor 122 are both turned off, so that the output terminal OUT is brought into a High impedance state. However, as the capacitance 1 is connected between the output terminal OUT and the ground terminal VSS, the voltage level of the output terminal OUT does not become floating, so that a ground potential, which is a Low level, is maintained.

Moreover, when a voltage level of the control signal CntS becomes a High level at the timing Tl, the PMOS transistor 352 is turned on and the NMOS transistor 353 is turned off. Therefore, the constant current source 351 is connected via the PMOS transistor 352 to the output terminal OUT. In this way, the capacitance 1 is charged by a reference current from the constant current source 351, and a voltage across the capacitance 1 (or in other words, a voltage level of an output signal from the output terminal OUT) gradually rises. When the voltage level of the output terminal OUT becomes greater than or equal to the threshold voltage V3 at the timing T3, a voltage level of the clock CLK from the comparison^' circuit 355 is inverted from a Low level to a High level. In response thereto, a High level output signal is output from the NAND gate 356, so that the PMOS transistor 352 is turned off and the NMOS transistor 353 is turned on. Therefore, the capacitance 1 is discharged via the NMOS transistor 353 and a voltage level of the output terminal OUT decreases to a ground potential.

A voltage level of the clock CLK turns to a Low level with a decrease in the voltage level of the output terminal OUT and a Low level output signal is output from the NAND gate 356, so that the PMOS transistor 352 is turned on and the NMOS transistor 353 is turned off. Therefore, the capacitance 1 is again charged by a reference current from the constant current source 351, and a voltage across the capacitance 1 (or in other words, a voltage level of an output signal from the output terminal OUT) gradually rises again. During a period in which a voltage level of the control signal CntS is a High level and a voltage level of the delay time setting signal DLY from the counter circuit 360 is a Low level, the above-described operation is repeated to generate a clock at a period Tc below.

_{Tc =} C¾ Vt

It '

Upon the AND gate 365 counting the clock CLK from the oscillating circuit 310 and the clock CLK being counted by the predetermined number of threshold times Count, the counter circuit 360 inverts a voltage level of the delay time setting signal DLY from a Low level to a High level (a timing T2 in FIG. 6) . In response thereto, the logical operation circuit 330 inverts a voltage level of the control signal CntP from a High level to a Low level. Therefore, the capacitance 1 is substantially charged at a timing T2 via the PMOS transistor 121 and the output control circuit 120 outputs a High level output signal from the output terminal OUT.

Therefore, when a voltage level of the detection signal Det is inverted from a Low level to a High level at the timing Tl, a voltage level of an output signal from the output terminal OUT changes to the High level at the timing T2, which is after the timing Tl. Now, assuming a time difference between the timing Tl and the timing T2 of a detection delay time D, the detection delay time D is calculated in accordance with a following equation: D=TexCount (3)

As described above, a period Tc is expressed in Equation (2), so that a capacitance value Cdly of the capacitance 1 which is connected between the output terminal OUT and the ground terminal VSS may be changed to change the period Tc and freely set the detection delay time D. In other words, it is arranged to include not only a function of outputting a signal to the output terminal OUT, but also to allow setting the detection delay time D by the attached capacitance 1 connected to the output terminal OUT. Therefore, the present embodiment may add, in the semiconductor apparatus, a function of setting the detection delay time D with the attached capacitance 1 without increasing the number of terminals of the semiconductor apparatus. A configuration of the oscillating circuit 350 is not limited to the configuration shown in FIG. 5, so that it may be a configuration in which a period Tc can be set with a capacitance value Cldy of the capacitance 1 connected to the output terminal OUT.

Moreover, the delay time setting circuit 210 of the semiconductor apparatus 200 according to the second embodiment may be replaced by the delay time setting circuit 310 according to the present embodiment. In this case, in accordance with which of detection signals Detl and Det2 for which a voltage level has been inverted at the timing Tl in FIGS. 4A and 4B, the number of threshold times Count may be changed to set a different detection delay time for the detection signals Detl and Det2.

Moreover, while the delay circuit 201 is arranged to output a High level output signal from the output terminal OUT2 in response to the High level detection signal Det2 in the present embodiment, the present invention is not limited thereto, so that a Low level output signal may be output from the output terminal OUT2 in response to the High level detection signal Det2. In this case, a voltage level of the control signal Cnt2 may be inverted in a timing chart of the control signal Cnt2 in FIG. 4B.

Furthermore, the counter circuit 360 may use one number of threshold times that is selected from multiple numbers of threshold times . This makes it possible to set multiple detection delay times.

Fourth embodiment

FIG. 7 is a circuit diagram illustrating a configuration of a semiconductor apparatus 400 according to a fourth embodiment of the present invention, while FIG. 8 is a timing chart illustrating an operation of the semiconductor apparatus 400 in FIG. 5. Compared to the semiconductor apparatus 100 according to the first embodiment, the semiconductor apparatus 400 according to the present embodiment differs in having a delay circuit 401 in lieu of the delay circuit 101. Below, only differences from the first embodiment will be described.

As described in detail below, the delay circuit

401 includes:

(a) a depression-type NMOS transistor 122A which is connected to the output terminal OUT;

(b) a comparison circuit 112 which compares a voltage across the capacitance 1 with a predetermined threshold voltage VI corresponding to the detection delay time D and generates the delay time setting signal DLY when the voltage across the capacitance 1 reached the threshold voltage VI; and

(c) a gate control circuit 425 which operates a NMOS transistor 122A as a constant current source which generates a predetermined constant current in response to a detection signal Det to discharge the capacitance 1 by the constant current and which turns on the NMOS transistor 122A in response to the delay time setting signal DLY.

In FIG. 7, the delay circuit 401 is configured to include a PMOS transistor 121, a depression-type NMOS transistor 122A, inverters 123 and 124, a reference voltage "source 111, a comparison circuit 112, and a gate control circuit 425.. The PMOS transistor 121 and the NMOS transistor 122A are serially connected between the power supply terminal VDD and the ground terminal VSS via a connection point which is connected to the output terminal OUT. Moreover, a non-inverting input terminal of the comparison circuit 112 is connected to the power supply terminal VDD via the reference voltage source 111, while an inverting input terminal ^"is connected to the output terminal OUT.

The detection signal Det is output to the gate control circuit 425 and also output to a gate of the PMOS transistor 121 as a control signal CntP via the inverters 123 and 124 which make up a driving circuit. Moreover, when a voltage level of the output terminal OUT is higher than a threshold voltage VI (see FIG. 8) which is lower than a voltage level of the power supply terminal VDD (also called a power supply voltage) by a reference voltage value Vref, the comparison circuit 112 generates a Low level delay time setting signal DLY to output the generated result to the gate control circuit 425. On the other hand, when the voltage level of the output terminal OUT is lower than or equal to the threshold voltage VI, it generates a High level delay time setting signal DLY to output the generated results to the gate control circuit 425. Moreover, as described in detail below, based on the detection signal Det and the delay time setting signal DLY, the gate control circuit 425 generates the control signal CntN to output the generated results to a gate of the NMOS transistor 122A.

An operation of the semiconductor apparatus 400 which is configured as described above is explained with reference to FIG. 8. When a voltage level of the detection signal Det is a Low level, a voltage level of the control signal CntP is also a Low level, so that the PMOS transistor 121 is turned on. Moreover, the gate control circuit 425 responds to a Low level detection signal Det to generate a low level CntN. Therefore, the NMOS transistor 122A is turned off and the capacitance 1 is connected to the power supply terminal VDD via the output terminal OUT and the PMOS transistor 121 and charged. Therefore, a voltage level of an output signal from the output terminal OUT becomes a power supply voltage level (a High level) .

At timing Tl, when a voltage level of the detection signal Det is inverted from a Low level to a High level, the voltage level of the control signal CntP is also inverted from a Low level to a High level in response thereto. Therefore, the PMOS transistor 121 is turned off. On the other hand, in response to a High level detection signal Det, the gate control circuit 425 outputs a predetermined control voltage CntN, which is lower than a threshold voltage Vth of the NMOS transistor 122A to a gate of the NMOS transistor 122A to thereby fix current control to a gate of the NMOS transistor 122A such that a constant current is caused to flow for a drain-to-source current of the NMOS transistor 122A. In this way, the capacitance 1 is discharged by the NMOS transistor 122A, which functions as a constant current source, and a voltage across the capacitance 1 (or in other words, a voltage level of an output signal from the output terminal OUT) gradually drops .

When the voltage level of the output terminal

OUT becomes less than or equal to the threshold voltage VI at the timing T2, a voltage level of the delay time setting signal DLY from the comparison circuit 112 is inverted from a Low level to a High level. In response thereto, the gate control circuit 425 changes a voltage level of the control signal CntN to a High level, which is greater than or equal to a threshold voltage Vth and brings the NMOS transistor 122A into a full-on state. Therefore, the capacitance 1 is substantially discharged at the timing T2 via the NMOS transistor 122A, so that a Low level output signal is output from the output terminal OUT.

Therefore, when a voltage level of the detection signal Det is inverted from a Low level to a High level at the timing Tl, a voltage level of an output signal from the output terminal OUT changes to the Low level at the timing T2, which is after the timing Tl. Now, assuming a time difference between the timing Tl and the timing T2 of a detection delay time D, the detection delay time D is calculated in accordance with equation (1) as in the first embodiment.

Therefore, a capacitance value Cdly of the capacitance 1 connected between the output terminal OUT and the ground terminal VSS may be changed to freely set the detection delay time D. In other words, the present embodiment is arranged to include not only a function of outputting a signal to the output .terminal OUT, but also to allow setting the detection delay time D by the attached capacitance 1 connected to the output terminal OUT. Therefore, the present embodiment may add, in the semiconductor apparatus, a function of setting the delay time D with the attached capacitance 1 without increasing the number of terminals of the semiconductor apparatus.

While the delay circuit 401 delays, by the detection delay time D, and inverts the detection signal Det and outputs the delayed and inverted results as an output signal from the output terminal OUT in the present embodiment, the present invention is not limited thereto. The delay circuit 401 may delay, but not invert the detection signal Det by the detection delay time D and output the delayed results as the output signal from the output terminal OUT. In this case, the PMOS transistor 121 may be replaced with the depression-type PMOS transistor and the gate control circuit 425 may cause the depression-type PMOS transistor to operate as a constant current source which generates a predetermined constant current in response to the detection signal Det to thereby charge the capacitance with the constant current and turn on the depression-type PMOS transistor in response to the delay time setting signal DLY.

Fifth embodiment

FIG. 9 is a circuit diagram illustrating a configuration of a semiconductor apparatus 100A according to a fifth embodiment of the present invention. Compared to the semiconductor apparatus 100 (see FIG. 1) according to the first embodiment, the semiconductor apparatus lOOA according to the present embodiment is configured to include a delay circuit 101A in lieu of the delay circuit 101. Moreover, compared to the delay circuit 101A, the delay circuit 101A is configured to further include the delay circuit 160 and the AND gate 120. The other features are the same as the semiconductor apparatus 100 according to the first embodiment, so that only differences from the first embodiment are explained.

In FIG. 9, after having been delayed by a predetermined minimum delay time Dint by the delay circuit 160, the control signal CntS from the logical operation circuit 130 is output to a first input terminal of an AND gate 161 and a gate of an NMOS transistor 113 as a delay control signal CntD. Moreover, the logical operation circuit 130 outputs a control signal CntP as a second input terminal of the AND gate 161. Furthermore, an output signal from the AND gate 161 is output to a gate of the PMOS transistor 121 via inverters 123 and 124 of the output control circuit 120 (see FIG. 1) .

Thus, according to the present embodiment, after the minimum delay time Dint has elapsed after the detection signal Det changes from a Low level to a High level, the delay control signal CntD and the PMOS transistor 121 are respectively inverted from a Low level to a High level. Therefore, a detection delay time D, which is from when the detection signal Det changes from a Low level to a High level to when a voltage level of an output signal from the output terminal OUT changes from a High level to a Low level, is expressed with the following equation:

_ _Λ Cdly x Vref

D = Dint+ - (4)

Iref

Therefore, even when the capacitance 1 is not connected to the output terminal OUT, the present embodiment may provide, to the detection signal Det, a minimum detection delay time as shown in equation (4).

A circuit configuration of the delay circuit 160 may be an arbitrary configuration which may delay a control signal CntS by a predetermined minimum delay time Dint.

Moreover, in the delay circuits 101 , 201, 201A, 301, and 401 according to the respective embodiments below and the above-described respective embodiments, a delay circuit 160 may further be included which delays the control signal CntS or the detection signals Detl and Det2 by a predetermined minimum delay time Dint.

Sixth embodiment

FIG. 10 is a circuit diagram illustrating a configuration of a delay time setting circuit 210A according to a sixth embodiment of the present invention. Compared to the delay time setting circuit 210 in FIG. 3, the delay time setting circuit 210A according to the present embodiment differs in that it further includes a capacitance 2 of a capacitor which has a capacitance value Cint . Below, only differences from the delay time setting circuit 210 will be described. In FIG. 10, the capacitance 2 is connected between the output terminal OUT1 and the ground terminal VSS . Therefore, in the present embodiment, the detection delay time D is expressed with the following equation:

_{D =} (Cdly + Cint) x Vref

Iref '

The equation (5) may be rewritten as follows:

_^ Cdly xVref CintxVref

D = - +

Iref Iref

Therefore, even when the capacitance 1 is not connected to the output terminal OUTl, the present embodiment may provide, to the detection signal Det, a minimum detection delay time which is expressed as (Cint x Vref) / Iref.

In the above-described respective embodiments and the respective embodiments below, the delay circuits 101, 101A, 201, 201A, 301, and 401 may further include a capacitance 2 which is connected in parallel to the capacitance 1. This makes it possible to provide a minimum detection delay time to the detection signal Det even when the capacitance 1 is not connected to the output terminal 1.

Seventh embodiment

FIG. 11 is a block diagram illustrating a configuration of a battery pack which includes a semiconductor apparatus for protection 500 according to a seventh embodiment of the present invention. The battery pack in FIG. 11 is configured to include a secondary cell 3; a semiconductor apparatus for protection 500; capacitances 1 and C51; resistors R51, R52, R53; an FET for discharge control Qd; an FET for charge control Qc; and terminals Tp and Tm. A load of the secondary cell 3 or a charger which charges the secondary cell 3 is connected between the terminals Tp and Tm. Moreover, the semiconductor apparatus for protection 500 is configured to include a battery voltage monitoring circuit 501; a current monitoring circuit 502; a delay circuit 201A; a power supply terminal VDD; a ground terminal VSS; detection terminal Sens; output terminals DOUT and COUT; and a terminal V- . Furthermore, compared to the delay circuit 201 in FIG. 3, the delay circuit 201A is different in that it further includes a delay circuit 160A. Moreover, the output terminals DOUT and COUT respectively correspond to output terminals OUTl and OUT2 in FIG. 3.

Moreover, a positive pole terminal of the secondary cell 3 is connected to the terminal Tp and connected to the power supply terminal VDD via the resistor R51. A negative pole terminal of the secondary cell 3 is connected to the ground terminal VSS and connected to the terminal Tm via the resistor R53, the FET for discharge control Qd, and the FET for charge control Qc. The capacitance C51 is connected between the power supply terminal VDD and the ground terminal VSS, while the capacitance 1 is connected between the output terminal DOUT and the ground terminal VSS. The resistor R52 is connected between the terminals V- and Tm.

The current monitoring circuit 502, which is configured to include elements such as a comparator, a reference voltage source, a sensing resistor, etc., detects a voltage across the resistor R52, which is connected between the ground terminal VSS and the detection terminal Sens, to thereby detect a charge current and a discharge current which flow in the secondary cell 3. Then, for a value which is greater than or equal to a predetermined first threshold or which is lower than or equal to a predetermined second threshold which is lower than the first threshold, a High level detection signal Detl is output to the logical operation circuit 240. Here, the first and second thresholds are set such that they respectively correspond to current values at times of over-charge and over-discharge of the secondary cell 3. In other words, the current monitoring circuit 502 generates a High level detection signal Detl when an abnormal current (an over-discharge current or over-charge current) of the secondary cell is detected.

The battery voltage monitoring circuit 501, which is configured to include elements such as a comparator, a reference voltage source, a sensing resistor, etc., detects a cell voltage of the secondary cell 3 based on a voltage between the power supply terminal VDD and the ground terminal VSS. Then, when a voltage value of a cell -voltage- detected- is greater than or equal to a predetermined third threshold value, or less than or equal to a predetermined fourth threshold value which is lower than the third threshold value, a High level detection signal Det2 is output to the delay circuit 201.

In the delay circuit 201A, in the same manner as the logical operation circuit 240 in FIG. 3, the logical operation circuit 240 generates control signals CntS, CntP, CntN, and Cnt2 based on the input detection signals Detl and Det2 and the delay time setting signal DLY. In the present embodiment, the logical operation circuit 240 outputs the control signals CntS and CntN to the delay circuit 160A, outputs the control circuit CntP to the output control circuit 120, and outputs the control signal Cnt2 to the output control circuit 230. The delay circuit 160A delays the control signals CntS and CntN by a predetermined fixed delay time, outputs the delayed control signal CntSD to the delay time setting circuit 210, and outputs the delayed control signal CntNd to the output control circuit 120. Moreover, the delay time setting circuit 210, and the output control circuits 120 and 230 respectively operate in the same manner as the delay time setting circuit 210 and the output control circuits 120 and 230.

Therefore, according to the present embodiment, High level detection signals Detl and Det2 are delayed by an added result of a detection delay time D which is set by equation (1) using a capacitance value Cdly of the capacitance 1 and a delay time set by a delay circuit 160A, so that the delayed results are output from the output terminals DOUT and COUT to the FET for discharge control Qd and the FET for charge control Qc . In this way, the secondary cell 3 may be protected from an abnormal state (for example, over-charge, over-discharge, high voltage, and low voltage) .

As described above, according to the present embodiment, a detection delay time of the semiconductor apparatus for battery pack protection may be set by the capacitance 1 which is connected to outside the semiconductor apparatus for protection 500.

While the semiconductor apparatus for protection 500 includes the delay circuit 201A in the present embodiment, the present invention is not limited thereto, so that it may include the delay circuit 201. In this case, a detection delay time is set only by the capacitance 1.

Moreover, while the battery pack according to the present embodiment includes one secondary cell 3, the present invention is not limited thereto, so that multiple secondary cells may be included.

Furthermore, in the present embodiment, the output control circuit 120, the delay time setting circuit 210, and the capacitance 1 are connected to the output terminal DOUT to provide the output terminal DOUT with not only a function of outputting a signal, but also a function of allowing to set the detection delay time D of the detection signals Detl and Det2 with the attached capacitance 1 which is connected to the output terminal DOUT. However, the present invention is not limited thereto, so that it may be arranged to connect, also to the output terminal COUT, an output control circuit which is similar to the output control circuit 120, a delay time setting circuit which is similar to the delay time setting circuit 210, and a capacitance, to set a detection delay time of the detection signal Det2 independent of a detection delay time D of the detection signal Detl.

Eighth embodiment

FIG. 12 is a block diagram illustrating a configuration of a semiconductor apparatus for voltage detection 600 according to an eighth embodiment of the present invention. In FIG. 12, the semiconductor apparatus for voltage detection 600 is configured to include a ground terminal VSS, an output terminal OUT, an input terminal Sens, a power supply terminal VDD, a delay circuit 101 in FIG. 1, and a voltage detection circuit 603. Moreover, the voltage detection circuit 603 is configured to include resistors R61 and R62 which are serially connected between the input terminal Sens and the ground terminal VSS; a reference voltage source 602; and a comparison circuit 601. Furthermore, a capacitance 1 which has a capacitance value Cdly is connected to the outside of the semiconductor apparatus 600 between the output terminal OUT and the ground terminal VSS.

An input voltage Vin which is input via the input terminal Sens is output to a non-inverting input terminal of the comparison circuit 601 after being voltage divided by the resistors R61 and R62. When the voltage divided input voltage Vin is at least a predetermined reference voltage from the reference voltage source 602, the comparison circuit 601 outputs a High level detection signal Det to the delay circuit 101, while, when the voltage divided input voltage Vi is less than the above-described reference voltage, a Low level detection signal_. Det is output to the delay circuit 101.

While the semiconductor apparatus for voltage protection 600 according to the present embodiment includes a delay circuit 100, the present invention is not limited thereto, so that it may include a delay circuit 301, 401, or 101A.

While reference voltage sources 111 and 354 respectively generate one reference voltage source in the above-described respective embodiments, the present invention is not limited hereto. The reference voltage sources 111 and 354 may generate multiple reference voltages and output one reference voltage selected from the multiple reference voltages generated. This makes it possible to set multiple detection delay times.

Moreover, while the constant current sources 144 and 351 respectively generate one constant current in the above-described respective embodiments, the present invention is not limited hereto. The constant current sources 144 and 351 may generate multiple constant currents and output one constant current selected from the multiple constant currents generated. This makes it possible to set multiple detection delay times. In this case, the constant current source 144 and 351 may respectively include a current mirror circuit or a depression-type MOS transistor.

The present application is based on and claims the benefit of priority of Japanese Priority Application No. 2012-148631 filed on July 2, 2012.

DESCRIPTION OF THE REFERENCE NUMERALS

1, 2 Capacitances

100, 100A, 200, 300, 400, 500, 600 Semiconductor apparatuses

101, 101A, 201, 201A, 301, 401 Delay circuits

110, 210, 201A, 310 Delay time setting circuits

120, 230 Output control circuits

130, 240, 330 Logical operation circuits

160, 160A Delay circuits

350 Oscillating circuit

360 Counter circuit

PATENT DOCUMENT

Patent document 1: JP2012-21867A NON-PATENT DOCUMENTS Non-patent document 1: "R5432V Series, Li-ion/polymer 3/4/5 Cell Batteries protection IC", On-line, retrieved on June 5, 2012, the Internet URL: http: //www. ricoh. co . p/LSI/product_power/flyer/HTM_DUM MY_NAME3.pdf;

Non-patent document 2: Seiko Instruments Inc., "S-8232 Series Battery Protection IC for 2-Serial-Cell Pack", On-line, retrieved on June 5, 2012, the Internet URL : http : / /datasheet . sii-ic . com/ p/battery_protection/ HTM_DUMMY_NAME2. pdf ;

Non-patent document 3: "R3150N Series, Maximum 36V Input Voltage monitoring IC", On-line, retrieved on June 5, 2012, the Internet URL: http: //www. ricoh. co. jp/LSI/product_power/vd/r3150/HTM_ DUMMY_NAMEl.pdf; and

Non-patent document 4: Seiko Instruments Inc., "Super-low current consumption super high-accuracy voltage detector with delay circuit (external delay time setting)", On-line, retrieved on June 5 , 2012, the Internet URL:http: //datasheet . sii-ic. com/jp/voltage_detector/HT M_DUMMY_NAME0. pdf

Claims

CLAIM 1. A delay circuit which delays an input first detection signal by a predetermined detection delay time and outputs the delayed first detection signal inverted or non-inverted from a first output terminal as a first output signal, wherein

the delay circuit generates a delay time setting signal indicating that the detection delay time has elapsed based on a voltage across the first capacitance in response to the first detection signal, and generates the first output signal to output the generated first output signal at generated timing of the delay time setting signal.

CLAIM 2. The delay circuit as claimed in claim 1, further comprising:

a first output control circuit which controls a first output signal level to a predetermined first level or a predetermined second level to output the controlled result from the first output terminal, or controls the first output terminal such that it is brought into a High impedance state;

a delay time setting circuit which responds to an input control signal to charge or discharge the first capacitance and generate the delay time setting signal based on the voltage across the first capacitance; and a logical circuit which controls the first output control circuit such that the first output terminal is brought into the High impedance state in response to the first detection signal, outputs the control signal to the delay time setting circuit, and controls the first output control circuit such that the first output signal which has the first level or the second level is output from the first output terminal in response to the delay time setting signal.

CLAIM 3. The delay circuit as claimed in claim 2, further comprising:

a second output control circuit which controls a second output signal level to the first level or the second level to output the controlled result from a second output terminal, wherein

the logical operation circuit controls the first output control circuit such that the first output terminal is brought into the High impedance state in response to an input second detection signal, outputs the control signal to the delay time setting circuit, and controls the second control circuit such that the second output signal level is caused to change from the first level to the second level, or from the second level to the first level .

CLAIM 4. The delay circuit as claimed in claim 2, wherein the delay time setting circuit compares the voltage across the first capacitance with a predetermined threshold voltage which corresponds to the detection delay time and generates the delay time setting signal when the voltage across the first capacitance reaches the threshold voltage .

CLAIM 5. The delay circuit as claimed in claim 2, wherein the delay time setting circuit includes a constant current source which generates a predetermined constant current to charge or discharge the first capacitance with the constant current.

CLAIM 6. The delay circuit as claimed in claim 2, wherein the delay time setting circuit includes

an oscillating circuit which generates a clock having a predetermined period set with the first capacitance in response to the control signal; and a counter circuit which counts the clock and which generates the delay time setting signal when the number of counts of the clock reaches a predetermined number of threshold times corresponding to the detection, delay time.

CLAIM 7. The delay circuit as claimed, in claim 2, wherein the delay circuit further includes a delay unit which delays the control signal by a predetermined minimum detection delay time.

CLAIM 8. The delay circuit as claimed in claim 1, wherein the delay circuit includes

a depression-type MOS transistor which is connected to the first output terminal;

a comparison circuit which compares the voltage across the first capacitance with a predetermined threshold voltage corresponding to the detection delay time and generates the delay time setting signal when the voltage across the first capacitance reaches the threshold value; and

a gate control circuit which operates the MOS transistor as a constant current source which generates a predetermined constant current in response to the first detection signal to thereby charge or discharge the first capacitance with the constant current and turns on the MOS transistor in response to the delay time setting signal.

CLAIM 9. The delay circuit as claimed in claim

1, further comprising:

a second capacitance which is connected in parallel to the first capacitance to set a minimum value of the detection delay time.

CLAIM 10. A semiconductor apparatus, comprising the delay circuit as claimed in claim 1.