CN114563682A

CN114563682A - Method and apparatus for calculating static delay timing of integrated circuit

Info

Publication number: CN114563682A
Application number: CN202011360073.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2020-11-27
Filing date: 2020-11-27
Publication date: 2022-05-31
Anticipated expiration: 2040-11-27
Also published as: CN114563682B

Abstract

The invention relates to a method for calculating a static delay time sequence of an integrated circuit by utilizing a test circuit, a computer readable storage medium and a processor, wherein a first voltage is input to the test circuit to obtain a first total delay time; inputting a second voltage to the test circuit to obtain a second total delay time; looking up a table to obtain a first delay time sequence ratio of the logic module under two voltages; looking up a table to obtain a second delay timing ratio of the wire at the two voltages; and deriving the delay time sequence of the logic module and the wiring based on the first total delay time, the second total delay time, the first delay time sequence ratio and the second delay time sequence ratio.

Description

Method and apparatus for calculating static delay timing of integrated circuit

Technical Field

The present invention relates generally to the field of test circuits. More particularly, the present invention relates to a method, computer readable storage medium, and processor for calculating static delay timing of an integrated circuit using a test circuit.

Background

With the development of semiconductor technology, chip manufacturing processes have entered the nanometer level, so that the chip has more functions and higher performance, but the circuit complexity is greatly increased, especially the chip is more and more sensitive to process deviations such as process defects, material defects, life defects, and the like, and environmental changes such as voltage, temperature, and the like, and interconnection delay becomes one of the problems to be solved urgently in the static timing analysis of the integrated circuit.

Process fluctuations of the interconnect originate mainly from two aspects. The first aspect is caused by the non-uniformity of the thickness of the metal and insulating layers during the chemical mechanical polishing process during the production process; the second aspect is caused by the inconsistency of interconnect line width and line spacing with design dimensions, which occurs during plate making and etching processes, and includes both line edge roughness and line width roughness effects. The interconnection dimension error caused by the process fluctuation directly changes parameters such as interconnection parasitic resistance (R), capacitance (C) and the like, and further influences the circuit characteristics.

Currently, there is no dedicated test circuit to specifically quantify the actual static delay timing of the chip, so a solution for calculating the static delay timing of the integrated circuit by using the test circuit is urgently needed.

Disclosure of Invention

To at least partially solve the technical problems mentioned in the background, aspects of the present invention provide a method, a computer-readable storage medium, and a processor for calculating a static delay timing of an integrated circuit using a test circuit.

In one aspect, a method of calculating static delay timing of an integrated circuit including a logic block and a wire using a test circuit connected to the logic block and the wire is disclosed. The method comprises the following steps: inputting a first voltage to the test circuit to obtain a first total delay time Td 1; inputting a second voltage to the test circuit to obtain a second total delay time Td 2; looking up a table to obtain a first delay timing ratio Rc of the logic module at the first voltage and the second voltage; looking up a table to obtain a second delay timing ratio Rn of the connection line at the first voltage and the second voltage; and deriving delay timings of the logic modules and the wires based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc, and the second delay timing ratio Rn.

In another aspect, the present invention discloses a computer readable storage medium having stored thereon a computer program code for calculating a static delay timing of an integrated circuit using a test circuit, the computer program code, when executed by a processor, performing the aforementioned method.

In another aspect, a processor for calculating static delay timing of an integrated circuit using a test circuit, the integrated circuit including a logic block and a wiring, the test circuit being connected to the logic block and the wiring. The processor includes: the delay circuit comprises a delay time module, a delay ratio module and a delay time sequence module. The delay time module is connected to the test circuit, and obtains a first total delay time Td1 based on the first voltage and a second total delay time Td2 based on the second voltage. The delay ratio module is used for looking up a table to obtain a first delay timing ratio Rc of the logic module under the first voltage and the second voltage, and looking up the table to obtain a second delay timing ratio Rn of the connection under the first voltage and the second voltage. The delay timing module is used for deriving the delay timing of the logic module and the wire based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc and the second delay timing ratio Rn.

The invention provides a scheme for calculating the static delay time sequence of an integrated circuit by using a test circuit, which specifically quantizes the static delay time sequence of the integrated circuit, compares the data after the integrated circuit which is actually produced in large scale to obtain the static delay time sequence distribution of the integrated circuits in batch, so as to guide the physical realization work and complete more accurate static time sequence analysis and design for manufacturing (DFM) analysis.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are illustrated by way of example and not by way of limitation, and like reference numerals designate like or corresponding parts throughout the several views, in which:

FIG. 1 is a schematic diagram showing a chip produced by a modern process;

FIG. 2 is a circuit diagram showing a 1-out-of-4 selector;

FIG. 3 is a block diagram illustrating an embodiment of the present invention;

FIG. 4 is a logic circuit diagram illustrating a delay of an embodiment of the present invention;

FIG. 5 is a logic circuit diagram illustrating an oscillator of an embodiment of the present invention;

FIG. 6 is a logic circuit diagram illustrating a counter of an embodiment of the present invention;

FIG. 7 is a waveform diagram illustrating an embodiment of the present invention during a count phase;

FIG. 8 is a timing diagram illustrating a plurality of signals of an embodiment of the invention;

FIG. 9 is a schematic diagram illustrating a processor of an embodiment of the invention;

FIG. 10 is a flow chart illustrating the calculation of static delay timing for an integrated circuit according to an embodiment of the present invention;

FIG. 11 is a graph illustrating an exemplary wiring delay profile;

FIG. 12 is a graph illustrating another exemplary wiring delay profile;

FIG. 13 is a graph illustrating another exemplary wiring delay profile; and

fig. 14 is a schematic diagram showing a test circuit group of the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be understood that the terms "first", "second", "third" and "fourth", etc. in the claims, the description and the drawings of the present invention are used for distinguishing different objects and are not used for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and claims of this application, the singular form of "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this specification refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection".

The following detailed description of embodiments of the invention refers to the accompanying drawings.

Fig. 1 shows a schematic diagram of a chip produced by a modern process. The main core of the chip is an integrated circuit 101 and a conductive trace 102, wherein the integrated circuit 101 contains a plurality of circuit elements for implementing one or more logic functions, and the integrated circuit 101 includes a plurality of pins 103 as input/output ports for input/output signal transmission of the integrated circuit 101. The conductive traces 102 are used to electrically connect the pins 103 of the integrated circuits 101, so that the integrated circuits 101 cooperate to realize a specific logic system function. The overall logic system also includes an input/output interface 104 as an input/output signal terminal of the logic system. The integrated circuit 101 and the conductive line 102 are packaged into a chip 105, and the chip 105 includes pins 106 connected to the input/output interface 104 for transmitting the input/output signals of the logic system to the outside of the chip 105.

The integrated circuit 101 may be divided into a base layer (base layer) and a metal layer (metal layer), on which various library units and standard circuit units are distributed, which are collectively referred to as logic modules in the present invention; the metal layer has several stacked metal wirings combined with via holes for electrically connecting the logic modulesSignal transfer may be performed to implement the logic functions of integrated circuit 101. Fig. 2 schematically shows a circuit diagram of a 4-to-1 selector 200, the selector 200 includes 4 and

gates

201, 2 not

gates

202, 1 or gate 203 and a plurality of wires 204, and the selector selects a signal S₁And S₂To control one of the 4 input signals w, x, y, z to become the output signal p, wherein the and gate 201, the not gate 202, the or gate 203, etc. are logic blocks generated on a silicon chip, and the connection lines 204 are those electrically connecting each logic block through vias and metal layers.

In practice, the transistors of the logic blocks may operate in different voltage thresholds, and the common voltage thresholds include an ultra low voltage threshold (uLVT), a Low Voltage Threshold (LVT), a Standard Voltage Threshold (SVT), and a high voltage threshold (LVT). The lower the voltage threshold of the logic module is, the lower the dynamic power consumption of the logic module is, but the more serious the leakage is, the leakage and the frequency are logarithmic, that is, the maximum operating frequency is increased by 1 time, and the leakage is increased by 10 times. Therefore, the working voltage of the integrated circuit does not explicitly pursue a low threshold, but a small part of key logic modules adopt an ultra-low voltage threshold, and the rest adopt a low voltage threshold, a standard voltage threshold or a high voltage threshold, so that the overall efficiency of the integrated circuit is optimal. The foundry typically provides various parameter values below these voltage thresholds for simulation by the chip design company when designing the chip.

The logic modules can generate different RC values when operated at different threshold voltages, and because the wiring is in a three-dimensional multilayer structure when being implemented on a silicon chip and is electrically connected with each metal layer by virtue of the through holes, each metal layer also has different RC values. With the development of semiconductor technology, chip manufacturing process has entered nanometer level, so that the distance between the logic module and the wiring in fig. 2 is smaller and smaller, which not only increases the complexity of circuit design, but also makes the integrated circuit more and more sensitive to process deviation such as process defect, material defect, life defect, etc., and environmental changes such as voltage, temperature, etc., so that the RC values generate significant errors, and these errors directly affect interconnection delay, which causes time sequence disorder, and in severe cases, the integrated circuit cannot normally operate.

The test circuit of the invention is used for quantifying the actual static delay time sequence, and after a large amount of tests are realized, the difference between the actual static delay time sequence and the simulated static delay time sequence can be obtained, so that the degree of process deviation can be known.

The following table exemplarily shows the standard resistance of each metal layer and Via under the standard voltage threshold of 7 nm process by taiwan integrated circuit manufacturing ltd, wherein "Via + i" represents the Via connecting the ith metal layer and the (i + 1) th metal layer, and "M + i" represents the i th metal layer connection.

TABLE 1

In order to reduce the influence of the via on the measurement results, the invention increases the wiring resistance value on each metal layer to more than 10 times the via resistance value, and for this reason, the last column in the table shows the required wire length, which makes the wiring resistance value large enough to ignore the influence of the via resistance. For example, assuming that the timing delay of M7 (the 7 th metal layer wire) is to be measured, the test circuit of the present invention enters the Via2 through the logic module, and the test signal reaches M7 through Via2, Via3, Via4, Via5, Via6 (collectively referred to as Via ladder), and then is conducted back to the test circuit of the present invention from Via6, Via5, Via4, Via3, Via2 (Via ladder), so as to calculate the timing delay of M7. The present invention requires that the wire length of M7 be at least 163.80 microns as listed in the row of table 1, at which length the standard resistance of M7 is 163.80 × 21.39 ═ 3503.68 Ω, and the standard resistance of the via ladder is 2 × (53.55+37.72+12.68+12.68+10.07) × -253.40 Ω. Since the standard resistance of the M7 wiring is more than 10 times of the standard resistance of the through hole ladder, the resistance of the through holes can be directly ignored in the actual test, and the actual timing delay of M7 can be obtained. These required line lengths may be obtained by simulation using a circuit simulation program such as HSPICE for IC performance analysis based on process parameters provided by a foundry such as Taiwan Integrated Circuit manufacturing, Inc. of China.

One embodiment of the present invention is a test circuit for quantifying the static delay timing of a particular cell in an integrated circuit. The particular cells may be logic blocks at different voltage thresholds and various levels of wiring in the metal layers. Fig. 3 shows a block diagram of this embodiment, and the test circuit includes a delay 301, an oscillator 302, a counter 303, and a processor 304. The delay unit 301 is configured to generate an oscillation enable signal 306, a scan enable signal 307, and a selection signal 308 according to the enable signal 305, wherein the oscillation enable signal 306 is used to drive the oscillator 302, and the scan enable signal 307 and the selection signal 308 are used to drive and control the counter 303. The oscillator 302 generates a test signal 309 for a certain time interval to oscillate through a specific unit 310 in response to the oscillation enable signal 306. The counter 303 is reset in response to the reset signal 312, starts or stops counting the oscillation frequency of the test signal 309 in the same time interval in response to the scan enable signal 307, and outputs a measured oscillation frequency signal 313 to the processor 304 in response to the selection signal 308 and the clock signal 311, wherein the clock signal 311 is used for determining the operation frequency of the counter 303 when outputting the oscillation frequency. The processor 304 receives the oscillation times signal 313 and measures the oscillation times to quantify the static delay timing. The following description will be made separately for each element.

Fig. 4 shows a logic circuit diagram of the delayer 301 of this embodiment. The delay 301 includes an input 401, a buffer 402, a buffer 403, a buffer 404, a buffer 405, a buffer 406, a buffer 407, an or gate 408, an or gate 409, a not gate 410, a buffer 411, an output 412, an output 413, and an output 414.

An input 401 of the delay 301 is connected to an input of the buffer 402, an output of the buffer 402 is connected to an input of the buffer 403 and an input of the or-gate 408, an output of the buffer 403 is connected to an input of the buffer 404 and an input of the or-gate 409, an output of the buffer 404 is connected to an input of the buffer 405 and an input of the buffer 406, an output of the buffer 405 is connected to an input of the buffer 407 and another input of the or-gate 408, an output of the buffer 406 is connected to an output 413 of the delay 301, an output of the buffer 407 is connected to another input of the or-gate 409, the output of or gate 408 is connected to the input of buffer 411, the output of or gate 409 is connected to the input of not gate 410, the output of not gate 410 is connected to the output 414 of delay 301, and the output of buffer 411 is connected to the output 412 of delay 301.

The enable signal 305 is input to the delay 301 from the input terminal 401, the oscillation enable signal 306 is output from the output terminal 413 of the delay 301, the scan enable signal 307 is output from the output terminal 414 of the delay 301, and the selection signal 308 is output from the output terminal 412 of the delay 301.

Fig. 5 shows a logic circuit diagram of the oscillator 302 of this embodiment. The oscillator 302 includes an input 501, a nand gate 502, an even number of not gates (illustratively, 6 not gates are shown: the not gate 503, the not gate 504, the not gate 505, the not gate 506, the not gate 507, the not gate 508), and an output 509.

The input 501 of the oscillator 302 is connected to the input of the nand gate 502, the output of the nand gate 502 is connected to the input of the specific unit 310 and the output 509 of the oscillator 302, the output of the specific unit 310 is connected to the input of the not gate 503, the 6 not

gates

503 and 508 are connected in series, and the input of the not gate 508 is connected to the other input of the nand gate 502.

The connecting lines between the NOT gates are shown by dotted lines because a specific cell 310 is connected in series between the NOT gates and the NAND gates 508 and the NAND gates 502, which are not shown for simplicity, and are connected in the same manner as the specific cell 310 is connected in series between the NAND gates 502 and the NOT gates 503. The purpose of this arrangement is to make the range of counts reasonable, on the one hand the number is large enough to distinguish slight delay differences, and on the other hand the number is small enough to avoid setting too many counting cells. For example, the metal layer to be measured is wired to M4, and it is calculated that 17 specific cells 310 are required to allow the counting range to reflect slight delay difference and avoid setting too many counting cells, the oscillator 302 needs to serially connect 16 not gates, one specific cell 310 is serially connected between the not gates and between the not gates 508 and the nand gates 502, 17 specific cells 310 are serially connected in total, each specific cell 310 is M4, and the wire length of M4 of each specific cell 310 is 94.73 micrometers, so the influence of the via ladder can be ignored.

The oscillation enable signal 306 is transmitted from the output 413 of the delay 301 to the input 501 of the oscillator 302, the nand gate 502 and the not

gate

503 and 508 respond to the oscillation enable signal 306 to input the test signal 309 into the plurality of specific units 310, and finally the test signal 309 is introduced into the other input of the nand gate 502 to generate oscillation, and the test signal 309 is output from the output 509 of the oscillator 302. In order to generate oscillation smoothly, the signal level at the output of the nand gate 502 must be the same as the signal level at the output of the not gate 508 (the last stage of the not gate), so the number of the not gates in this embodiment must be even.

Fig. 6 shows a logic circuit diagram of the counter 303 of this embodiment. Counter 303 includes an input 601, an input 602, an input 603, an input 604, and N series flip-flop cells 605, where N is preferably 12 for complete counting, and 3 flip-flop cells 605 are exemplarily shown. Each flip-flop cell 605 includes a D flip-flop 606, a buffer 607, a selector 608, a buffer 609, and a not gate 610, which are connected to each other in the manner shown in the drawing. Each flip-flop 605 can count binary one-

bit values

0 and 1, and when N flip-flop 605 are connected in series, it can count binary N bits, i.e. at most 2^NNext, the process is carried out. The counter 303 further comprises an input 611 and an output 612, the input 611 being connected to the output 509 of the oscillator 302 for receiving the test signal 309.

The scan enable signal 307 is input from an input terminal 601 of the counter 303, the selection signal 308 is input from an input terminal 602 of the counter 303, the clock signal 311 is input from an input terminal 603 of the counter 303, the reset signal 312 is input from an input terminal 604 of the counter 303, and the oscillation frequency signal 313 is output from an output terminal 612 of the counter 303.

When the test circuit is to initiate oscillation,referring to FIG. 7, first at t₁Time is allowed for the reset signal 312 to form a square wave, which in this embodiment lasts at least 200 picoseconds, so that the values of all D flip-flops 606 in the counter 303 are reset to 0. Then enable signal 305 is at t₂The time is changed from low level to high level, and the time is kept for 1000 ns, the enable signal 305 has three functions for the test circuit, the first is to control the ring oscillation of the oscillator 302 to start and close, the second is to realize the selection of the clock of the counter 303, and the third is to match the clock signal 311 after the enable signal 305 is changed from high level to low level, and at t₃The time start drive counter 303 outputs a count value. The operation of the various components will be described in greater detail below.

At t₂At the time when the enable signal 305 goes from low to high, one of the paths (buffer 402, or gate 408, buffer 411, output 412) of the delay 301 will respond most quickly, so the select signal 308 goes from low to high earliest. The selection signal 308 is input to the input 602 of the counter 303, and the signal for controlling the clock terminal of each flip-flop cell 605 is derived from the test signal 309 or the clock signal 311. When the selection signal 308 is high, the selector 608 of this embodiment selects the test signal 309 from the input end 611 and transmits the test signal 309 to the clock end of the D flip-flop 606, in preparation for starting counting the ring oscillation frequency of the oscillator 302.

After the select signal 308 goes high, the other path of the delay 301 (buffer 402, buffer 403, or gate 409, not gate 410, output 414) then responds, so the scan enable signal 307 goes from high to low, the scan enable signal 307 is input to the input 601 of the counter 303 and transmitted to the SE port of each D flip-flop 606, and when the scan enable signal 307 goes low, the data of each D flip-flop 606 goes from the D port to the Q port, and the counter 303 is ready.

The other path (buffer 402, buffer 403, buffer 404, buffer 406, output 413) of the delay unit 301 goes through 4-stage buffering of the buffer 402, buffer 403, buffer 404, and buffer 406, and finally responds such that the oscillation enable signal 306 goes from low level to high level, and the oscillation enable signal 306 is input to the input terminal 501 of the oscillator 302. When the oscillation enable signal 306 is still at a low level, the output of the nand gate 502 is at a high level, when the oscillation enable signal 306 changes from a low level to a high level, the output of the nand gate 502 changes to a low level, the output of the not gate 508 changes to a low level after the low-level test signal 309 passes through the specific units 310 (without changing the level thereof) and the 6 not

gates

503 and 508, so that the output of the nand gate 502 changes to a high level, the output of the not gate 508 changes to a high level after the high-level test signal 309 passes through the specific units 310 and the 6 not

gates

503 and 508, and the output of the nand gate 502 changes to a low level again. Accordingly, the test signal 309 oscillates high and low in the ring while the oscillation enable signal 306 remains high.

The test signal 309 is input to the clock terminal of the D flip-flop 606 as the clock signal of the D flip-flop 606, and then an inverted level signal is formed between the D terminal and the Q terminal based on the not gate 610 and the buffer 609, and when the level of the test signal 309 changes by one period, the level of the Q terminal changes accordingly. The output of the not gate 610 of the previous stage D flip-flop 606 is connected to the input of the selector 608 of the next stage flip-flop cell 605, so that the N flip-flop cells 605 start counting according to the high-low oscillation of the test signal 309.

As described above, the delay unit 301 sequentially drives the selection signal 308, the scan enable signal 307, and the oscillation enable signal 306 to change the level to drive the oscillator 302 to generate the oscillating test signal 309, and the counter 303 counts according to the oscillation of the test signal 309.

Since the delay time of the test signal 309 passing through the specific cell 310 is proportional to the RC value thereof, the delay time is longer when the actual resistance value of the specific cell 310 is larger than the standard resistance value, and is shorter otherwise. The test circuit of this embodiment measures the oscillation frequency of the test signal 309 in a unit time (1000 ns), and if the frequency is high, it indicates that the delay time of the specific cell 310 is short, i.e., the actual resistance value of the specific cell 310 is small, and if the frequency is low, it indicates that the delay time of the specific cell 310 is long, i.e., the actual resistance value of the specific cell 310 is large. By detecting the number of oscillations, the difference between the actual static timing delay of a particular cell 310 and the standard static timing delay can be estimated.

After the enable signal 305 is asserted high for 1000 ns, the enable signal 305 goes from high to low, which first forces the oscillation enable signal 306 to go from high to low, and once the oscillation enable signal 306 goes low, the output of the nand gate 502 of the oscillator 302 is asserted high and no longer oscillates, thereby stopping the ring oscillation.

Next, the selection signal 308 changes from high level to low level after 4-level buffering (buffer 402, buffer 403, buffer 404, buffer 405), which controls the selector 608 of the flip-flop 605 of the counter 303 to select the clock signal 311, and the D flip-flop 606 starts to operate according to the clock signal 311 instead of the test signal 309, in this embodiment, the period of the clock signal 311 is greater than 20 ns.

Finally, the scan enable signal 307 changes from low level to high level after 5-stage buffering (buffer 402, buffer 403, buffer 404, buffer 405, buffer 407), and the SE terminal of the D flip-flop 606 is at high level, so that the data of the D flip-flop 606 arrives at the Q port from the SI terminal instead of the D terminal, and serial output for counting is ready.

Since the output of the previous stage 605 of the counter 303 is connected to the SI terminal of the next stage 605, the output 612 of the counter 303 will sequentially forward from the last stage 605 to the processor 304 based on the timing of the clock signal 311, i.e., the processor 304 receives the highest bit value of the binary system first, then the second highest bit value, and then the lowest bit value. Accordingly, the processor 304 obtains a binary oscillation order value.

In summary, when the enable signal 305 goes from high to low, the delay unit 301 sequentially drives the oscillation enable signal 306, the selection signal 308 and the scan enable signal 307 to change the level, so that the counter 303 outputs the oscillation count to the processor 304.

Fig. 8 is a timing diagram of the enable signal 305, the oscillation enable signal 306, the scan enable signal 307, and the select signal 308. based on the logic scheme of the delay 301 of this embodiment, the select signal 308 changes level later than the enable signal 305 when oscillation is started, the scan enable signal 307 changes level later than the enable signal 305, the oscillation enable signal 306 changes level later than the enable signal 305 when counting is output, the select signal 308 changes level later than the oscillation enable signal 306, and the scan enable signal 307 changes level later than the select signal 308.

In this embodiment, the delay unit 301 is arranged to generate the oscillation enable signal 306, the scan enable signal 307 and the selection signal 308 by using only one enable signal 305, and as can be seen from fig. 7, the test result (oscillation frequency signal) can be obtained by only providing the enable signal 306, the clock signal 311 and the reset signal 312, so that the control of the test circuit is simpler.

When a specific unit of the integrated circuit is tested by using the test circuit of this embodiment, the specific unit needs to operate at 2 voltages respectively, so that the processor 304 can obtain enough information to calculate the timing delay. Fig. 9 shows a schematic diagram of the processor 304 of this embodiment. The processor 304 includes an input 901, a delay time module 902, a delay ratio module 903, a delay timing module 904, and an output 905, each of which performs the process shown in fig. 10.

Because the wiring is too fine, the wiring cannot be connected with a test circuit for testing alone, and the logic module is connected to obtain the time sequence delay information of the logic module and calculate the time sequence delay information of the wiring.

In step 1001, a first voltage is input to the test circuit to obtain a first total delay time Td 1. The first voltage may be any voltage value acceptable to the integrated circuit, for example 0.75V. The oscillator 302 generates a test signal 309 in a time interval, the test signal 309 is delayed by a logic module and a wire, and the counter 303 records a binary first oscillation frequency and outputs the binary first oscillation frequency to the processor 304. The delay time module 902 receives the first oscillation times through the input terminal 901, and further obtains a first total delay time Td 1.

More specifically, the delay time module 902 receives the bit values of the first oscillation frequency sequentially from the highest bit to the lowest bit of the binary system, for example, the delay time module 902 receives [ 11111010000 ], which indicates that the first oscillation frequency is 2000 times in the time interval. The delay time module 902 then divides the time interval by the first oscillation number and then by the number of ring oscillation stages to obtain a first total delay time Td1, which is:

td1 time interval/first oscillation frequency/ring oscillation stage number

The number of ring stages is the total number of all logic gates in the oscillator 302, i.e. the number of the specific cells 310 connected in series, and in this embodiment, the total number of the nand gates 502 and the not

gates

503 and 508 is 7. Taking the time interval as 1000 ns, the first oscillation frequency as 2000 times, and the number of ring stages as 7 as examples, the first total delay time Td1 is 1000 ns/2000/7 is 71 ps. The first total delay time Td1 reflects the total delay time of a particular unit 310 (logic block plus wire) when the integrated circuit is operating at 0.75V.

In step 1002, a second voltage is input to the test circuit to obtain a second total delay time Td 2. The second voltage is also any voltage value acceptable to the integrated circuit, but must be different from the first voltage, such as 0.8V. The oscillator 302 generates a test signal 309 in the same time interval, the test signal 309 is delayed by the logic module and the wire, and the counter 303 records the binary second oscillation frequency and outputs the second oscillation frequency to the processor 304. The delay time module 902 receives the bit values of the second oscillation times sequentially from the highest bit to the lowest bit through the input terminal 901, for example, if the delay time module 902 receives [ 11111101110 ], it indicates that the second oscillation times is 2030 times in the time interval. The delay time module 902 then divides the time interval by the second oscillation number and then by the number of ring stages to obtain a second total delay time Td 2. For the above example, Td2 is 1000 ns/2030/7 is 70 ps. The second total delay time Td2 reflects the total delay time of a particular unit 310 (logic module, wiring) when the integrated circuit is operating at 0.8V.

In step 1003, a table lookup is performed to obtain a first delay timing ratio Rc of the logic module at the first voltage and the second voltage. As described above, the foundry provides various parameter values at the voltage threshold, and based on these parameter values, the simulated timing delay shown in Table 2 can be made (room temperature 25 degrees Celsius, ultra-low voltage threshold for example).

TABLE 2

The delay ratio module 903 obtains a first delay timing ratio Rc of the logic module at the first voltage and the second voltage by looking up the table 2, and the first delay timing ratio Rc is calculated by:

wherein Tc1 is the time delay of the logic module at the first voltage, and Tc2 is the time delay of the logic module at the second voltage. For example, the particular cell to be tested is M3, then:

in step 1004, a table lookup obtains a second delay timing ratio Rn of the wire at the first voltage and the second voltage. The delay ratio module 903 continues to look up table 2 to obtain a second delay timing ratio Rn of the wire at the first voltage and the second voltage, where the second delay timing ratio Rn is calculated by:

where Tn1 is the time delay of the wire at the first voltage and Tn2 is the time delay of the wire at the second voltage. For example, the particular cell to be tested is M3, then:

in step 1005, the delay timing of the logic blocks and the wires are derived based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc and the second delay timing ratio Rn. The delay timing module 904 derives the timing delays of the logic blocks and the connections based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc, and the second delay timing ratio Rn obtained in advance, that is:

according to the above formula, the delay timing module 904 obtains the actual time delay Tc1 of the logic module at the first voltage, the actual time delay Tc2 of the logic module at the second voltage, the actual time delay Tn1 wired at the first voltage, and the actual time delay Tn2 wired at the second voltage. These data are output via output 905 for subsequent processing.

By the method, the test circuit of the embodiment can obtain the timing delay of the logic module and the specific metal layer wiring under the specific voltage. In an application scenario, by using a large number of test chips in the embodiment, big data of the process corner connection delay of each layer of metal at a specific temperature can be obtained, and because each chip has a slight error in the manufacturing process, the process deviation of the batch of chip metal wires can be obtained based on the big data. Fig. 11 shows an exemplary wiring delay distribution graph, where a dashed line 1101 indicates that the wiring is 20% faster than the standard deviation in the simulation environment, a dashed line 1102 indicates that the wiring is 20% slower than the standard process deviation in the simulation environment, and the histogram is the actually measured distribution, it can be seen that the data is normally distributed around 0%, indicating that the RC values of the wiring of the batch of chips are not deviated. Fig. 12 shows another exemplary wiring delay profile showing that the RC value of the wiring for this batch of chips is larger than the standard process, so that the timing delay is overall slower. Fig. 13 shows another exemplary wiring delay profile showing that the RC value of the wiring for this batch of chips is smaller than the standard process, so that the timing delay is overall faster.

The embodiment provides a test circuit, which specifically quantifies the time sequence delay of a logic module of a chip and a metal layer wiring, and compares the time sequence delay of the actually produced chip after a large number of tests to obtain the whole time sequence delay distribution of the chip so as to guide the work of physical realization.

Another embodiment of the present invention is a test circuit set using the test circuit frame of fig. 3 for testing a plurality of specific units at a time. Fig. 14 shows a test circuit group of this embodiment, which includes a delay 1401, a multistage test circuit 1402, and a processor 1403.

The delay 1401 functions as the delay 301 to generate an oscillation enable signal, a scan enable signal and a selection signal according to an enable signal. Each stage of test circuit 1402 includes an oscillator 1404 and a counter 1405, the oscillator 1404 having the same function as the oscillator 302, generating a test signal in response to an oscillation enable signal within a time interval to oscillate through a plurality of specific units 1406, the counter 1405 having the same function as the counter 303, resetting in response to a reset signal, receiving the test signal generating the oscillation, starting or stopping counting the number of oscillations of the test signal within the same time interval in response to a scan enable signal, and outputting a measured oscillation number signal in response to a selection signal and a clock signal. The processor 1403, which functions as the processor 304, receives the oscillation times signal and measures the oscillation times to quantify the static delay timing.

If the chip to be tested has N particular cells, this embodiment may configure N stages of test circuits 1402, each stage of test circuits 1402 testing one particular cell 1406. The counter 1405 of each stage of the test circuit 1402 is connected in series with the counter 1405 of the upper and lower stages of the test circuit 1402, and the output terminal of the counter 1405 of the last stage of the test circuit 1402 is connected to the processor 1403.

For example, if the specific cell to be tested has 13 logic modules under the ultra-low voltage threshold, 13 logic modules under the standard voltage threshold, and 13 connections from M2 to M11, the test circuit group of this embodiment needs to be configured with 13-level test circuits 1402, that is, N is 13. One specific cell 1406 is connected per stage, for example, specific cell 1 is M11, specific cell 2 is M10, specific cell 3 is M9, specific cell 4 is M8, specific cell 5 is M7, specific cell 6 is M6, specific cell 7 is M5, specific cell 8 is M4, specific cell 9 is M3, specific cell 10 is M2, specific cell 11 is a logic module under a standard voltage threshold, specific cell 12 is a logic module under a low voltage threshold, and specific cell 13 is a logic module under an ultra-low voltage threshold.

When the test circuit group wants to start oscillation, the reset signal is first used to reset all the D flip-flops in the counter 1405, then the enable signal is switched from low level to high level, and the delay 1401 controls the selection signal to be switched from low level to high level at the earliest so that the test signal is transmitted to the clock terminal of the D flip-flops in the counter 1405. The delay 1401 then controls the scan enable signal to go from high to low, so that the data of each D flip-flop in the counter 1405 arrives at the Q port from the D port, and the counter 1405 is ready. The delay 1401 finally controls the oscillation enable signal to go from low level to high level, and the oscillation enable signal is inputted to each oscillator 1404, the test signal starts to oscillate high and low in the oscillation loop, and the counter 1405 counts according to the oscillation of the test signal.

After the enable signal is maintained at the high level for a certain period of time, the enable signal goes low, and the delay 1401 first controls the oscillation enable signal to go low from the high level, so that the oscillator 1404 stops oscillating. Then the delay 1401 controls the selection signal to go from high level to low level, and the D flip-flop of the counter 1405 starts to operate according to the clock signal instead of the test signal. Finally, the delay 1401 controls the scan enable signal to change from low level to high level, and starts to output the count data serially.

As shown in fig. 14, a counter 1405 for counting the number of oscillations of the specific unit N is directly connected to the processor 1403, followed by the counter 1405 for counting the number of oscillations of the specific unit N-1, followed by the counter 1405 for counting the number of oscillations of the specific unit N-2, until the last counter 1405 for counting the number of oscillations of the specific unit 1, so that the processor 1403 receives the number of oscillations of the specific unit N first, followed by the counter of oscillations of the specific unit N-1, followed by the counter of oscillations of the specific unit N-2, and followed by the counter of oscillations of the specific unit N-1.

Also taking the 13 specific units to be tested as an example, the processor 1403 will receive the oscillation frequency signal of each specific unit 1406 in the following order: logic modules at ultra-low voltage thresholds, logic modules at standard voltage thresholds, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11.

After receiving the oscillation times of all the specific units 1406, the processor 1403 executes the process shown in fig. 10 to obtain the timing delay of each specific unit 1406 at the 2 operating voltages, and further can test a large number of chips by using this embodiment to obtain the connection delay distribution of each specific unit 1406 of the batch of chips.

The embodiment provides a test circuit group, which specifically quantizes the time sequence delay of all or part of logic modules and metal layer wiring of a chip, and compares the time sequence delay of the chip produced in practice after a large number of tests to obtain the whole time sequence delay distribution of the chip so as to guide the work of physical realization.

Another embodiment of the invention is a computer readable storage medium having stored thereon computer program code for calculating a static delay timing of an integrated circuit using a test circuit, which when executed by a processor performs the method as described in fig. 10.

The invention specifically quantizes the static delay time sequence of the integrated circuit to obtain the static delay time sequence distribution of the integrated circuit, so as to guide the work of physical implementation and complete more accurate static time sequence analysis and manufacturability design analysis, and the more accurate static time sequence analysis and manufacturability design analysis are beneficial to adopting higher working frequency under the condition of considering the yield in the back-end implementation.

It is noted that for the sake of simplicity, the present invention sets forth some methods and embodiments thereof as a series of acts or combinations thereof, but those skilled in the art will appreciate that the inventive arrangements are not limited by the order of acts described. Accordingly, persons skilled in the art may appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the invention. Further, those skilled in the art will appreciate that the described embodiments of the invention are capable of being practiced in other alternative embodiments that may involve fewer acts or modules than are necessary to practice one or more aspects of the invention. In addition, the description of some embodiments of the present invention is also focused on different schemes. In view of the above, those skilled in the art will understand that portions of the present invention that are not described in detail in one embodiment may also refer to related descriptions of other embodiments.

In particular implementations, based on the disclosure and teachings of the present invention, one of ordinary skill in the art will appreciate that the several embodiments disclosed herein can be practiced in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are split based on the logic function, and there may be another splitting manner in the actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In the present invention, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed across multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the scheme of the embodiment of the invention. In addition, in some scenarios, multiple units in an embodiment of the present invention may be integrated into one unit or each unit may exist physically separately.

The foregoing may be better understood in light of the following clauses:

clause a1, a test circuit for quantifying the static delay timing of a particular cell in an integrated circuit, comprising: an oscillator responsive to an oscillation enable signal to generate a test signal to generate oscillation by the specific unit; a counter to count the number of oscillations within a time interval; and a processor configured to quantize the static delay time sequence according to the sub-quantization.

Clause a2, the test circuit of clause a1, wherein the particular cell is one of a logic module and a wire.

Clause A3, the test circuit of clause a2, wherein the logic module employs one of an ultra-low voltage threshold, a low voltage threshold, and a standard voltage threshold.

Clause a4, the test circuit of clause a1, wherein the oscillator comprises: a nand gate inputting the test signal to the specific unit in response to the oscillation enable signal; and a plurality of series not gates inputting an output signal from the specific cell to the nand gate.

Clause a5, the test circuit of clause a4, wherein the counter receives the test signal, starts or stops counting in response to a scan enable signal.

Clause a6, the test circuit of clause a5, wherein the test circuit is in accordance with clause aThe counter comprises N series trigger units for counting at most 2^NThe number of times.

Clause a7, the test circuit of clause a6, wherein the test circuit comprises a delay to generate the oscillation enable signal, the scan enable signal, and a select signal according to an enable signal.

Clause A8, the test circuit of clause a7, wherein when the enable signal transitions from low to high, the delay sequentially drives the select signal, the scan enable signal, and the oscillation enable signal to transition from low to high, the counter starts counting; when the enable signal is converted from high level to low level, the delayer sequentially drives the oscillation enable signal, the selection signal and the scanning enable signal to be converted from high level to low level, and the counter outputs the times to the processor.

Clause a9, the test circuit of clause a7, wherein the select signal is to control the clock selection of one of the N series connected flip-flop cells from the test signal or clock signal.

Clause a10, the test circuit of clause a2, wherein the processor comprises: a delay time module for obtaining a first total delay time based on the first voltage and obtaining a second total delay time based on the second voltage; a delay ratio module to test the logic module with the oscillator to obtain a first delay timing ratio Rc of the logic module at the first voltage and the second voltage, and to test the wire with the oscillator to obtain a second delay timing ratio of the wire at the first voltage and the second voltage; and a delay timing module to derive the static delay timing of the logic module and the wire based on the first total delay time, the second total delay time, the first delay timing ratio, and the second delay timing ratio.

Clause a11, the test circuit of clause a10, wherein the delay time module is to: calculating a first oscillation frequency in the time interval by utilizing the counter; and dividing the time interval by the first oscillation frequency and then by the ring oscillation number to obtain the first total delay time.

Clause a12, the test circuit of clause a10, wherein the delay time module is to: calculating a second oscillation frequency in the time interval by utilizing the counter; and dividing the time interval by the second oscillation times and then by the ring oscillation number to obtain the second total delay time.

Clause a13, the test circuit of clause a11 or 12, wherein the oscillator comprises a nand gate and a plurality of series nor gates, the ring order being a total number of the nand gate and the plurality of series nor gates.

Clause a14, a test circuit set for quantifying static delay timing of a plurality of specific cells in an integrated circuit, comprising: a multi-stage test circuit, each stage of the test circuit comprising: an oscillator responsive to an oscillation enable signal to generate a test signal to generate oscillation by the specific unit; a counter to count a number of said oscillations within a time interval; and a processor configured to quantize the static delay time sequence according to the sub-quantization; wherein the counter is connected in series with the counter of the superior test circuit.

Clause a15, the set of test circuits of clause a14, wherein the plurality of particular units includes logic blocks and connections, the oscillator of each stage of test circuits is connected to a different particular unit.

Clause a16, the set of test circuits of clause a15, wherein the logic module employs one of an ultra-low voltage threshold, a low voltage threshold, and a standard voltage threshold.

Clause a17, the set of test circuits of clause a14, wherein the oscillator comprises: a nand gate inputting the test signal to the specific unit in response to the oscillation enable signal; and a plurality of series not gates inputting an output signal from the specific cell to the nand gate.

Clause a18, the set of test circuits of clause a17, wherein the counter receives the test signal, starts or stops counting in response to a scan enable signal.

Clause a19, the set of test circuits of clause a18, wherein the counter comprises N series flip-flop cells for counting up to 2^NThe number of times.

Clause a20, the set of test circuits of clause a19, wherein the set of test circuits includes a delay to generate the oscillation enable signal, the scan enable signal, and a select signal according to an enable signal.

Clause a21, the set of test circuits of clause a20, wherein when the enable signal transitions from low to high, the delay sequentially drives the select signal, the scan enable signal, and the oscillation enable signal to transition from low to high, and the counter starts counting; when the enable signal is converted from high level to low level, the delayer sequentially drives the oscillation enable signal, the selection signal and the scanning enable signal to be converted from high level to low level, and the multistage test circuit outputs the times to the processor.

Clause a22, the set of test circuits of clause a20, wherein the select signal is used to control the clock of one of the N series flip-flop cells to select one of the test signal and the output signal of the counter of the superior test circuit or a clock signal.

Clause a23, the set of test circuits of clause a15, wherein the processor comprises: a delay time module for obtaining a first total delay time based on the first voltage and obtaining a second total delay time based on the second voltage; a delay ratio module to test the logic module with the oscillator to obtain a first delay timing ratio Rc of the logic module at the first voltage and the second voltage, and to test the wire with the oscillator to obtain a second delay timing ratio of the wire at the first voltage and the second voltage; and a delay timing module to derive the static delay timing of the logic module and the wire based on the first total delay time, the second total delay time, the first delay timing ratio, and the second delay timing ratio.

Clause a24, the set of test circuits of clause a23, wherein the delay time module is to: calculating a first oscillation frequency in the time interval by utilizing the counter; and dividing the time interval by the first oscillation frequency and then by the ring oscillation number to obtain the first total delay time.

Clause a25, the set of test circuits of clause a23, wherein the delay time module is to: calculating a second oscillation frequency in the time interval by utilizing the counter; and dividing the time interval by the second oscillation times and then by the ring oscillation number to obtain the second total delay time.

Clause a26, the set of test circuits of clause a24 or 25, wherein the oscillator comprises a nand gate and a plurality of series nor gates, the ring order being the total number of the nand gate and the plurality of series nor gates.

Clause a27, the set of test circuits of clause a14, wherein the processor is connected to a counter of a last stage test circuit.

Clause B1, a method of calculating static delay timing of an integrated circuit using a test circuit, the integrated circuit comprising a logic block and wiring, the test circuit connected to the logic block and the wiring, the method comprising: inputting a first voltage to the test circuit to obtain a first total delay time Td 1; inputting a second voltage to the test circuit to obtain a second total delay time Td 2; looking up a table to obtain a first delay timing ratio Rc of the logic module at the first voltage and the second voltage; looking up a table to obtain a second delay timing ratio Rn of the connection line at the first voltage and the second voltage; and deriving delay timings of the logic modules and the wires based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc, and the second delay timing ratio Rn.

Clause B2, the method of clause B1, wherein the step of inputting a first voltage to the test circuit comprises: calculating a first oscillation frequency in a time interval by using the test circuit; and dividing the time interval by the first oscillation frequency and then dividing by the number of ring oscillation stages to obtain the first total delay time Td 1.

Clause B3, the method of clause B1, wherein the step of inputting a second voltage to the test circuit comprises: calculating a second oscillation frequency within a time interval by using the test circuit; and dividing the time interval by the second oscillation number and then by the number of ring stages to obtain the second total delay time Td 2.

Clause B4, the method of clause B2 or 3, wherein the test circuit comprises an oscillator comprising a nand gate and a plurality of not gates, the ring order being a total number of the nand gate and the plurality of not gates.

Clause B5, the method of clause B1, wherein the first delay timing ratio Rc and the second delay timing ratio Rn are derived from a table lookup.

Clause B6, the method of clause B1, wherein the delay timing Tn1 of the wire at the first voltage is obtained by the formula:

clause B7, the method of clause B1, wherein the delay timing Tn2 of the wire at the second voltage is obtained by the formula:

clause B8, the method of clause B1, wherein the delay timing Tc1 of the logic module at the first voltage is obtained by the formula:

clause B9, the method of clause B1, wherein the delay timing Tc2 of the logic module at the second voltage is obtained by the formula:

clause B10, a computer readable storage medium having stored thereon computer program code for calculating a static delay timing of an integrated circuit using test circuitry, the computer program code, when executed by a processor, performing the method of any of clauses B1-9.

Clause B11, a processor for calculating static delay timing of an integrated circuit using a test circuit, the integrated circuit including a logic block and a wire, the test circuit connected to the logic block and the wire, the processor comprising: a delay time module connected to the test circuit, obtaining a first total delay time Td1 based on a first voltage, and obtaining a second total delay time Td2 based on a second voltage; a delay ratio module for looking up a table to obtain a first delay timing ratio Rc of the logic module at the first voltage and the second voltage, and looking up a table to obtain a second delay timing ratio Rn of the wire at the first voltage and the second voltage; and a delay timing module to derive delay timings of the logic modules and the wires based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc, and the second delay timing ratio Rn.

The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A method of calculating static delay timing of an integrated circuit using a test circuit, the integrated circuit including logic blocks and connections, the test circuit being connected to the logic blocks and the connections, the method comprising:

inputting a first voltage to the test circuit to obtain a first total delay time Td 1;

inputting a second voltage to the test circuit to obtain a second total delay time Td 2;

looking up a table to obtain a first delay timing ratio Rc of the logic module at the first voltage and the second voltage;

looking up a table to obtain a second delay timing ratio Rn of the connection line at the first voltage and the second voltage; and

deriving delay timings of the logic modules and the wires based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc, and the second delay timing ratio Rn.

2. The method of claim 1, wherein inputting a first voltage to the test circuit comprises:

calculating a first oscillation frequency in a time interval by using the test circuit; and

dividing the time interval by the first oscillation number and then dividing by the number of ring oscillation stages to obtain the first total delay time Td 1.

3. The method of claim 1, wherein inputting a second voltage to the test circuit comprises:

calculating a second oscillation frequency within a time interval by using the test circuit; and

dividing the time interval by the second oscillation number and dividing by the number of ring oscillation stages to obtain the second total delay time Td 2.

4. The method of claim 2 or 3, wherein the test circuit comprises an oscillator comprising a NAND gate and a plurality of NOT gates, the ring order being a total number of the NAND gate and the plurality of NOT gates.

5. The method of claim 1, wherein the first delay timing ratio Rc and the second delay timing ratio Rn are derived from a look-up table.

6. The method of claim 1, wherein a delay timing Tn1 of the wire at the first voltage is obtained by the equation:

7. the method of claim 1, wherein a delay timing Tn2 of the wire at the second voltage is obtained by the equation:

8. the method of claim 1, wherein the delay timing Tc1 of the logic module at the first voltage is obtained by the following equation:

9. the method of claim 1, wherein the delay timing Tc2 of the logic module at the second voltage is obtained by the following equation:

10. a computer readable storage medium having stored thereon computer program code for calculating a static delay timing of an integrated circuit using a test circuit, which when executed by a processor performs the method of any of claims 1 to 9.

11. A processor for calculating static delay timing of an integrated circuit using a test circuit, the integrated circuit including logic blocks and connections, the test circuit being connected to the logic blocks and the connections, the processor comprising:

a delay time module connected to the test circuit, obtaining a first total delay time Td1 based on a first voltage, and obtaining a second total delay time Td2 based on a second voltage;

a delay ratio module for looking up a table to obtain a first delay timing ratio Rc of the logic module at the first voltage and the second voltage, and looking up a table to obtain a second delay timing ratio Rn of the wire at the first voltage and the second voltage; and

a delay timing module to derive delay timing of the logic module and the wire based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc, and the second delay timing ratio Rn.