JPS6051838B2 - pattern signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern signal generator capable of outputting dot hatch signals or crosshatch signals on a cathode ray tube. An object of the present invention is to provide a device that can easily change the width of a signal.

An embodiment of the present invention will be described below along with a conventional device.

FIG. 1 shows an example of a television receiver incorporating a pattern signal generator 8 of the present invention, in which 1 is a video detection circuit, 2
1 is a synchronization separation circuit, 3 is a horizontal deflection circuit, 4 is a vertical deflection circuit, 5 is a video amplifier, and 6 is a cathode ray tube, and 1 to 6 are the same as in a normal television receiver.

Reference numeral 7 denotes a changeover switch for switching between the output of the pattern signal generator 8 and the output of the video detection circuit 1.

Next, the contents of the pattern signal generating device 8 will be explained using FIGS. 2 to 5. As shown in FIG. 2, a NAND gate 9,
10, resistors 12 and 13, and capacitors 11 and 14 is a generally known gated oscillator, and a horizontal pulse shown in FIG. Oscillates for periods of high level.

It becomes possible to oscillate at the time shown in FIG. 3 from O, and the oscillation output shown in FIG. The output of the oscillator is 16
The signal is applied to the bit shift register 15 as a clock signal. The output of the shift register 15 is sent to the OR gate 16
The signal is applied to the input terminal of the shift register 15 via. A flip-flop 17 is provided to which the horizontal pulse shown in FIG. It is added to the input terminal of the shift register 15. As shown in Figure 3c, the above Q output rises at the falling edge of the horizontal pulse in Figure 3a (at time t1), and falls at the rising edge of Figure 2 (at time t1(0)). In other words, the signal at the input terminal of the shift register 15 is at time TlO
Since the level is high from O to TlO3 and then becomes low level, the pulse shown in FIG. 3d is generated at the 16th bit. This pulse is generated every 16 bits thereafter. Therefore, if the frequency of the signal shown in Fig. 3b is selected to an appropriate value, X 1-bit width high-level signals (white on a cathode ray screen) can be obtained during one horizontal scanning period, and these signals are transmitted every horizontal scanning period. It will be repeated for a period of time. If this is displayed on a cathode ray tube screen, it will appear as multiple white vertical lines. The interval between the vertical lines can be freely determined within the range of 9 to 16 bits if the shift register 15 is of parallel output type. On the other hand, the following circuit is provided to produce horizontal lines on the cathode ray tube screen.

That is, the negative horizontal pulse shown in FIG. 3a is applied to the AND gate 18 via the inverter 29, and the vertical synchronizing signal shown in FIG. 4a is applied to the AND gate 18. Then, the signal shown in FIG. 4 is obtained from the gate 18 of M, and this corresponds to the clock signal shown in FIG. 3b.
This clock signal is applied to a 16-bit shift register 19 and further applied to a set terminal of a flip-flop 21. The vertical synchronizing signal shown in FIG. 4A is applied to the reset terminal of the flip-flop 21. The O output of the flip-flop 21 is -0 along with the output of the shift register 19.
It is applied to the input terminal of the shift register 19 through the R gate 20. Since the horizontal synchronization signal and the vertical synchronization signal are out of phase by an 11-period period for each field, the signal shown in Figure 4, ``C'', will be changed to the signal ``C'' in Figure 4 in the next field. become that way.
Note that the signals C and E in FIG. 4 are the O outputs of the flip-flop 21. The operation of this circuit is similar to the vertical line case,
A pulse with a width of one horizontal period is output from the shift register 19 every 16 bits. The output of the shift register 19 and the output of the shift register 15 are connected to an AND gate 22 and an 0R gate 23.
added to.

A ground current or a voltage of +5V is applied to this AND gate 22 via a changeover switch 28. 0R
A signal obtained by inverting the polarity of the output of the gate 23 and the output of the switch 28 using the inverter 25 is applied to the AND gate 24, and the output of the AND gate 24 and the output of the AND gate 22 are sent to the buffer amplifier 27 via the 0R gate 26. has been added.

The output of this buffer amplifier 27 is applied to the cathode ray tube from a terminal 30. Set the changeover switch 28 to A or b as shown.
When it is in a short circuit state, the AND gate 22 is in a cutoff state,
Since the NΦ gate 24 becomes conductive, the shift register 1
Both outputs 5 and 19 are applied to the cathode ray tube, and a crosshatch signal appears on the screen.

The AND gate 22 that short-circuits terminals A and c of the changeover switch 28 conducts, and the AND gate 24 shuts off the cathode B.
A dot hatch signal will appear on the wire tube. If you want to change the width of the horizontal line, for example, double it, use the fifth
The circuit shown in the figure can be used. That is, if the horizontal pulse of FIG. 3a is applied to the flip-flop 31 and frequency-divided by 112, a pulse with a width of two horizontal periods can be obtained from the shift register, and the width of the display line can be easily changed. Furthermore, instead of the outputs of the oscillators 9 to 14, the frequency of the color subcarrier doubled may be used. In this case, the input of shift register 15 and flip-flop 1
If a frequency dividing circuit of 112 is installed in front of the set input terminal of 7, ±=140r1s (F5. is a color sub 2f,
It is possible to obtain an output whose width is an integer multiple of the width of the pulse (c carrier frequency).

Shift register 15, flip-flop 17,
A conventional device corresponding to the 0R gate 16 includes, for example, a counter 32, gates 33 and 34, inverters 34 and 35, and an 0R gate 36, as shown in FIG.
By using a shift register in place of the counter 32, the gates 33, 34 and inverters 34, 35 can be replaced with one flip-flop, thereby simplifying the configuration.

As described above, the signal generating device of the present invention has a relatively simple configuration compared to conventional devices, and furthermore, the display width can be easily changed freely, so it has high industrial value. It is something.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a television receiver including a pattern signal generator according to the present invention, FIG. 2 is a block diagram of a pattern signal generator according to an embodiment of the present invention, and FIGS. FIG. 5 is a block diagram of a portion of another embodiment of the present invention, and FIG. 6 is a block diagram of a main part of a conventional pattern signal generating device. 8... Pattern signal generator, 15, 19... Shift register, 17, 21... Flip-flop, 16,
20, 23, 26...0R gate, 18, 22, 24
...AND gate, 29, 25...inverter.

Claims (1)

[Claims] 1. A first clock pulse generating means that is controlled by a horizontal pulse and generates a clock pulse whose repetition frequency is higher than the repetition frequency of the horizontal pulse; a first two stabilizing means is provided which is restored by the first two stabilizing means;
a first shift register which receives the output of the stabilizing means and its own output as input signals and further receives the output of the clock pulse generating means as a clock pulse; a second clock pulse generating means which generates the same frequency or a frequency divided thereof as a clock pulse; and a second clock pulse generating means which is driven by the vertical synchronizing signal and which is reset by the clock pulse of the second clock pulse generating means. 2, a second shift register which receives the output of the second bistable means and its own output as input signals, and further receives the output of the second clock pulse means as a clock signal; A pattern signal generating device characterized in that it produces a dot hatch or a cross hatch on a cathode ray tube using the output of a shift register.