JPS5826213B2 - Pulse detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse detection circuit, and particularly to a circuit that detects only pulse signals having a predetermined pulse width.

In a television system, a video signal obtained by an image pickup tube to display a color image is converted into a so-called composite video signal containing luminance information and color information, and a carrier wave is transmitted by the composite video signal. A modulation method is used.

A synchronizing pulse signal for synchronizing horizontal scanning and vertical scanning on the transmitting side and the receiving side is included in the composite video signal at predetermined intervals.

When reproducing video, a synchronization signal is separated from the composite video signal by a synchronization separation circuit and used for synchronization of horizontal scanning and vertical scanning.

However, in the past, pulse noise signals were mixed into the synchronization pulse signal output from the synchronization separation circuit due to fluctuations in the reference level of the composite video signal and noise, so stable synchronization was not performed and the reproduced image was disturbed. This resulted in deterioration of image quality.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a novel pulse detection circuit that removes pulse signals having a predetermined width or less from a series of pulse signals having various pulse widths.

Preferred embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of the configuration of an embodiment of the present invention.
is a signal input terminal, and the above-mentioned synchronous pulse separation circuit is connected to this input terminal.

2 is a shift register that provides a delay longer than the pulse width to be removed; 3 is a pulse signal rising edge detection circuit;
It is composed of an AND element flip-flop circuit.

4 is a counter having a predetermined counting time longer than the pulse width to be removed; 5 is a pulse signal fall detection circuit, which is composed of a NAND AND element flip-flop circuit.

6 is an AND element that is connected to the output side of the shift register 2 and allows the output from the shift register 2 to pass in response to a predetermined count output signal of the counter 4; 7 is an AND element that connects the count output signal of the counter to the output of the shift register 2; This is a flip-flop circuit that holds the signal until the falling edge of the signal.

A clock pulse generator 8 provides a synchronizing signal for the shift register 2, the rising edge detection circuit 3, the counter 4, and the falling edge detection circuit.

FIG. 2a shows the synchronizing pulse signals output from the above-mentioned synchronizing pulse separation circuit and reaching the signal input terminal 1, including the horizontal synchronizing pulses P1. P2 is the pulse width n1τ.

It has a repetition period (nl + n2) τ, as shown in Fig. 2a.
In this case, the above-mentioned pulse noise signal Pn was mixed into the synchronization pulse P2, and as a result, the horizontal scanning synchronization became unstable and the reproduced image was disturbed.

However, nl t n2 is an integer, and τ is a basic unit time.

Figure 2 and c are shift register 2 and AND, respectively.
The signal output from element 6 is shown.

Next, the operation of this embodiment will be explained with reference to FIG. 1 and FIGS. 2a, b, and c.

When an H level signal with a pulse width of n2τ is input to the signal input terminal 1 during the first period of the clock pulse, it is stored in the shift register, and the signal is transferred bit by bit to the output side in synchronization with the clock pulse.

Then, in the n-th period of the clock pulse, the pulse signal stored in the shift register 2 is delayed by the time n, τ and is output as shown in FIG. An H level voltage is applied to the input for a period n2τ corresponding to the input pulse width.

On the other hand, the rising edge detection circuit 3 detects the rising edge of the human pulse at the time when the H level pulse signal is input, that is, in the first period of the clock pulse, and the output of the detection circuit 3 changes from the H level to the L level only when the rising edge of the pulse is detected. This level change is transmitted to the preset terminal 4a of the counter 4.

At the same time, an H level signal is applied from the signal input terminal 1 to the clear terminal 4b of the counter 4 in the first period, so the counter 4 starts counting in synchronization with the clock pulse.

Then, one carry signal is output from the output terminal 4c every n cycles of the clock pulse.

That is, the counter 4 outputs the carry signal after a time delay of n, τ required for counting n clock pulses from the rising edge of the input pulse, and this carry signal is input to the S input terminal of the R-S flip-flop 1.

Therefore, after the n-th period, the output of the R-8 flip-flop 7 to the other input of the AND element 6 is held at H level, and as a result, for the period n after the n-th period of the clock pulse.
The H level output signal corresponding to the input signal from the shift register 2 for 2τ becomes the output signal of the AND element 6 as it is.

Since the output of the shift register 2 is inverted from the H level to the L level in the subsequent n+n2 period of the clock pulse, the falling edge detection circuit 5 detects the falling edge of the pulse in the n+n2 period.

In other words, the output of the fall detector 5 changes from L level to H level only when the fall of the pulse signal input to the detector is detected, and this level change is caused by the R-S flip-flop 7.
The output of the R-8 flip-flop 7 becomes L level after the (n+n2)th cycle of the clock pulse.

Therefore, the output of the AND element 6 becomes L level, and the L level
The level continues for a period n1τ without input pulses.

In this way, the counter 4 starts counting clock pulses in coincidence with the signal input to the shift register 2, and an input signal pulse having a width equal to or longer than the predetermined count n hours is extracted.

Next, as shown in FIG. 2a, a horizontal synchronizing pulse is generated.

A case in which a signal in which a noisy pulse Pn having a time width narrower than n and τ is input to the input terminal 1 will be explained.

It is assumed that the horizontal synchronizing pulse P2 is input in the first period of the clock pulse.

In other words, an L level signal is input to the input terminal 1 in the first period, but a noisy pulse signal Pn is input to the shift register 2 in the second period after the (1) clock period.

Therefore, the counter 4 starts counting through the same process as described above, but in the subsequent clock cycle, the noisy pulse signal Pn shifts to the L level, so the counter 4 stops counting.

Until the next H level pulse signal is input to the signal input terminal 7, the counter 4 stops counting and does not issue a carry signal.

For this reason, the output of the R-8 flip-flop 7 is held at L level, so the noisy pulse signal Pn output from the shift register 2 is not output from the AND element 6 and ends up at the third
As shown in FIG. C, the noisy pulse signal Pn is removed from the horizontal synchronizing signal.

Note that in this embodiment, the number of H level pulse signals included in the synchronization pulse is one, but the present invention is not limited to this, and even if a plurality of noisy pulses are included in the synchronization pulse, the present invention is not limited to this. It is obvious that it is possible to remove.

As is clear from the above description, the pulse detection circuit according to the present invention can detect only pulse signals of a predetermined width with a simple circuit configuration, and is therefore extremely useful for use in color image reproduction circuits and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, and FIG.
Figures a, b, and c are timing charts. 1: Signal input terminal, 2: Shift register, 3: Pulse rising detection circuit, 4: Counter, 5: Pulse falling detection circuit, 6: AND element, 7: R-S flip-flop, 8: Clock pulse generator.

Claims (1)

[Claims] 1 Equipped with a shift register that sequentially outputs an agile signal that delays a human input signal by a predetermined period, and clears the counted value of a separately provided counter by the rising edge of the input signal, and clears the counted value of a separately provided counter by the rising edge detection signal obtained by the rising edge detection circuit of the input signal. The counting operation of the counter is started, and after a predetermined counting operation is completed, the gate circuit connected to the output terminal of the shift register is opened and a signal is taken out from the shift register, and the input signal provided at the output terminal of the shift register is opened. The gate circuit is closed by the fall detection signal obtained by the fall detection circuit, and a pulse signal having a width determined by the delay time given to the input signal by the shift register and the count value of the counter is selected and extracted. A pulse detection circuit featuring: