SU1529282A1 - Method and apparatus for detecting frequency- and phase-modulated signals of reproduction of digital magnetic record - Google Patents

Abstract

The invention relates to the accumulation of information and makes it possible to reduce the detection error at an uneven speed of movement of the magnetic carrier by increasing the tolerance for changing the speed of movement of the magnetic carrier. Two sequences of delayed sync pulses are formed from the selected sync pulses, the first of which, together with the selected sync pulses, coincide with the end and the beginning of the backlight pulses of information symbols, and the second forms a sequence of sync pulses when a drop signal is present. The first frequency divider, the second counter, the second frequency divider, the fourth and fifth And elements, the sixth And element, the third counter, the second decoder, and the delay element are entered into the device for performing the method. Il 2

Description

The invention relates to the accumulation of information, in particular, to methods and devices for detecting frequency-and-phase-fueled playback signals of digital magnetic recording.

The aim of the invention is to reduce the detection error when changing the speed of movement of the magnetic recording medium.

Fig, I shows the block diagram of the device; in fig. 2 - time diagrams of his work ..

The proposed method is that the reproducible signal is amplified, filtered and exported (Fig. 2a). From the rectified signal, the first pulse sequence is formed, corresponding to the extra-: real signal values (Fig. 26), the second pulse sequence, corresponding to fixed signal levels (Fig. 2c). Pulses (Fig. 2d) are formed from the first and second pulse sequential, corresponding to the output mode, the signal with a duration equal to the interval between the pulses of the first sequence (Fig. 2b) corresponding to the first extreme values of the signal after the beginning and end Signal loss mode. In this case, the fallout mode corresponds to a state where, if there are fflys in the first sequence in the second sequence, there are no pulses.

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The signal of delay (Fig. 2d), corresponding to the fallout mode, is delayed. For this, two stable high frequency pulse sequences are formed, whose frequencies are referred to as 3/4. The lower frequency F / 4 measures the interval in each period of the separated sync pulses (Fig. 2c), the code of the measured interval (Fig. 2y) in the subsequent period of the sync pulses is counted by the frequency F / 3 (Fig. 2f). Of the last counts in. each period of the pulses -, (Fig. 2x) form a sequence of delayed sync pulses in 3/4 of the interval between the two last sync pulses of the output sequence of the selected sync pulses (Fig. 2c). The beginning and end of the signal — the step (FIG. 2d) is shifted to the first pulse, which follows the sequence of delayed clock pulses (FIG. 2x). A straightforward (Fig. 2i) and inverse (Fig. 2o) sequence of delayed fallout signals are formed.

The code of the measured interval (FIG. 1U) in the next period of the clock pulses (FIG. C) is counted by the frequency F / 4 (FIG. 1e). From the last counted sh-pulses (Fig. 1h), a sequence of substitution sync pulses is formed.

Direct (Fig. 1e) and inverse (Fig. 1e) illumination pulses of information symbols are formed, coinciding with the beginning with the end of the selected sync pulses (Fig. 1c), and the end with the first I-pulse - in the sequence held by 3 / 4 T .. sync pulses i (Fig. 1x).

L Multiply the direct pulses of the sublight: that of the information symbols (Fig. 1e) with the pulses. The first sequential; ti (Fig. 1b). as a result, the transitions: allocate information symbols (Fig. 1i.). A fourth pulse sequence is obtained (Fig. 1g); the multiplication of inverse (inverse) pulses of illumination of information symbols (Fig. 1e) with the pulses of the first-: pulse sequence; (Fig. 1b). Form gating

impulses (fig. 1k), in which the beginning coincides with the end of the informational sim; oxen (Fig. 1i), and the end - with the first: the pulse of the fourth impulse after-; Coding (Fig. 1g),

Gating pulses (Fig. 1k) are multiplied with information symbols (Fig. 1i) and the result of multiplication (Fig. 1l) is added to the fourth pulse sequence (Fig. 1g), resulting in a fifth pulse sequence (Fig. 1m).

The forward delayed fallout pulse (Fig. 1n) is multiplied with the fifth pulse sequence (Fig. 1m). As a result of multiplication, the sync pulses (fig. P) are separated, which are not included in the backlight of the forward delayed fallout signal (fig. 1h).

The inserted sync pulses (Fig. N) are added to a sequence of substitution sync pulses (Fig. 1h), which are not included in the backlight delays of the deposited signal (Fig. 1o). As a result, a sequence of backward sync pulses (Fig. 1c) is formed, which consists of sync pulses separated from the input signal and their substitution sync pulses, which are substituted when the level of the reproduced signal flows below the threshold of reliable formation.

A device for detecting frequency and phase-controlled digital information signals reproduced from a magnetic carrier contains serially connected magnetic head 1, amplifier 2, filter 3 and rectifier 4, connected by an output to the first and second inputs of the first trigger 5, respectively through the formers 6 and 7 pulses by extremum :, - and signal levels, the second trigger 8, connected by the first input, to. the output of the first trigger 5, the second input through the first decoder 9 to the outputs of the first counter 10, the third trigger P., connected by the first input to the output of the first decoder 9, and the output to the first input of the first element 12, which has the second input connected to one input the second element And 13 connected to the output of the output information bus 14, the fourth trigger 5 connected by the first input to the output of the first element And 12, the third element And 16 connected by the output to the counting input of the first counter 10, the generator 17 pulses, output synchroni iruyuschuyu

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Inu 18, as well as the first divider 19 asthotes, the second counter 20, are switched on sequentially between the output of the ejiepaTopa 17 pulses and the information inputs of the first counter 10, the second divider 21 of the frequency, switched on between the output of the generator of 17 pulses and the first input of the third element H 16 , quarters 22 and Fifth 23 elements And, in which the first inputs are connected respectively to the first and second highs of the second trigger 8, and the outputs through the first element OR 24 are connected to the output clock 18, the sixth element And 25, whose first input is connected to the output data bus and to the second input of the fourth trigger 15, the second input to the output of the fourth trigger, and the output through the second LII element 26 to the second input of the fourth element And 22, the third counter 27, the second decoder 28 connected in series between the output of the second The 19 frequency generator and the second input of the fifth element And 23, the delay element 29 connected between the output clock 18 and the installation input of the second counter 20. In addition, the output of the imaging unit 6 img: pulses are extremum connected to the first input of the second And 13, the second input of which is connected to the second output of the third trigger 11 and the second input of the third element AND 16, the output of the first element And 12 is connected to the second input of the second element OR 26, the synchronization bus 18 is connected to the second input of the third trigger 11 and to the control the inputs of the first 10 and third 27 counters, and the information inputs of the third counter 27 are connected to the corresponding inputs of the second counter 20.. .

The first trigger 5 is made according to the D-flip-flop scheme, in which the first input is synchronizing, and the second input is informational.

The second trigger 8 is executed according to the D-flip-flop pattern 5 in which the first input is informational and the second input is synchronizing. In this case, the second trigger 8 has two outputs - pr - and inverse.

The third 11 and fourth 15 triggers are made according to the scheme of a non-tactile 1-K-flip-flop triggered by the back front (decay) of the pulse.

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First 10, second 20 and third 27 counters can be binary counters with the same number of bits. The number of bits is determined by the clock cycle and the filling frequency input to the counting input of the second counter 20. The first 10 and third 27 meters have control inputs connected to the output clock 18, which at high potential puts these meters into parallel mode rewriting the input code, and at low potential - into the sequential counting mode, the synchronization inputs C, connected respectively to the outputs of the third element AND 16 and the first divider 19 of the frequency, and infor operating inputs connected to the corresponding outputs of the second counter 20. In this case, the bits of the second counter. 20 is rewritten into the first 10 and third 5 27 counters in the return code, which allows the use of counters 10 and 27 in the subtraction mode (counting the input information). The second counter 20 has an installation K-input, a connection to the delay element 29, and a synchronizing clock. C-input, connected to the output of the first frequency divider 19.

The first 19 and second 21 frequency dividers divide the high frequency generated by the pulse generator 17, so that at the output of the first divider 1S the frequency is formed with 4i-F / 4, and the frequency F-3 is formed at the output of the second frequency divider 21. .

First 9 and second 28 decoders form one of the code states, for example, all ones or zeros, at the outputs of the first 10 and third 27 counters.

The delay element 29 is connected by the input to the sync output bus 18, and the output is connected to the setup input of the second counter 20. The delay time is chosen from such conditions that before the second counter 20 is reset, its code has been rewritten on the first 10 and third third counts commandos from the synchronization output bus 18 to the control inputs of counters 10 and 27.

On the times of the xx diagrams. On figure 2 are marked: a - the highest signal

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at the output, rectifier 4; b - pulse signal generated by the shaper 6 pulses at the extremum; in - impulse signal generated by the shaper 7 pulses level. In the interval T1-TZ, a pulse signal is not generated, since the level of the reproduced signal is lower than the level of reliable formation; g - signal of loss on the exhaust of the first trigger 5; d, e - forward and inverse pulses of illumination of information symbols, generated at the outputs of the third trigger. eleven; W - synchronizing. impulses allocated at the output of the first element AND 12 | "- information symbols allocated at the output of the second element And 13; k - building. pulses at the output of the fourth trigger 15 ;. l - subsynchronization pulses of the circuit are released at the output of the sixth element And 25; m is the total signal at the output of the second element OR 26, consisting of the selected synchronous pulses by the element AND 12 and the sub-synchronizing pulses at the output of the six element And 25; n, o - direct and inverse sequence of delayed fallout signals generated by the second trigger 8; p - selected sync pulses entering the illumination region of the delayed fallout signal n (a signal is generated at the output of the fourth element I 22); p - replacement pulses of sync pulses h entering the illumination region of the delayed inverse fallout signal of an o (a signal is generated at the output of the fifth element And 23); e - the signal allocated on the output synchronization bus 18, consisting in the interval TO-T1 and T4-T5 from the selected sync pulses, and in the interval T1-T4 - from the sync pulses

substitutions; t is the signal with% delayed on delay element 29; y — fill diagrams for the triggering of the second counter 20 (the maximum signal corresponds to the time before the second counter is reset to zero 20); f - diagrams for filling the triggers of the first counter 10 (the maximum signal corresponds to the complete filling of the counter); X - pulses at the output of the first decipher 9 (pulses are generated at the moment of overflow of the first counter 10); C - Filling diagrams for the triggers of the third counter 27, the Maximum signal corresponds to or the moment ne

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replenishment of the counter, or the moment preceding the rewriting of the code. The counter overflow occurs if the subsequent period of the selected clock pulses is greater than or equal to the previous one; h - pulses at the output of the second decoder 28. Pulses are generated only at the moments of overflow of the third counter 28. At the same time, the third counter 27 operates in the overflow mode and allocated in this interval in the delayed T1-T4 fallout signal pulses from the output of the second decoder 28 are fed to the output clock 18 with a constant frequency.

The device works as follows.

Reproducing with the magnetic head 1 the signal after the amplifier 2 and the filter 3 is fed to the rectifier 4, which converts this signal into a single-field one (Fig. 2a). This signal arrives at the shaper 6 according to the extremum, which forms the first pulse sequence (Fig. 26), and at the shaper 7 according to the level, which forms the second pulse sequence (Fig. 2c).

The first sequence is sent to the synchronizing input of the first trigger 5, and the second to its information input. As a result, the dropout pulses are generated at the output of the first trigger 5. (Fig. 2d), the fallout pulses (FIG. 2d) from the output of the first trigger 5 arrive at the information input of the second trigger 8, which is delayed by the clock pulses (Fig. 2x) arriving at its second sync input delays the front and rear edges of the impulse loss (Fig. 2n, o).

The formation of delayed sync pulses (Fig, 2x) is performed at the output of the first decoder 8 from the saturated sync pulses (Fig. 2e) at the output of the first element OR 24,

In this case, the selected clock pulses from the output of the first element OR 24 are fed to the output clock bus 18, as well as to the feedback circuit: to the second input of the third trigger 11, setting it to a state (Fig. 2e), which ensures the passage of the pulse sequence through third element

And 16, on the control inputs of the first 1Q and third 27 counters, overwrites the status of the second counter triggers in them in the reverse code

20, and to the installation input of the second counter 20, after delaying line 29, it wrapped this counter after completing the code rewriting process at the first 10 and third 27 counters.

The high frequency, generated by the pulse generator 17, is fed to the inputs of the first 19 and second 21 frequency dividers, which divide it by 4 and 3, respectively. The high frequency, divided by 4, measures (recalculated) the period of the selected clock pulses. The counted code of the measured period from the output of the second counter 20 in the reverse code is overwritten into the first 10 and third 27 counters. The code of the first counter 0 eo is read in the next period you

divided sync pulses with a high frequency divided by 3. At the moment of overflow of the first counter 10 (Fig. 2f), the pulses (Fig. 2x) are formed at the output of the first decoder 9, corresponding to the sync pulses delayed by 3/4 of the last. pairs of dedicated clock pulses (Fig. 2c).

The delayed clock pulses (Fig. 2x) from the output of the first decoder 9 also arrive at the first input of the third

trigger 11, set it to its initial state. The output of the third trigger 11 generates forward and backward pulses of the illumination of information symbols (Fig. 2e, e), the duration of which is equal to 3/4 of the period of the last pair of selected sync pulses (Fig. 2e).

On the second 13 and first 12 elements, And trans, the signal generated by the pulse shaper 6 by the extremum (Fig. 26), respectively, with the forward and backward pulses of the illumination of the information symbols (Fig. 2e, e). In this case, at the output of the second element And 13, connected to the output information bus 14, information symbols are allocated, and at the output of the first element 12 (fig. 2g) - synchronizing pulses (symbols).

The device self-synchronization algorithm is that, in the recorded signal structure, the frequency doubling method between two

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There may be no more than one information symbol in the synchronization symbols. By taking this into account at the output of the fourth, Trigger 15, a gating pulse (Fig. 2k) is formed, with a duration equal to the interval between the selected information characters (Fig. 2i) and the synchronizing symbols (Fig. 2g).

The gating pulse (Fig. 2k) on the sixth element And 25 is multiplied with information symbols (Fig. 2i). In set 5c operating mode, there are no pulses at the output of the sixth element And 25, and at the moment the device enters the working mode, the sync pulses (FIG. 2L), which then add to the second sync sync pulse on the second element OR 26.

At the output of the fourth element And 22, as a result of multiplying the direct sequence of delayed fallout signals (Fig. 2n) with the pulse sequence (Fig. 2m) formed by the second element of QOL 26, the synchronizing pulses (Fig. 2n) 5 are not included in the zone loss of reproduced information, which then through the first element OR 24 enters the output clock bus 18 ..

- At the output of the fifth element AND 23, as a result of multiplying the reverse sequence of delayed fallout signals (Fig. 2c) with a sequence of replacement pulses of the synchro f-pulses (Fig. 2h), the supplied sync pulses (Fig. 2p) that are passed to the output bus 18 of the clock pulses at the time when the signal is reproduced with low confidence and the device is operating 5 in the fallout mode.

Replacement pulses (Fig. 2h) are generated at the output of the second decoder 28, which in the proposed device decrypts the single state of the triggers of the third counter 27 (Fig. 2n), into which for each selected sync pulse (Fig. 2c), the state of the triggers is written in the reverse code the second counter 20 (Fig. 2y) measuring the periods of the following clock pulses.

The recorded code of each period of the selected sync pulses (Fig. 2c) is counted as a high frequency, de0

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4, In the fallout zone (Fig. 2o, interval T2-T4), the third counter 27 is always overflowed (Fig. 1c) and the replacement of the second decryptor 28 is formed on the output of the second decoder 28, with a period equal to the interval between the two last sync pulses, pronounced before the start of the fall (Fig. 20, time T2).

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Claims (1)

1. A method for detecting manipulated digital magnetic recording playback signals in terms of frequency and phase by generating time signals from the reproducible signal of reaching extremes and predetermined fixed values, generating a signal of moments of reproducing reproduction signals with a duration equal to the interval between the first extremes after the beginning and end of the fallout mode, multiplying the time points to reach extreme and fixed values and the informational and synchronizing pulses, different from the fact that, in order to reduce the detection error when changing the speed of movement of the magnetic recording carrier, each selected synchronizing pulse is delayed by 3 / A of the interval between the last two synchronizing pulses, simultaneously delaying the signal of the moments of the moment before the first of the delayed synchronizing pulses, after that they form the direct and inverse signals corresponding to the instants of the appearance of the information pulses , After completion of the synchronizing pulse duration of 3/4 of the interval between the last two sync pulses, by multiplying the signal straight to the signal time points. . reaching extreme values form selected information pulses, simultaneously multiplying inverse signals with a time signal reaching extrema values, selected information pulses multiplying pulses generated from the end of the selected information pulses to the first pulse of the result of multiplying inverse signals. 12 0 five from 5 0 five 0 five and the result of the multiplication is added to the result of the multiplication, inverse signaling, after which, according to the result of multiplying the result of the summation with the delayed selected synchronizing pulse, the extracted synchronous pulses are formed. 2, An apparatus for detecting frequency and phase manipulated digital magnetic recording playback signals, comprising a series-connected magnetic head, amplifier, filter and rectifier, connected via an output. pulses by extremum and signal levels to the inputs of the first trigger connected by the output to the first input of the second trigger connected by the second input to the first input of the third trigger and to the outputs of the first counter, the first element I connected to the inlet by the first input the output of the third trigger and the output to the first input of the fourth trigger, the second element And connected by the first input to the output of the pulse shaper by the extremum, the third element And connected by the output to the counting input of the first A counter, pulse generator and information and synchronization bus, characterized in that, in order to reduce the detection error when the speed of movement of the magnetic recording medium is changed, the first and second frequency dividers, the delay element, the second and third counters, the second decipher are entered into it , the fourth and sixth elements And the first and second elements OR, and the pulse generator is connected through the first frequency divider to the counting inputs of the second and third counters and through the second frequency divider to p to the left input of the third element And connected by the second input to the output of the third trigger and the second input of the second element And connected by the output to the data bus, the second input of the fourth trigger and the first input of the sixth element And connected by the second input to the output of the fourth trigger and output to the first input of the second the OR element connected by the second input to the output of the first element AND connected by the second input to the output of the pulse former at the extremum Mj, while the third trigger is connected by the second input to the sync niziruyuschey bus and via a first OR element - to the outputs of the fourth and fifth AND gates, the first inputs connected to the outputs of the second flip-flop and a second input - to the outputs respectively of the second OR gate and a second decoder coupled to inputs of the output I. the third meter connected by the control input to the output of the first one. the OR element, the control input of the first counter and the input of the delay element connected by the output to the setup input of the second counter, connected by outputs to the information inputs of the first and third counters. Phi. i