SU1529285A1 - Device for checking errors in multichannel equipment for magnetic recording - Google Patents

Abstract

The invention relates to instrumentation, in particular to a magnetic recording technique, and can be used in the built-in means of monitoring multichannel digital magnetic recording apparatus. The purpose of the invention is to reduce the error of tolerance control of errors of multi-channel magnetic recording equipment and reduce the time of control. Introduction of the third and fourth inverters 8 and 9, the trigger 18, as well as the second playback buffer register 14, the adders block 22, the error register 23, the gating block 24, the channel error counter block 25 and the switch 26, the total error allocation block 19 the third shift register 28, the second 29, and the third 30 adders and the gating element 31, as well as the corresponding connections between the elements, allow for a one-to-one comparison of each reproduced column fragment of the recorded in the multi-channel block 1 of the magnetic recording of the test sequence with the corresponding reference control fragment, formed element-wise and synchronously with the reproducible sequence of pseudo-random signals in the process of total error control of all channels. Simultaneous monitoring of the errors of each channel and total errors and their indication reduces the error in the result of the tolerance control of the multichannel magnetic recording equipment and shortens the monitoring time. 1 il.

Description

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its fourth and fourth overblockers 8 and 9, trlgger 18, as well as sequentially connected second playback buffer register 16, adder block 22, periicTiia 23 errors, gating unit 24, block 25 channel error counters and switch 26; the introduction in block 19 of the total error allocation of the third shift register 28, the second 29 and third 30 adders and the strobing element 31, as well as the corresponding inter-11 links; the elements allow for a one-to-one comparison of each reproduced column to an fragment recorded in the multichannel magnetic recording unit 1 test sequence with the corresponding reference control fragment, form a 1.1m element-wise and synchronous with the reproducible sequence of pseudo-random signals in the process total go error control of all channels. Simultaneous monitoring of the errors of each channel and total errors and their indication reduces the error in the result of the tolerance control of the multichannel magnetic recording equipment and reduces the monitoring time, 1 sludge.

The invention relates to instrumentation, in particular to a technique of magnetic recording, and can be used in the built-in means of controlling multichannel digital magnetic recording equipment.

The purpose of the invention is to reduce the error of the result of tolerance control of errors of multichannel magnetic recording equipment and reduce the time of control.

 The drawing shows the structure - I nal the scheme of the proposed device. The device contains a multichannel-i HLrft magnetic recording unit 1, a clock I BbDi generator 2, a shaper 3 code I I 5 the first 4 and second 5 shift registers, the first 6, the second 7, the third: 8 and the fourth 9 inverters, the first 10 and second 11 frequency dividers, buffer register 12 records, first 13 and second l4 back-up buffer registers, phase detector 15: 16 n frequency filter, J-controlled Heater 17, trigger 18 block 19 of total error allocation, total error counter 20, indication block 21, adder block 22, 23 error register, strobiro block 24 Ani unit 25 channel counters oshi side and the switch 26,

The total error allocation unit 19 includes the start node 27, the third shift register 28, the first 29 and the second 30 adders (modulo two), and the gating element 31.

The output of the clock generator 2 is connected to the clock input of the first shift register 4 and to its information

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via the shaper 3 of the code, and through the first inverter 6 and the first frequency divider 10 connected in series to the control input of the parallel input of the information of the buffer register 12 of the record connected between the outputs of the bits of the first shift register 4 and the information inputs of the multichannel magnetic recording unit 1, the input the recording clock signal of which is connected via the second inverter 7 to the output of the first frequency divider 10, and the output of the playback clock signal to the first input of the phase detector 15 and to the control input laziness parallel input information of the first buffer register 13 reproducing bits which inputs are connected to data outputs of a multichannel reproducing magnetic recording unit 1, and outputs bits - bits to the inputs of the second shift register 5 and the bits to the inputs of the second buffer register 14 reproduction. The output of the phase detector 15 through the low-pass filter 16 is connected to the input of a voltage controlled oscillator 17, the output connected to the clock input of the second shift register 5, to the input of the second frequency divider 11 and to the first clock input of the block 19 total error allocation, and from the second clock input and the clock input of the trigger 18 through the third inverter 8,

The high-order output of the second frequency divider 11 is connected to the second input of the phase detector 15 and through

the fourth inverter 9 is with the control input of the parallel input of information of the second playback buffer register 14 and with the input of the gating unit 24.

The output of the transfer pulse of the second frequency divider 11 is connected to the control input of the error register 23, which is parallel in water, and controlled by the input of the second shift register 5, the output of which is connected to the information input of the trigger 18, the output connected to the information input of the block 19 .

The outputs of the bits of the second buffer register 14 playback are connected to the first inputs of the adders (on

 5 denie and noise-resistant channel coding in accordance with the selected recording method. The playback system of block 1 performs correction and signal shaping.

module two) block 22 adders, when reproducing, a clock signal.

than the second input of the first of these adders and the second inputs of the remaining adders of block 22 are connected respectively to the output of the first adder 30 of block 19 of the total allocation of column irregularity (in parallel and to the outputs of bits of the third code) with the accompanying each shift register 28 this block. column sync pulse. In the same

The outputs of the block 22 of adders are connected with the inputs of the bits of the error register 23, the outputs of which are connected to the signal Q. the number of playback channels is equal to the input inputs of the block 24 of the stroiro number of recording channels, i.e. eight, vani, outputs connected to the counter; the Shaper 3 of the code forms a counter signal in the form of a pseudo-random

temporary alignment of the string, as well as about} error and error correction. The recording information signals are fed to the input of block 1 as post-view, the playback signals are formed at the output of block 1, while

channel errors, the bit outputs of which are connected to the corresponding first groups of inputs of the switch 26, the second group of inputs, which are connected to the bits of the counter of the total error 20, and the switch outputs are connected to the inputs of the display unit 21.

In block 19, the total error allocation, the first clock input is connected to the synchronization input of the start node 27 and to the gate input of the gating element 31, the output of which is the output of block 19, connected to the counting input of the total error counter 20. The second clock input of block 19 is connected to the clock input of the third shift register 28, whose information input is connected to the output of the start node .27, and the outputs of two corresponding bits to the inputs of the first adder 29,

The output of the adder 29 is connected to the first signal input of the start node 27 and to the first input of the second adder 30, the second input of which

and the second signature input of the launch node 27 is connected to the ish input of the block 19, and the output of the second sum-j of the torus 30 is connected to the signal input of the gating element 31.

Multichannel magnetic recording block 1 contains an input parallel recording system (for example, the number

: channels and, respectively, recording tracks is equal to eight), full speed; there is a powerful introduction to the information signal of each channel, special channel markers to eliminate playback skew, and noise-resistant channel coding in accordance with the chosen recording method. The playback system of block 1 performs correction and signal shaping.

playback, clock signal.

the columns (in a parallel code) with the sync pulse accompanying each column. In the same

temporary alignment of the string, as well as about} error and error correction. The recording information signals are fed to the input of block 1 as a number of playback channels equal to the number of recording channels, i.e. eight, the Shaper 3 code generates a test signal in the form of a pseudo-random

the form of the reproduced signals at the output of block 1, while

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sequences of symbols and contains (for an 8-channel system) 11 - bit shift register, the outputs of the 9th and 11th bits of which are connected through a modulo two modulator to the information input of the register, while the clock input and output of this register are respectively, the input and output of the shaper. The registers 4, 5, 12, 13, 14, and 23 are 8-bit, and the register 28 is 11-bit bits (since it must correspond to the code-forming shift register of the imaging unit 3 codes). Frequency dividers 10 and 11 have a division factor corresponding to the number of channels of block 1 (in this example, equal to eight).

The start node 27 can be performed, for example, containing a button connected in series (these elements in the block diagram are not disclosed and not marked), two triggers, the output of the second is connected to the control input of the electronic switch, the output and the first and second inputs of which are 0

They are respectively output, first-1-1.1 m and the second signal inputs of i-i 27 start. The button output is connected to the 1C setup input of the first trigger, and the clock input to the second trigger input is the sync input of the start node 27. In the presence of a control signal at the output of the second trigger, the electronic switch skips the output of the start node 27 from the second input of this evil. When a button is pressed, the output of the first shift register 28 is received by the output of the first shift register 28 (dm} um forming the control test sequence). . The gating element 31 is an element with a second inverse input (a test input), Block 21 may contain digital indicators or may be made on LEDs, with error indications, respectively, in either binary or binary code.

Gating unit 24 consists of axial elements. And, the second inputs of which are connected ii are connected to the input gate of this block.

The block to 25 contains eight anal error counters, and the switch 26 is a switch that can alternately connect the outputs of the bits of the counter 20 total errors shee of the counter of the 25 channel error switches to the outputs of the display unit 21.

The device works as follows.

I The shaper 3 codes generates an ij-ecTOBfatfi signal, in the form of a pseudo-random sequence of characters, which is sequentially entered into the first shift register 4 with the frequency of the act generator 2 (for example, with a frequency of 8 MHz). The signals of the clock generator 2, the controlled voltage generator 17, as well as the synchronization signals of recording and reproducing have the form of a pulse voltage of 4ndr.

The output signal of the form-E | code 3 code is written to the first shift register | istr 4 along the positive edge of the clock pulses of the FJaTopa 2 gene. On the same front, information is shifted in the code generator Former 3 and Because of the delay in its operation, the value of | a new bit at its output at

is after the previous bit has already been written to the first shift register 4. After every eight clock cycles of the output of the clock generator 2, a positive voltage drop is generated at the output of the first frequency divider 10, which carries out parallel recording of all eight bits of the first shift register 4 to the buffer register 12 of the record, with a delay of half a contact after the next shift of information in the register 4. Thus, in the buffer register 12 of the record a column of the record is formed, i.e. a parallel code (fragment) of test information, which is recorded on a magnetic recording medium (not shown) in the multichannel magnetic recording unit 1, respectively, in eight tracks.

The write column is written by the write pulse with a half-period delay relative to writing to the buffer register 12 the contents of the first shift register 4, This delay is provided by the second inverter 7, the frequency of the write clock pulses is 1 MHz.

The structure of each recording column is an 8-bit fragment of a pseudo-random sequence, and the signal recorded on each carrier track is also pseudo-random, but its code-law is different from the primary test signal. Thus, the field of control data recorded on a carrier (magnetic tape) represents the placement of a pseudo-random signal both along the tape (in rows) and across it (in columns), which most closely corresponds to the actual conditions of operation of a multichannel digital magnetic recording equipment. .

The reproduced column with the help of its playback clock (on its positive edge) is written to the first playback buffer register 13, and the clock signal (sequence of clock pulses) playback with a frequency of 1 MHz is also fed to the first input of the phase detector 15, which together with the 16 low-pass filter, controlled voltage generator 17 and the second frequency divider 11 form a frequency multiplier with phase-locked loop. The frequency of the signal at the output of the generator 17 is 8 MHz and is equal to the frequency of the clock generator 2, and the frequency of the signal at the output of the frequency divider 11 (at the output of its higher bit and at the output of the transfer pulse) is 1 MHz.

Parallel recording of the contents of the first playback buffer register 13 to the second shift register 5 is delayed relative to the positive edges of the output signal of the second frequency divider 11 and the playback clock exceeding the phase error between these edges, and linked to the positive high-frequency output edges (8 MHz a) oscillator signal 17; Delay is provided by using a transfer pulse of a second frequency divider 11. This pulse has a half-period of the input signal of the divider 11 and its decline (rear negative front) forms; -; on the positive front of the input pulse of the divider. When the division factor is a multiple of two, the decline of the transfer pulse coincides with the negative level of the output signal level of the last bit of the splitter 11 and the transfer pulse is located midway between the positive differences of the output signal of this splitter. In this case, the parallel recording of information into the second shift register is made with a delay of about half the period of following the playback clock on their positive fronts. The transfer pulse includes a parallel input mode in the register 5 and overlap. (approximately 20–30 inconsistent) corresponding to the positive difference in the output levels of the voltage controlled oscillator 17, at the moment of its occurrence, the write to this register occurs at the clock input of the shift register 5.

In the absence of a transfer pulse at the control input of the second shift register 5. This register operates in the sequential shift mode along the positive fronts of the output signal of the generator 17, and the initial

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pseudo-random follower auste information.

The output information of the second shift register 5 is overwritten through a poltakt into a trigger 18 that the clock signal of the generator 17 is inverted in the third inverter 8, and then goes to the block 19 of the total section opblock. the third shift register 28 and the first adder 29, the Comparison is carried out modulo two in the second adder, the output of which trobiruets second half-wave clock signal on the element 31, the output of which on schetnp input of the counter 20 receives the total error error pulses.

Before starting the control, the shaper of the control pseudo-random sequence (register 28 and adder 29) must be entered into synchronism with the reproducing sequence.

To do this manually (operator) using the start node 27, the information input of the third shift register 28 is given for some time (this connection is shown by a dotted line in the image {P and element 27 in the block diagram) the reproduced signal (from the output of the trigger 18) until the flow at the output of the block of total error allocation does not cease to form, which occurs after the filling register 28 is filled with reproducible information. Switching the input information signal of register 28 is performed The distance between the moments of information shift in it. After entering block 19 into synchronism, the counter 20 total errors and channel error counters of block 25 are zeroed out and the device is ready for error control mode,

In the middle of the interval between the points of input of the reproduced information in the first buffer register. 13, its contents are overwritten in the second playback buffer register 14, the output information of which, i.e. this column is bitwise the bottom (per channel) is compared

no Ho / iyjiio two in block 22 adders with the corresponding control column. This column by the time of formation of the output transfer pulse of the second frequency divider 11 is completely formed in the third shift register 28, taking into account that the first bit of this column will be at the output of cy f-29, i.e. on the information entry of this register. At this point, the transfer pulse from the splitter 11 is fed to the input of the control for parallel input of the error register 23, on the leading edge of which the output signals of the error of the adder block 22 are written to the register 23.

The formed channel error pulses are performed in block 24 by gating the error signals by the second half-wave output signal of the higher bit of the second frequency divider 11, Impulse) channel errors are counted by the corresponding counters of block 25,

After completion of the monitoring process, its result (total reliability) is determined by the total error counter 20 and the transmitter 21, and the reliability of the zapgsi-reproducing on individual channels (tracks) is performed by alternately connecting the switch 26 to the inputs of the display unit 21 of the meter outputs display. channel error for block 25,

Reducing the error tolerance error control of multichannel magnetic recording equipment is achieved by performing a bitwise (channel-by-channel) comparison of the reproduced column-fragment of the recorded test sequence with the corresponding reference fragment of the control pseudo-random sequence generated by element-by-element and synchronous with the reproducible sequence in the total process . all channels) error control.

Simultaneous monitoring of total and per channel reliability also reduces the monitoring time in the process of performing setup, repair, and 1 routine maintenance with magnetic recording equipment, since in the case of obtaining unsatisfactory results in total reliability, the proposed device is 1529285

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It allows you to immediately determine the channel with low confidence, without additional time-consuming cycles to re-monitor errors of individual g (hardware channels).

Claims (1)

Invention Formula An error control device for multichannel magnetic recording equipment containing a multichannel magnetic recording unit, a clock generator, an output connected to an input of a code generator, a clock input of the first shift register and a buffer register connected between the bit outputs of the first through the first inverter with the input of the first frequency divider shift register, information input connected to the output of the driver codes, and information inputs of the multi-channel magnetic recording unit, the input sync signal The recording of which through the second inverter is connected with the output of the first frequency divider, also connected to the control input of the paraple data entry of the write buffer register, the play buffer register connected between the informational playback steps of the multichannel magnetic recording unit and the bit inputs of the second shift register connected in series a phase detector, the first input of which is associated with the output clock signal of the reproduction of the multichannel block of magnetic recording and with the input of control by parallel input of the buffer playback register, a low-pass filter, a voltage controlled oscillator and a second frequency divider, the output of the last bit of which is connected to the second input of the detector, and the output of the transfer pulse from the control input of the second shift register, the clock input of which associated with the output of the voltage controlled generator and with the clock input of the block of the total error allocation, the output connected to the input of the cyMMapHbLx error counter, and the display unit that differs in that, in order to reduce the error of the result of the tolerant error control of multichannel magnetic recording equipment and time monitoring, it introduced the third and fourth inverters, a trigger connected between the output of the second shift register and the information input of the total error error block, the second clock input of which and the trigger input of the trigger through the third inverter is connected to the output of a voltage controlled oscillator, as well as a sequentially connected second playback buffer register, block adders, an error register, the input control input input of which is connected to the transfer pulse output of the second frequency divider, a gating unit whose input gate and the input control input input of the second replay buffer register are connected via the fourth inverter to the output of the last bit second frequency divider unit ten 15 20 total errors, the total error error block contains the third shift register, the information input connected to the output of the start node, the clock input to the second clock input of the sum error selection block, and the outputs of the two corresponding bits to the inputs of the first adder. the output to which is connected to the first inputs of the start node and the second adder, the second input of which is connected to the second input of the start node and its information input. Block of the total output error output - with the signal input of the gating element, the gate gating which is connected to the synchronization input the start and with the first clock input of the total error selection battery, the output of which is the output of the gating element, the second inputs of the adders of the adder block are connected respectively to the output channel error counters and commutator 25 of the first adder block allocation the torus, the outputs connected to the inputs of the display unit, and the second group of inputs - with the outputs of the bits of the counters total errors, the total error block contains the third shift register, information input connected to the output of the start node, a clock input to the second clock input of the total error allocation block, and the outputs of the two corresponding bits to the inputs of the first adder. the output of which is connected to the first inputs of the start node and the second adder, the second input of which is connected to the second input of the start node and the information input of the block of total error allocation, and the output of the input signal of the gating element, the gate input of which is connected to the synchronization input the start node and with the first clock input of the block of the total error allocation, the output of which is the output of the gate element, the second inputs of the adders of the block of adders are connected respectively to the output total errors and with the outputs of the bits of the third shift register.