SU1589417A1 - Device for data transmission and reception - Google Patents

Abstract

The invention relates to telecommunications and can be used in transceivers with pulse-width manipulation. The purpose of the invention is to increase the speed of information exchange. To achieve the goal, the second element OR 34, the third element AND 35 and the second frequency divider 36 are introduced into the device. The number of transmitted and received bits of the transmitted signal is determined by multiplexer 26, which switches pulses of three possible durations to its output. The analysis of the received signal is carried out by the decoder 12. The subscriber’s readiness to receive information is determined by the number of additional bits in the data field using the D-trigger 20 and the decoder 6. 2 Il.

Description

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BACKGROUND OF THE INVENTION The invention relates to electrical communication and can be used in pulse-width manipulation transceivers.

I The purpose of the invention is to increase the speed of information exchange.

FIG. 1 shows a structural electrical circuit of the device for transmitting and receiving data j in FIG. 2 - timing charts that explain its work |

I A device for transmitting and receiving data contains a clock oscillator 1, amplifier 2, low-pass filter 3, shaper 4 square-wave pulses, first counter 5, first de: 6, first and second RS-flip-flops 7 and 8, the first element OR 9, the first delay block 10, the second counter 20, 11, the second decoder 12, the third RS flip-flop 13, the second delay block 14, the fourth RS-flip-flop 15, the third 16 delay, 17 K10ROTKY pulses , fourth block 18 25 h; supports, first shift register 19, first D-flip-flop 20, consumer 21 And | information, first And 2 element 2, information source 23, second shift register 2 | 4, first divider 25 frequent-, first multiplexer 26, second terminal I 27, fifth block 28 delay-Qi, third counter 29, third decrypt 30, second D -trigge p 31, second ityplipcop 32 and tr. chains D-flip-flop 33, as well as the second element ИШ1 34, 1 retiy element I 35 and the second divider 36 frequencies.

A device for transmitting and receiving data operates as follows.

The first frequency divider 25, operating from the clock generator 1, generates three sequences of pulses of different durations T, T II T, arriving at the second inputs of the first-O5 13OHO multiplexer, 26. The output of the latter depends on the value of the pilot signals acting on its first and third inputs. Figure 2 (a) shows the waveform at the output of the device in the presence of transmitted information; in fig. 2 (b) - in its absence.

The shaper 17 short pulses produces a sequence of pulses that coincide in time with negative differences of the output Signal. This sequence resets the first divider 25h30

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Loads for impulses with a duty cycle of 0.5.

The data from the information source 23 in the parallel code is written to the second shift register 24. The data tracking strobe sets the third counter to zero. With the next difference (negative) from the corresponding output of the first frequency divider 25, the second D-flip-flop 31 is set to the state where the signal from the output of the fifth delay unit 28 allows (via the second And 27 element) performing a shift in the second shift register 24 and counting the number of transmitted bits by the third counter 29. In addition, the control inputs of the first and second multiplexers 26 and 32 are set to the values of the signals that provide for the formation of pulses lnostyu T and T .. Next shift occurs for each falling edge of the pulse from the output, the first multiplexer 26 during the second shift register 24. Depending on the value of the next bit, a pulse of duration T or T is formed. At the end of the transmission, the signal changes at the output of the third decoder 30 and sets the second D-flip-flop 31 to a state that enables the transfer of a combination of pulses with duration T and T or only synchronization pulses with duration T, stops shifting information in the second shift register 24 and counting the number of pulses by the third counter 29. The composition of the combination of synchronization pulses (if only one bit is additionally transmitted) of duration T, T, or T ,, depends on the state of the third D-flip-flop 33. The pulse duration wherein s (T, and T) is determined by the value of the signal at the output of the third decoder 30 and the output of the third D- flip-flop 33 connected to the third AND gate 35.

The information in the third D-flip-flop 33 is recorded on each falling edge of the pulses from the output of the first multiplexer 26 and depends on the readiness of the remote subscriber to receive. To continue the transfer, new data is recorded from the information source 23 to the second shift register 24. From the state of the D-flip-flop 33 and the value of the signal at the output of the second frequency divider 36 by two (through the third element

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And Jb depends on the formation of an additional bit in the form of a pulse of duration T

L, OR "T synchronization pulse". To increase the capacity of the device during the formation of the synchronization pulse T.j from the first frequency divider 25, the second frequency divider 36 is synchronized. It establishes a state that ensures the formation of a pulse Tz, regardless of the state of trigger 33. Due to this, a group of synchronization pulses can consist of one pulse.

The input analog signal from the communication line through the amplifier 2, the filter of the 3 lower frequencies and the shaper 4 of the rectangular pulses is fed to the blocks 5,11,19. The pulse arriving at the installation input of the second counter And allows you to start measuring its duration by counting the pulses from the output of the clock generator 1, Depending on the duration of the input pulses using the second decoder

12 are set to 1 RS-triggers

13 or 15. If the pulse duration is T, j, then both of the above mentioned trigger triggers are G, and if T is then

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only D-flip-flop 13. On the back front of the input pulse, data is shifted in the first shift register 19. The required delay is provided by a second delay unit 14. At the same time, the number of received bits is counted by the first counter 5. If at least two bits are received, then the signal from the second output, and the first decoder 6, is set to 1, the first RS-flip-flop 7, which means the Receiver is busy. data with a known fixed number of bits is set to 1 second RS-flip-flop 8. Using the first element OR 9, a signal is generated To receive is not ready, arriving at the D-input of the flip-flop 33. It is recorded by the falling edge of the D-flip-flop input 33. Signal Buffer is filled with the output of the second The second RS flip-flop 8 through the first block 10 of the delay arrives at the input of the first shift register 19, prohibiting a shift in it. At the same time he enters the consumer of 21 information. After reading the data from register 19, the second RS flip-flop 8 is set to O.

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When the synchronization pulses arrive, the first short-trigger 7 is reset to zero, the first counter 5 is set to zero, the readiness signal is received to the first D-trigger, her 20. It only occurs when there is no signal at its installation input and corresponds to completion data transmission. The required delay of the synchronization signals is provided by the third and fourth delay blocks 16 and 18. With the aid of the first element And 22, a signal K for- is generated. , ready, then arrives at the input of the information source 23 for recording in the second shift register 24 new data in the parallel code. After the end of the input pulse (during pause 20), the RS-flip-flops 13 and 15 are reset and the counting is stopped by the second counter 11. As a result, the information source 23 records the data in the second register 24 for transfer, while the transmission completion signal is present. the output of the third decoder 30 and the signal To receive ready from the output of the first D-flip-flop 20.

The availability of the subscriber receiving data from the communication line is determined by the number of additional bits received in the message field with a fixed number of bits in the data field. If the number of bits in the data field is 8 or O (in the absence of information), this is the specified number of additional bits equal to one, the total number of bits in the message field may be as follows: 0.1.8.9. Accordingly, the information on the number of additional bits is entered into the D flip-flop 20 through the second element of the RShI 34, depending on the value of the signal at the corresponding 11x outputs of the first decoder 6.

Due to the absence of pulses of duration T in the received signal, the requirements for the necessary bandwidth of the communication channels are reduced, which allows Q to increase the speed of information exchange.

Claims (1)

Invention Formula  A device for transmitting and receiving data, comprising a clock generator, a series-connected low-pass filter amplifier and a square pulse shaper, successively tel | first connected and first decryptor, first and second K8- | triggers, first OR element, first delay unit, consecutively | second second counter and second 11, third serial RS trigger and second terminal unit , the fourth RS flip-flop and the third delay block, the short pulse shaper, the fourth delay block, the first shift register, the first D-flip-flop, the information consumer, the first AND element and the second register, the sdEyg , the first frequency divider, the first multiplexer, the second element I, the fifth delay unit, the third counter and the third decoder are connected in series, the second D-flip-flop, the second Myj-px, and the third D-flip-flop, whose information input is connected to the output the first element OR, whose inputs are connected to the outputs of the first and second RS-flip-flops, the first inputs of which are connected respectively to the output of the third delay unit and to the output of the information consumer neij) BbEft and the second inputs of which are co with the output, and the first input of the first register with the motor, the second input of Kofoporo is connected to the output of shaping-rectangular pulses, ne; p-you1 | w inputs of the first counter, tr €; t eri and fourth RS-flip-flops and the second: |: o counter, the second input of which is connected to the output of the clock generator Tojjja and the first input of the first frequency divider, the second input of which the fourth short pulse driver is connected to the clock input of the third D-Trigger and the output of the first multiplexer, the first and second inputs of which are connected respectively to the outputs of the second multiplexer and the first frequency divider, where the outputs of the third and fourth delay blocks are connected respectively to the data and information inputs of the first Boiro D flip-flop, the input of the first delay block is connected to the output of the second RS flip-flop, the output of the third decoder is connected to the setup inputs of the first and second D-flip-flops and the first input of the first element is AND, the output The second element And is connected to the input of the third counter and the first input of the second shift register, the second inputs of the third and fourth RS-flip-flops are connected to the corresponding outputs of the second decoder, the output of the first D-flip-flop is connected to the second input of the first element And, the output of the fifth delay block is connected to the first input of the second element And, the information input of the second D-flip-flop is connected to a common bus, and the outputs of the information source are connected to the second inputs of the second shift register, the output of which is connected to the first input of the second the multiplexer, while the second delay block is connected to the third input of the first shift register; the first and second outputs of the first decoder are connected to the second inputs of the first and second RS-flip-flops, respectively; the output of the third delay block is connected to the second input of the first counter; with the first input of the first shift register, and the amplifier input is the input of the device whose output is the output of the first multiplexer, characterized in that, in order to increase the rate of information exchange The second element OR, the third element None of the second frequency divider, the output of which is connected to the first input of the third element AND, the second input and output of which are connected respectively to the output of the third D-flip-flop and the second input of the second multiplexer, the third input of which is connected to the third input of the first the multiplexer and the output of the p delay block whose input is connected to the output of the second D-flip-flop, the clock input of which is connected to the corresponding output of the first frequency divider and the first input of the second divider h Frequency, the second input of which is connected to the output of the first multiplexer and the second input of the second element And, the first input of which is connected to the third input of the second frequency divider, the first and second inputs and the output of the second element OR are connected respectively to the third and fourth outputs of the first decoder and the fourth block delay.