SU1721836A2 - Data transceiver - Google Patents

Abstract

The invention relates to communication technology. The aim of the invention is to increase the speed at which information is exchanged. To achieve this goal, the device contains a transmitter and a receiver of data transmitted by the method of pulse-width manipulation. Additionally, a frequency divider, a multiplexer, an RS flip-flop and a phase inverter are introduced, which provide the conversion of pulse-width manipulation into phase and vice versa. 1 il.

Description

The invention relates to a communication technique, can be used in the construction of transducers of pulse-width manipulation, and is an improvement of the invention according to the author. St. No. 1665529.

The purpose of the invention is to increase the speed at which information is exchanged.

The drawing shows a structural electrical circuit of the device.

The device contains a clock pulse generator 1, amplifier 2, low-pass filter 3, shaper 4 rectangular pulses, first counter 5, first decoder 6, first RS flip-flop 7, trigger 8 Buffer full, first element OR 9, second block 10 delay, second counter 11, second decoder 12, second RS flip-flop 13, first delay block 14, third RS flip-flop 15, third delay block 16, information consumer block 17, fourth delay block 18, first shift register 19, second D-flip-flop 20 , the second element And 21, the second element OR 22, the source of information 23, Torah register 24

shift, the first frequency divider 25, the first multiplexer 26, the first element And 27, the fifth delay unit 28, the third counter 29, the third decoder 30, the third D-flip-flop 31, the second multiplexer 32, the first D-flip-flop 33, the second divider 34 frequency , shaper 35 short pulses, third element OR 36, fourth RS flip-flop 37, phase inverter 38, third frequency divider 39, third multiplexer 40, sixth delay block 41, element EXCLUSIVE OR 42, fourth counter 43, fourth decoder 44.

The device works as follows.

A frequency divider 25 operating from generator 1 generates three sequences of pulses of different duration T1 T2 TZ received at the second inputs of the multiplexer 26. The output signal of the latter depends on the value of the control signals acting on its first and third inputs,

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The shaper 35 short pulses produces a sequence of pulses that coincide in time with negative differences in the output signal. This sequence synchronizes the frequency divider 25 counters to obtain pulses with a duty cycle of 0.5, reset the RS flip-flop 37 and set the D flip-flop 33 to a state that provides the formation of TK pulses.

The data from the information source 23 in the parallel code is recorded in the register 24. The data tracking gate sets the counter 29 to O. The next differential (negative) from the corresponding output of the frequency divider 25 D-flip-flop 31 is set to the state where the signal from the output of the delay block 28 resolves through the AND 21 element the performance of the shift of the register 24 and the counting of the number of transmitted bits by the counter 29. In addition, the control inputs of the multiplexers 26 and 32 set the value of the signals ensuring the formation of pulses Tyu T1 and T2. Next, there is a shift on each falling edge of the pulses from the output of the multiplexer 26 in the shift register 24. Depending on the value of the next bit, a pulse of duration T1 and T2 is generated at the output of multiplexer 26. At the end of the transfer, the signal changes at the output of the decoder 30 and sets the D-flip-flop 31 to the state providing the transfer of a combination of pulses T1 and TZ or only synchronization pulses of TZ, stopping the information shift in the register 24 and counting the number of pulses by the counter 29. Composition combinations of synchronization pulses (if only one bit is additionally transmitted) of duration T1 and TZ or TZ depend on the state of D-flip-flop 33. The duration of the pulses (T1 and TZ) is determined by the value of s catch at the output of the decoder 30 and the output of D-flip-flop 33, connected to AND gate 27.

To continue the transfer, new data is written from the information source 23 to the shift register 24. The state of the D-flip-flop 33 and the value of the signal at the output of the frequency divider 34 by two through the AND 27 element determine the formation of an additional bit in the form of a pulse T1 or a TK synchronization pulse. To increase the throughput of the device during the formation of the synchronization pulse TK from the frequency divider 25, the divider 34 is synchronized. It establishes a state that ensures the formation of the TZ impulse regardless of the D trigger 33 state. Due to this, the synchronization pulse group can consist of one pulse.

The output signal from multiplexer 26 is divided by divider 39, forming impulses at the output, the front of which coincides with the falling edge of the pulses at the output of multiplexer 26. This signal controls multiplexer 40, to the inputs of which are fed

0 pulses with a frequency of T1, shifted in phase. As a result, a phase shift keying signal is obtained at the output of the device, containing components with frequencies T1 and T2. Analog input signal from line

5 communication through the amplifier 2, the filter 3 and the shaper 4 is fed to the inputs of the EXCLUSIVE OR 42 element, the output of which, due to the presence of the delay unit 41, produces short impulses on the front

0 of each pulse at the device input, performing a reset in O of the counter 33. With the help of the counter 43 and the decoder 44, pulses with a duration between the T2 fronts are selected by counting the clock pulses of the generator 1.

The pulses from the output of the decoder 44 are fed to the blocks 5.11 and 19. Using the counter 11, the duration of the pause between pulses is measured by counting the pulses from the output of the generator 1. Depending on the length of the pause of the input pulses, the decoder 12 is set to 1 trigger 13 and 15. If the duration of the pause TZ, then both triggers are set

5 to 1, and if T2, then only trigger 13. On the front of the input pulse, data is shifted in register 19. A delay is required provided by block 14. At the same time, the number of received signals is counted

0 bits of counters 5. If you take at least two bits, the signal from the second output of the decoder 6 is set to 1 trigger 7, which means the receiver is busy. After receiving the entire data field with a known fixed number of bits, it is set to 1 trigger 8. From using the element OR 9, a signal is generated. To reception is not ready, arriving at the D input of the D-flip-flop 33. It is memorized on the front of the pulse arriving at the clock input of the D-flip-flop 33 from the output of the RS flip-flop 37, which is set to 1 on the rising edge T1. The buffer signal is filled from the output of the trigger 8 through the block 10 enters the input of the register 19, for 5 there is a shift in it. At the same time, it enters block 21, and also, through the element OR 36, resets the RS flip-flop 7 to zero. After reading the data from the register 19, the block 21 sets the flip-flop 8 to the initial state. After that, the signal state

The receiver is occupied only by the information consumer via trigger 8.

When the synchronization signals are received, the leading edge of the pulse from the output of block 16 through the OR 36 element performs an additional reset of the RS flip-flop 7 to 0, setting Counter O 5 received bits, recording the readiness signal to receive the D flip-flop 20. This occurs only when there is no signal on the setup input of the D-flip-flop 20 and corresponds to the completion of data transfer. The necessary delay of the signals is provided by the fourth blocks 16 and 18. The K-signal is ready from the output of the D-flip-flop and is fed to the input of the source 23 for recording new data in the register 21 in the parallel code. After the end of the input pulse (during the pause), the RS-flip-flops 13 and 15 are reset and the counting stops by the counter 11.

The availability of the subscriber who is receiving data from the communication line is determined by the number of received extra bits in the message field with a fixed number of bits in the data field. If the number of bits in the data field is 8 or 0 (in the absence of information), then for a given number of additional bits equal to one, the total number of bits in the message field may be as follows: 0.1, 8.9. Accordingly, the information on the number of additional bits recorded in the 0-flip-flop 20 through the element OR 22 depends on the value of the signal on the corresponding outputs of the decoder 6.

Due to a more rapid reset to zero of RS-flip-flop 7 on the leading edge of the pulse from the flip-flop 8, the buffer is full and the recording of information about readiness to receive D-flip-offZ3 is changed by the multiplexer 26 in the process of forming the TK pulse pause. This accelerates acknowledgment (readiness) signals and ultimately increases device throughput.

F o rumlula and z o breetn

A device for transmitting and receiving data on aut. St. No. 1665529, characterized in that, in order to increase the transmission speed during the exchange of information, a third frequency divider, a third multiplexer, a fourth RS flip-flop, a phase inverter, and the output of the square pulse former are connected to the first input of the first counter through serially connected sixth block delay

the EXCLUSIVE OR element, the fourth counter AND, the fourth decoder, the output of the square pulse generator is connected to the second input of the EXCLUSIVE OR element, the second input

the fourth counter is connected to the clock generator output, the first output of the first frequency divider is connected to the first inputs of the fourth RS trigger and the third multiplexer and the phase inverter input, the output of which is connected to the second input of the third multiplexer, the output of which is the device output, the output of the first multiplexer through the third frequency divider connected to the third input

the third multiplexer, the output of the short pulse pulse generator is connected to the second input of the fourth RS flip-flop, the output of which is connected to the third input of the first D flip-flop.

Claims (1)

Claim A device for transmitting and receiving data by ed. St. No. 1665529, characterized in that, in order to increase the transmission speed during the exchange of information, a third frequency divider, a third multiplexer, a fourth RS-flip-flop, a phase inverter, the output of the square-wave pulse former are connected to the first input of the first counter through the sixth delay unit introduced in series , the element EXCLUSIVE OR, the fourth counter AND, the fourth decoder, and the output of the shaper of rectangular pulses is connected to the second input of the element EXCLUSIVE OR, the second input of the fourth counter soy is dined with the output of the clock generator, the first output of the first frequency divider is connected to the first inputs of the fourth RS-trigger and the third multiplexer and the input of the phase inverter, the output of which is connected to the second input of the third multiplexer, the output of which is the output of the device, the output of the first multiplexer is connected through the third frequency divider with the third input of the third multiplexer, the output of the short pulse former is connected to the second input of the fourth RS-trigger, the output of which is connected to the third input of the first a D-flip-flop.