KR910008754B1 - Pcm data generator - Google Patents

Abstract

The pulse width modulation (PCM) data generating circuit is installed on a private branch exchange to test the PCM coding and decoding state of a subscriber. The circuit comprises a standard data generator (100) for generating the standard data used in PCM coding, a PCM data generator (200) for receiving the standard data, for synchronizing to the frame synchronous signal and shifting according to the bit clock signal (CLK,X) to generate the PCM data, a channel selecting unit (600) for generating the channel position selection signal to transmit the PCM data to the designated channel, a channel counter (300) for changing the channel sequentially by counting the bit clock signal, a reference channel data generator (400) for generating the reference channel by shifting the channel data transmitted from the PCM exchange unit (10) and a comparator (500) for finding channel through which the PCM data is transmitted.

Description

PCM data generation circuit

1 is a conceptual diagram according to the present invention.

2, 3 is a timing diagram according to the present invention.

4 is a detailed circuit diagram of the PCM data generation circuit 60 of FIG. 1 according to the present invention.

5 and 6 are operational waveform diagrams of FIG. 4 according to the present invention.

The present invention relates to a PCM (Pulse Code Modulation) data generating circuit that can be installed in an exchange to diagnose a subscriber.

Recently, a lot of communication using the PCM method has been developed a lot communication system accordingly. In the development process of the PCM exchange system using the PCM method, a circuit test instrument is required to check the PCM data processing process of the system.

It was configured to process continuous analog signals as digital data using a PCM coder / decoder for a conventional PCM data transmission related test. At this time, an expensive measuring instrument, which is an analog signal generator, is first required, and a subscriber diagnosis is performed by combining a separate additional circuit for converting the analog signal to PCM. Therefore, in the related art, a PCM coder / decoder for digital processing and expensive equipment for analog signal generation are required for diagnosis after completion of development of the PCM exchange system.

Accordingly, an object of the present invention is to test the amount of crosstalk and PCM coating and decoding in communication equipment and easily perform self-diagnosis without using analog equipment or PCM coder / decoder chip for subscriber diagnosis to solve the conventional problems. To provide a PCM data generator that can be applied.

In order to accomplish the above object, the present invention provides a standard data generator for counting a frame sync signal to generate PCM data (1KHZ ΦdBm) and generating standard data for PCM, and for transmitting the generated PCM data to a designated channel. A channel selector for generating a channel position selection signal in one frame, a channel counter periodically generating a predetermined pulse for the channel selection, and transmitting the generated PCM data to the assigned channel position The PCM data generation unit for transmitting the parallel value of the PCM data as a serial value, the reference channel data setting unit for generating channel data as a reference for connection with other subscribers, and the channel data output continuously generated in the channel counter unit When the same as compared with the output of the reference channel data setting unit, the channel selection determination information of the channel selector Characterized by a comparison part adapted to.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a conceptual diagram according to the present invention. In the PCM exchange apparatus 10, the frame sync (FS), the bit clock (CLK.X), the channel data clock (CLK.C; Chaner Data Clock), It is configured to require channel data (DC). The first subscriber circuit 20 and the second subscriber circuit 30 based on the third degree frame sink FS according to the signals FS, CLK.X, CLK.C, and DC in the PCM exchange apparatus 10. When a call path is formed through channel 2 (CH # 2), data transmission / reception (TXD, RXD) is performed through channel 2 (CH # 2).

That is, on the same principle, the PCM exchanger 10 simultaneously provides the signals FS, CLK.X, CLK.C, and DC to the first subscriber circuit 20 and the PCM data generation circuit 60, thereby providing the signals. When the first subscriber circuit 20 forms a communication path with the PCM data generation circuit 60, the data generated by the PCM data generation circuit 60 passes through the transmission highway HWX and passes through the PCM exchange apparatus 10. The data generated through the reception highway HWR of the first subscriber circuit 20 and passing through the transmission highway HWX of the first subscriber circuit 20 is transferred to the PCM data generation circuit through the PCM exchange device 10. It is input past the receive highway HWR. As a result, the first subscriber circuit 20 may receive a 1 KHZ, 0 dBm signal generated by the PCM data generation circuit 60, which may be received by the telephone set STN1, and the level measuring device 50 may be received. Through the measurement value is displayed to the subscriber can diagnose the status of the provided signal.

2 and 3 show waveforms of the transmission / reception data TxD and RxD according to the above-described signals FS, CLK.C, CLK.X, and DC and channel selection.

4 is a detailed circuit diagram of the PCM data generation circuit 60 of FIG. 1 according to the present invention, where 100 represents a frame sync (FS) signal input through the line 101 to a standard data generator. As the input of CLK, waveforms of FIG. 5 to be described later and sequentially generated from "1" to "8" as shown in Table 1 are generated, and one byte per frame is generated to the flip-flop 12 as a predetermined time value. It is configured to hold by.

)을 쉬프트 레지스터(13)의 A,C,E단에 연결하고 카운터(11)의 출력단(QC)을 쉬프트 레지스터(13)의 H단에 연결하며, 상기 쉬프트 레지스터(13)의 B,D,F,G단에 μ-law와 A-law를 선택하기 위한 연결단(J1,J2,J3,V1,G1)이 구성되고, 프레임 싱크(FS) 신호를 인버터(21-23)에서 반전하여 쉬프트 레지스터(13)의 로드단(LD)으로 제공하여 입력단(A-H)의 입력 데이터를 로딩하기 위해 신호로 제공되고 비트 클럭단(CLK.X)의 클럭신호를 낸드게이트(31)에 입력하고 상기 쉬프트 레지스터(13)의 클럭 인히비트단(CLK INH)의 신호를 인버터(20)에서 반전하여 낸드게이트(30)의 타단으로 입력하고 상기 낸드게이트(31)의 출력을 인버터(24)에서 반전하여 쉬프트 레지스터(13)의 쉬프팅 클럭단(CLK)의 클럭신호로 제공된다. 따라서 로드단(LD)의 신호에 따라 입력단(A-H)의 로딩된 데이터를 인버터(24)를 통해 출력되는 클럭신호에 따라 1비트씩 쉬프팅시켜 3-스테이트버퍼(41)에 입력되어 게이트단과 연결된 노드(103)의 상태에 따라 지정된 채널 시간에만 출력되어 PCM 교환장치(10)의 송신 하이웨이(HWX)로 입력된다. 그러나 상기 지정 채널 시간이 지난 경우는 상기 쉬프트 레지스터(13)의 클럭인히비트단(CLK INH)의 "하이"로 엑티브 될 때이다. 이때 3-스테이트버퍼(41)의 게이트단의 라인(103)은 "하이"가 되고, 인버터(25)의 출력이 "로우"가 되어 낸드게이트(31)는 "하이" 상태로 계속될 뿐 비트클럭단(CLK.X)의 클럭을 받을 수 없는 상태가 되어 쉬프트 레지스터(13)의 클럭단(CLK)의 입력은 없으므로 쉬프트 레지스터(13)의 데이터 출력은 없다.200 denotes a PCM data generator and output terminals Q and D of the flip-flop 12 of the standard data generator 100.

) Is connected to the A, C, and E stages of the shift register 13, and the output terminal QC of the counter 11 is connected to the H stage of the shift register 13, and the B, D, Connection stages J1, J2, J3, V1, and G1 for selecting μ-law and A-law are configured at the F and G stages, and the frame sync signal is inverted in the inverters 21 to 23 and shifted. It is provided as a signal for loading the input data of the input terminal AH by providing it to the load terminal LD of the register 13 and inputs the clock signal of the bit clock terminal CLK.X to the NAND gate 31 and shifts the shift. The clock input signal CLK INH of the register 13 is inverted by the inverter 20 and input to the other end of the NAND gate 30, and the output of the NAND gate 31 is inverted by the inverter 24 and shifted. It is provided as a clock signal of the shifting clock stage CLK of the register 13. Accordingly, the data loaded from the input terminal AH is shifted by one bit according to the clock signal output through the inverter 24 according to the signal of the load terminal LD, and is input to the 3-state buffer 41 to be connected to the gate terminal. It is output only at the designated channel time in accordance with the state of 103 and is input to the transmission highway HWX of the PCM switching device 10. However, when the designated channel time has passed, it is when the high of the clock bit CLK INH of the shift register 13 is activated. At this time, the line 103 at the gate end of the 3-state buffer 41 becomes "high", and the output of the inverter 25 becomes "low" so that the NAND gate 31 continues to be "high". Since the clock of the clock stage CLK.X is not received and there is no input of the clock stage CLK of the shift register 13, there is no data output of the shift register 13.

300 is a channel counter unit which inverts the frame sink FS in the inverter 21 and is applied to the clear stage CLK of the counters 51 and 52 and the NAND gate 32 unit of the channel selector 600. The clock of CLK.X is applied to the clock terminal CLK of the counter 51, and the inverter 26 is connected to the output terminal of the counter 51 so that the output terminal of the inverter 26 is the clock terminal of the counter 52. CLK) and the counters 51 and 52 are cleared around the frame sync FS. From this time, the counter 51 counts the clock of the bit clock stage CLK.X so that one pulse is generated every eight inputs. Is generated and applied to the clock terminal CLK of the counter 52 through the inverter 26 and counted. That is, eight clocks become a clock for one channel, and the output of the output terminal Qc of the counter 51 is inverted by the inverter 26 and counted about the frame sink FS by the counter 52. (QA-QD) is generated sequentially in the value corresponding to the channel.

Therefore, the counter 51 counts eight bit clocks to use as a clock of one channel, and the counter 52 counts the output of the counter 51, thereby counting one to 32 channel values in a frame sync (FS) period. Count until it occurs. That is, the counter 52 repeatedly counts 1-32 based on the frame sink FS.

400 is a reference data generator that receives the channel data DC from the PCM exchanger 10 and shifts the shift register 54 by the channel data clock CLK.C to set the channel to the output terminals QA-QF. This channel value is output.

The comparator 500 is a comparator unit that compares the channel data values A 0 -A 3 generated at the counter 52 of the channel data generator 300 with the channel data values B 0 -B 3 provided from the shift register 54. Compare). When the comparator 53 compares both channel values A0-A3 and B0-B3, the "high" signal is generated. The output of the frame sink FS through the inverter 21 inverts the FS of FIG. 3 and thus becomes "high" except for the synchronous pulse width section. When the "high" of this signal and the output of the comparator 52 are "high", the output of the NAND gate 32 becomes "low", enabling the 3-state buffer 41 to output the output stage of the shift register 13 ( The shifted PCM data of QH) is controlled to be supplied to the corresponding channel section in frame synchronization (FS), and the " high " signal is transmitted through the inverter 25, so that the bit clock stage CLK. The clock of X) is received and provided to the shifting clock of the shift register 13 through the inverter 24. Accordingly, the shift register 13 shifts the A-law or μ-law type data of the input terminals A-H, thereby generating PCM data from the generated PCM data to the output terminal QH. The PCM generation data is transmitted by the output of the NAND gate 32 to the transmission highway HWX of the PCM exchanger 10 through the open 3-state buffer 41 in the enabled section of the corresponding channel.

That is, the first subscriber circuit 20 of FIG. 1 communicates with the PCM data generation circuit 60 through the PCM exchange apparatus 10 through one channel (CH ^{# 1} ). First, the reference channel data setting unit 400 is performed. The NAND gate is provided in the frame synchronization (FS) section when the channel counting unit 300 provides the value of 1 channel and counts the channel based on the frame synchronization signal FS in the channel counting unit 300. The output of the 32 becomes " low " to enable the 3-state buffer 41 to set a channel for supplying the PCM data, and to receive a bit clock from the NAND gate 31 through the inverter 23 so that the inverter ( A-law or μ-law data is shifted from the input terminal AH in the shift register 13 by a bit clock inputted through 24) to generate PCM data to the output terminal QH. Transmission of the output PCM exchanger 10 via an enabled 3-state buffer 41 Supplied to New Highway (HWX).

In the shift register 13 of the data generator 200, the contact node J1 and the first power supply terminal V1 are connected to a high state, and the contact node J2 is connected to the contact node J1. And ground terminal (G1) are connected to the "low" state, the contact node (J3) and the ground terminal (G1) is connected to the "low" state, so the input terminals (A, B, C) of the shift register 13 , D, E, F, G, H) = X, 1, X, 1, X, 0, 0, X [X: Don'T Care] is specified. In the case of the A-law type PCM, the contact node J1 and the first power terminal G1 are connected to be “high”, and the contact node J2 and the first power terminal V1 are connected to the contact node. Since J3 and the ground terminal G1 are connected to be "high", the input terminals A, B, C, D, E, F, G, H of the shift register 13 are X, 1, X, 1, It is specified as X, 1, 0, X.

5 is an operation timing diagram of FIG. 4 according to the present invention, in which QA-QC is an output waveform of the output terminals QA-QC, and output terminals Q and Q are deflected based on the frame sync waveform. The output waveform of the flop 12, and FIG. 6 is a timing diagram of PCM data generation in FIG. 4 according to the present invention, and includes a frame sync FS, a bit clock stage CLK.X, channel data DC, and a channel data clock. The waveform CLK.C is shown, and the NAND gate 32 of the comparator 53 and the channel selector 600 of the comparator 500 is converted from the signal in which the frame sink FS is inverted by the inverter 21. The PCM data is generated by setting the channel by the output of the power amplifier and shifting the clock by the output of the inverter 24 in the shift register 13.

)은 제5도와 같이 출력된다. 그리고 카운터(11)의 출력단 (QC)의 출력과 디플립플롭 (Q,

)의 출력을 쉬프트 레지스터(13)의 입력단(A, B, C, E, F)으로 입력한다.Based on the above configuration, a specific embodiment of the present invention will be described in detail with reference to FIGS. 1-6, and the output timing diagram of the counter 11 will be described with reference to FIG. That is, when the frame sync (FS) signal input through the line 101 is input to the clock terminal CLK of the counter 11 and counted, the signal of the output terminal QA of the counter 11 is flip-flop 12. Is input to the clock terminal CLK, and the signal of the output terminal QB is input to the data D of the flip-flop 12 to output the output terminal Q,

) Is output as shown in FIG. The output of the output terminal QC of the counter 11 and the deflip-flop Q,

) Is input to the input terminals A, B, C, E, and F of the shift register 13.

As shown in the timing diagram of FIG. 6, the frame synchronizing signal FS is inverted by the inverter 21 and input to the clear terminal CLR of the NAND gate 32 and the counter circuits 51 and 52. The signal of the bit clock terminal CLK.C of the line 301 is input to the NAND gate 31 and the clock terminal CLK of the counter 51. The counter 51 is cleared based on the frame synchronization signal FS inverted by the inverter 21 to count the clock of the bit clock stage CLK.X, and generates one pulse every 8 counts. Channel data is generated at a predetermined counting time input to the clock terminal CLK of the counter 52. Meanwhile, the channel data clock terminal CLK.C clock inputted to the line 401 is inputted to the clock terminal CLK of the shift register 54, and the channel data DC is inputted to the line 402. When the signal is input to the output signal QA-QF and shifted according to the eight clock signals of the channel data clock terminal CLK.C, the channel data becomes a reference data value. When the value is input to the comparator 53, the comparator 53 compares the channel data output by counting the frame synchronizer FS of the counter 52 with the output channel data of the shift register 54 and outputs the same. The state is "high." When the NAND gate 32 logicalizes the "high" signal of the output terminal A = out of the comparator 53 in the "high" section centering on the frame synchronous FS through the inverter 21, "low" is obtained. Is generated and input to the clock inhibit bit CLK INH of the shift register 13 and to the gate of the 3-state buffer 41. At this time, the 3-state buffer 41 is enabled, and the enabled " low " section of the 3-state buffer 41 becomes a channel section in the frame sync FS, which is generated by the shift register 13. Data is then supplied to that channel.

On the other hand, the output passing through the inverter 25 becomes "high" and is input from the NAND gate 31. The bit clock of the bit clock stage CLK.X is received in the " high " section of the inverter 25, inverted by the inverter 24, and then input to the clock stage CLK of the shift register 13. When the signal through the node 102 has a predetermined delay by the inverters 22 and 23 and gives a load signal to the load register LD of the shift register 13, the signal is selected according to the selection of μ-law and A-law. The data and output data of the counter 11 and the flip-flop 12 are shifted in accordance with the clock of the clock stage CLK to generate PCM data. In the case of the A / μ-law PCM method, when the PCM data of the present invention and the PCM data of each prem of [2] and [3]-[8] are displayed in a table at the channel time in the frame [1], Table 1 Same as

It should be noted that the table in Table 1 replaces the contents of page 93 of CCITT Recommendation G.711, Section III.3. Since the state of the input terminals A-H of the shift register 13 is PCM data,

TABLE 1

The frame data of [1]-[8] are continuously output as shown in Table 1, and the above shows the signal for 1KHZ, ΦdBm as PCM code, and this data is actually published by CCITT (Recommendation G. 711). Also, in order to make PCM data in this way, it can be applied not only to 1KHZ and ΦdBm but also to any desired frequency, and to make data based on the calculation formula between the desired frequency and sampling frequency in the continuous generator.

The example in FIG. 6 shows an example of channel 1 (CH # 1), and the inverter 24 of the shift register 13 in the section "low" of the selected channel 1 (CH # 1) in the NAND gate 32. PCM data is generated from the output stage QH to the output stage 20 of the 3-state buffer 41 through the output stage QH.

That is, the output of the NAND gate 32 of the channel selector 600 is the channel data of the reference channel data setting unit 400 and the channel data of the channel counting unit 300 by the comparator 53 in the frame sync FS. When the comparison result of the comparator 53 is input to the NAND gate 32 so as to designate one of the positions # 1-# 8 as shown in FIG. 3 when the comparison is the same, the output of the NAND gate 32 is " Low "to enable the 3-state buffer 41, which becomes " low " at one of [1]-[8] in Table 1 above, and the PCM data generated by the shift register 13 is enabled. It is output through the three-state buffer 41 is applied to the transmission highway (HWX) of the PCM switch 10. In the PCM exchange apparatus 10, since the PCM data generation circuit 60 and the first subscriber circuit 20 are internally connected, the generated PCM data is input to the first subscriber circuit 20 through a reception highway HWR. The subscriber can listen to the signal through the handset STN1 and measure the transmitted signal through the level measuring device 50 to perform various diagnosis.

Therefore, it can be seen that the PCM data generation circuit 60 generates and provides test PCM data for the role of one subscriber circuit.

As described above, PCM digital code is generated by a simple circuit, so it is easy to apply, and because it is designed to apply μ-law and A-law simultaneously according to the PCM method, the two methods can be selected as needed. In addition, the general PCM measuring instrument has a number of channels in accordance with the PCM transmission method to consider a lot when purchasing maintenance, and when the PCM method is different, there is an advantage of eliminating the inconvenience of having to purchase equipment for the purpose again. And while using the circuit of the present invention, there is an advantage that can be applied if only the external input condition is matched, no matter how many channels in any way.

Claims (4)

The PCM switch 10 provides a frame sync (FS) signal, a bit clock signal (CLK.X), channel data (DC), and channel data clock signal (CLK.C) supplied during transmission in the frame sync period. In the circuit for generating PCM data of the PCM exchanger 10, the standard data generator 100 for generating basic data used for the PCM by counting the frame sync signal FS as an input signal; And the bit clock according to the synchronization of the frame sync signal FS by inputting the counted output of the standard data generator 100 as input data and a signal according to selection of an A-law or μ-law method as PCM data. The PCM data generator 200 generates a PCM data by shifting the signal CLK.X and outputs the corresponding channel to the channel, and transmits the PCM data generated by the PCM data generator 200 to a designated channel. Channel in Frame Synchronization (FS) Signal A channel selector 600 which provides a value selection signal, a channel counter unit 300 which sequentially generates a channel value by counting the bit clock signal CLK.X based on the frame synchronization signal FS; A reference channel data setting unit 400 for shifting the channel data DC provided from the PCM exchanger 10 to a channel data clock signal CLK.C to generate channel data as a reference, and the reference channel data PCM data, characterized in that consisting of a comparison unit 500 to find the channel to send the PCM data from the channel value of the setting unit 400 to send the PCM data to the channel selector 600 Generating circuit. The method of claim 1, wherein the standard data generator 100 grounds the input terminal AD of the counter 11, connects the frame synchronization signal terminal CLK to the clock terminal CLK, and outputs the output terminals QA-QB. The flip-flop 12 is connected to the clock terminal CLK and the data terminal D, and the output terminal Q,

) And the output terminal (QC) of the counter (11) to the input terminal of the PCM data generator (200). The counter of claim 1, wherein the channel counter unit 300 connects the inverted frame synchronization signal FS to the clock terminal CLK of the clear terminal CLR of the counters 51 and 52. PCM data generation circuit, characterized in that by connecting the inverter (26) to the output terminal (QC) of the output terminal of the inverter (26) is connected to the counter (51) to the clock terminal (CLK). The method of claim 1, wherein the PCM data setting unit 200 is connected to the input terminal (AH) of the shift register 13, the standard data generating unit 100 and the μ / A-law selection terminal (V1, G1), The frame synchronizing signal FS connects the inverters 21-23 to the load terminal LD of the shift register 13, and the bit clock terminal CLK.X is connected to the input terminal of the NAND gate 31. The output terminal 103 of the channel selector 600 is connected to a 3-state buffer 41 and a clock inbit stage CLK INH of the inverter 25 and the shift register 13. The output terminal of (20) is connected to the input terminal of the NAND gate 31, and the output of the NAND gate 31 is connected to be input to the clock terminal (CLK) of the shift register 13 through the inverter 24 And the 3-state buffer (41) is connected to the output terminal (QH) of the shift register (13).

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